32位雙重快速跳躍進位鏈六級流水線加法器Verilog的實現(xiàn)

1、32位雙重快速跳躍進位鏈六級流水線力口法器Verilog的實現(xiàn)DLUT-SOFTWARE-0819Mr Xie2011/6/28'timescale 1ns / 1ps/定義時間單位為1n s,時間精度為1ps/ 模塊名：fullAdder32/端口說明：elk:輸入的時鐘A:輸入的32加數(shù)B:輸入的32位被加數(shù)Ci n：輸入的最低位進位Cout :輸出的最高位進位 Sum：兩個數(shù)相加的和/目標器件： Veritex4系列的XC4VSX35/ 工具版本：Xilinx-ISE10.1 ISE Simulator(VHDL/Verilog) Synplify Pro9.6.2/依懶關系：不

2、依懶于其它模塊/ 創(chuàng)建日期：08:43:38 06/21/2011/創(chuàng)建人：/module fullAdder32(clk,A,B,Ci n, Cout,Sum);in put clk;/聲明clk為1位的線網(wǎng)型輸入變量in put 31:0 A; /聲明A為32位的線網(wǎng)型輸入變量in put 31:0 B; /聲明B為32位的線網(wǎng)型輸入變量，in put Cin;/聲明Cin為1位的線網(wǎng)型輸入變量output Cout;/聲明Cout為1位的線網(wǎng)型輸出變量output 31:0 Sum; /聲明Sum為32位的線網(wǎng)型輸出變量reg 31:0 Sum; /對Sum進行重新聲明為寄存器型reg

3、Cout;/對Cout進行重新聲明為寄存器型reg 30:0 C;/每一位相加時產(chǎn)生的進位reg 30:0tmpC1, tmpC2, tmpC3; /臨時變量，對進位作一個暫存reg 31:0d;/小組的本地進位reg 31:0tmpd1, tmpd2, tmpd3;/臨時變量，對本地進位作一個暫存reg 31:0t;/小組的傳遞進位reg 31:0tmpt1, tmpt2, tmpt3;臨時變量，對傳遞進位作一個暫存reg 8:1D;/大組的本地進位reg 8:1tmpD1; 臨時變量，對大組的本地進位作一個暫存reg 8:1T;/大組的傳遞進位reg 8:1tmpT1; 臨時變量，對大組的

4、傳遞進位作一個暫存reg 31:0tmpA1, tmpA2, tmpA3, tmpA4, tmpA5; 對輸入變量 A 作暫存reg 31:0tmpB1, tmpB2, tmpB3, tmpB4, tmpB5; /對輸入變量 B 作暫存reg tmpCin1, tmpCin2, tmpCin3, tmpCin4, tmpCin5;/對輸入變量 Cin 作暫存reg tmpCout1, tmpCout2;對輸出變量 Cout作一個暫存/ 第一個時鐘周期 /計算小組的本地進位d和傳遞進位t/對輸入的加數(shù)A,被加數(shù)B,低位進位Cin作一級暫存always (posedge elk) beg ind

5、<= A&B;t <= A|B;tmpAI <= A;tmpBI <= B;tmpCi n1 <= Ci n;end/ 第二個時鐘周期 /對輸入的加數(shù)A,被加數(shù)B,低位進位Cin作二級暫存/對小組的本地進位d,傳遞進位t作一級暫存/ 計算進位 C0,C1,C2/計算大組的本地進位D、傳遞進位Talways (posedge elk) beg intmpdl <= d;tmptl <= t;tmpA2 <= tmpAI;tmpB2 <= tmpBI;tmpCi n2 <= tmpCi n1;C0 <= d0 I t0&am

6、p;tmpC in 1;C1 <= d1 | t1&d0 | t1&t0&tmpC in 1;C2 <= d2 | t2&d1 | t2&t1&d0 | t2 &t1&t0&tmpCi n1;D1 <= d3 | &t3,d2 | &t3:2,d1 | & t3:1,d0;T1 <= & t3:0; /t3&t2&t1&t0;D2 <= d7 | & t7,d6 | & t7:6,d5| & t7:5,d4;T2

7、<= & t7:4; /t3&t2&t1&t0;D3 <= d11 | & t11,d10 | & t11:10,d9| & t11:9,d8;T3 <= & t11:8; t11&t10&t9 &t8;D4 <= d15 | & t15,d14 | & t15:14,d13| & t15:13,d12;T4 <= & t15:12; t15&t14&t13&t12;D5 <= d19 | & t19,d18

8、 | & t19:18,d17| & t19:17,d16;T5 <= & t19:16; t19 &t18 &t17&t16;D6 <= d23 | & t23,d22 | & t23:22,d21| & t23:21,d20;T6 <= & t23:20; t23&t22&t21&t20;D7 <= d27 | & t27,d26 | & t27:26,d25| & t27:25,d24;T7 <= & t27:24; t27

9、&t26&t25&t24;D8 <= d31 | & t31,d30 | & t31:30,d29| & t31:29,d28;T8 <= & t31:28; t31&t30&t29&t28;end/t第三個時鐘周期 /對輸入的加數(shù)A,被加數(shù)B,低位進位Cin作三級暫存/對小組的本地進位d,傳遞進位t作二級暫存/對大組的本地進位D,傳遞進位T作一級暫存/對進位部分進位C作二級暫存/ 計算進位 C3,C7,C11,C15always (posedge elk) beg in tmpd2 <= tmp

10、d1;tmpt2 <= tmpt1;tmpA3 <= tmpA2;tmpB3 <= tmpB2;tmpCi n3 <= tmpCi n2;tmpD1 <= D;tmpT1 <= T;tmpC12:0 <= C2:0;tmpC13 <= D1 | T1&tmpCi n2;tmpC17 <= D2 | T2 &tmpCi n2;tmpC111 <= D3 | T3&tmpCi n2;tmpC115 <= D4 | T4&tmpCi n2;end/t第四個時鐘周期 /對輸入的加數(shù)A,被加數(shù)B,低位進位C

11、in作四級級暫存/對小組的本地進位d,傳遞進位t作三級暫存/對進位部分進位C作二級暫存/ 計算進位 C6:4,C10:8,C14:12,C19:16,C23,C27/計算最高進位Coutalways (posedge clk) begi n tmpd3 <= tmpd2;tmpt3 <= tmpt2;tmpA4 <= tmpA3;tmpB4 <= tmpB3;tmpCi n4 <= tmpCi n3;tmpC20 <= tmpC10;tmpC21 <= tmpC11;tmpC22 <= tmpC12;tmpC23 <= tmpC13;tmp

12、C27 <= tmpC17;tmpC211 <= tmpC111;tmpC215 <= tmpC115;tmpC24 <= tmpd24 | tmpt24&tmpC13;tmpC25 <= tmpd2 5 | tmpt2 5&tmpd24 | tmpt2 5&tmpt24&tmpC13;tmpC26 <= tmpd26 | tmpt26&tmpd25 |tmpt26 &tmpt25 &tmpt24 &tmpC13;tmpC28 <= tmpd28 | tmpt28&tmpC17;t

13、mpC29 <= tmpd29 | tmpt29&tmpd28 | tmpt29 &tmpt28 &tmpC17; tmpC210v=tmpd210 | tmpt210&tmpd29| tmpt210&tmpt29&tmpt28&tmpC17;tmpC212 <= tmpd212 | tmpt212&tmpC111;tmpC213 <= tmpd213 | tmpt213&tmpd212| tmpt213&tmpt212&tmpC111;tmpC214 <= tmpd214 | tm

14、pt214&tmpd213|tmpt214&tmpt213&tmpt212&tmpC111;tmpC216 <= tmpd216 | tmpt216&tmpC115;tmpC217 <= tmpd217 | tmpt217&tmpd216| tmpt217&tmpt216&tmpC115;tmpC218v=tmpd218 | tmpt218&tmpd217| tmpt218&tmpt217&tmpt216&tmpC115;tmpC219 <= tmpD15 | tmpT15&

15、;tmpC115;tmpC223 <= tmpD16 | tmpT16&tmpC115;tmpC227 <= tmpD17 | tmpT17&tmpC115;tmpCoutl <= tmpD18 | tmpT18&tmpC115;end/對輸入的加數(shù)A,被加數(shù)B,低位進位Cin作五級級暫存/對進位部分進位C作三級暫存/對最高進位Cout作一級暫存/ 計算進位 C22:20,C26:24,C30:28always (posedge elk) begi ntmpA5 <= tmpA4;tmpB5 <= tmpB4;tmpCi n5 <=

16、tmpCi n4;tmpC319:0 <= tmpC219:0;tmpC323 <= tmpC223;tmpC327 <= tmpC227;tmpCout2 <= tmpCoutl;tmpC320 <= tmpd320 | tmpt320&tmpC219;tmpC321 <= tmpd321 | tmpt321&tmpd320| tmpt321&tmpt320&tmpC219;tmpC322 <= tmpd322 | tmpt322&tmpd321| tmpt322&tmpt321&tmpd320

17、| tmpt322&tmpt321&tmpt320&tmpC219;tmpC324 <= tmpd324 | tmpt324&tmpC223;tmpC325 <= tmpd325 | tmpt325&tmpd324| tmpt321&tmpt320&tmpC223;tmpC326 <= tmpd326 | tmpt326&tmpd325| tmpt326&tmpt325&tmpd323| tmpt326&tmpt325&tmpt324&tmpC223;tmpC328 <

18、;= tmpd328 | tmpt328&tmpC227;tmpC329 <= tmpd329 | tmpt329&tmpd328| tmpt329&tmpt328&tmpC227;tmpC330 <= tmpd330 | tmpt330&tmpd329| tmpt330&tmpt329&tmpd328| tmpt330&tmpt329&tmpt328&tmpC227;end/第六個時鐘周期 /所有的進位已經(jīng)產(chǎn)生/計算A、B兩個數(shù)的和Sum/輸出最高進位always (posedge elk) beg

19、inSum <= tmpA5AtmpB5AtmpC330:0,tmpCi n5;Cout <= tmpCout2;enden dmodule/ module fullAdder32(clk,A,B,Ci n,Cout,Sum);測試代碼如下：'timescale 1ns / 1ps /定義時間單為及時間精度/模塊名：test.v/輸入輸出端口：無/目標器件： Veritex4系列的XC4VSX35/ 工具版本：Xilinx-ISE10.1 ISE Simulator(VHDL/Verilog) Synplify Pro9.6.2/ 創(chuàng)建日期：08:44:52 06/23/2011/創(chuàng)建人：/module test;/輸入信號reg elk;reg 31:0 A;reg 31:0 B;reg Ci n;/輸出信號wire Cout;wire 31:0 Sum;/實例化要測試的模塊fullAdder32 uut ( .clk(clk), A(A),.Ci n( Ci n), .Cout(Cout), .Sum(Sum);in itial beg in/初始化輸入信號clk =