杭電計(jì)組實(shí)驗(yàn)4-寄存器堆設(shè)計(jì)實(shí)驗(yàn)

1、實(shí)驗(yàn)報(bào)告2018 年5 月12 日成績：姓名陽光男學(xué)號16041321班級16052317專業(yè)計(jì)算機(jī)科學(xué)與技術(shù)課程名稱計(jì)算機(jī)組成原理與系統(tǒng)結(jié)構(gòu)試驗(yàn)任課老師張翔老師指導(dǎo)老師張翔老師機(jī)位號默認(rèn)實(shí)驗(yàn)序號4實(shí)驗(yàn)名稱實(shí)驗(yàn)四寄存器堆設(shè)計(jì)實(shí)驗(yàn)時間2018/5/12實(shí)驗(yàn)地點(diǎn)1 教 211實(shí)驗(yàn)設(shè)備 號個人電腦、Nexys3開發(fā)板一、實(shí)驗(yàn)程序源代碼1.寄存器堆模塊代碼：moduleRegister_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);in put 4:0R_Addr_A;in put 4:0R_Ad

2、dr_B;in put 4:0W_Addr;in put Write_Reg;in put 31:0W_Data;in put Clk;in put Reset;output 31:0R_Data_A;output 31:0R_Data_B;reg 31:0REG_Files0:31;reg 5:0i;in itial/仿真過程中的初始化begi nfor(i=0;i<=31;i=i+1)REG_Filesi=0;endassig n R_Data_A=REG_FilesR_Addr_A;assig n R_Data_B=REG_FilesR_Addr_B;always(posedge

3、Clk or posedge Reset)begi nif(Reset)for(i=0;iv=31;i二i+1)REG_Filesi=O;elseif(Write_Reg&&W_Addr!=O)REG_FilesW_Addr=W_Data;enden dmodule2.頂層電路模塊代碼：module Top_Register_file(Addr,Write_Reg,C1,C2,Clk,Reset,LED);in put 4:0Addr;in put 1:0C1;/C1選擇32位數(shù)據(jù)輸出哪八位字節(jié)in put Write_Reg,C2,Clk,Reset;/C2選擇讀 A/B 端

4、口 的數(shù)據(jù)output reg 7:0LED;wire 31:0R_Data_A,R_Data_B;reg 31:0W_Data;reg4:0 A,B;Register_file reg1(A,B,Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);always(Addr or Write_Reg or C1 or C2 or R_Data_A or R_Data_B) begi nA=0;B=0;LED=0;W_Data=0;if(!Write_Reg)/ 讀操作 Write_Reg=0beg inif(!C2)beg inA=Addr;ca

5、se(C1)2'b00:LED二R_Data_A7:0;2'bO1:LED二R Data A15:8;2'b10:LED二R_Data_A23:16;2'b11:LED二R_Data_A31:24;endcaseendelsebeg inB=Addr;case(C1)2'b00:LED二R_Data_B7:0;2'bO1:LED二R_Data_B15:8;2'b10:LED=R_Data_B23:16;2'b11:LED=R_Data_B31:24;endcaseendendelse/寫操作begi ncase(C1)2'

6、b00:W_Data=32'h0000_0003;2'b01:W_Data=32'h0000_0607;2'b10:W_Data=32'hFFFF_FFFF;2'b11:W_Data=32'h1111_1234;endcaseendenden dmodule3.測試代碼module test;/In putsreg 4:0 R_Addr_A;reg 4:0 R_Addr_B;reg 4:0 W Addr;reg Write_Reg;reg 31:0 W_Data;reg Clk;reg Reset;/ Outputswire 31:0 R

7、_Data_A; wire 31:0 R_Data_B;/I nsta ntiate the Unit Un der Test (UUT) Register_file uut (.R_Addr_A(R_Addr_A),.R_Addr_B(R_Addr_B), .W_Addr(W_Addr), .Write_Reg(Write_Reg), .W_Data(W_Data), .Clk(Clk),只 eset(Reset),.R_Data_A(R_Data_A), .R_Data_B(R_Data_B);in itial beg in/In itialize In puts R_Addr_A = 0

8、; R_Addr_B = 0;W_Addr = 0; Write_Reg = 0;W_Data = 0; Clk = 0;Reset = 0;/ Wait 100 ns for global reset to finish #100;/ Add stimulus here#100;R_Addr_A = 0;R_Addr_B = 0;W_Addr = 5'b00001;Write_Reg = 1;W_Data = 32'h1111_1111;Clk = 1;Reset = 0;#100;R_Addr_A = 0;R_Addr_B = 0;W_Addr = 5'b00001

9、;Write_Reg = 1;W_Data = 32'h1111_1111; Clk = 0;Reset = 0;#100;R_Addr_A = 0;R_Addr_B = 0;W_Addr = 5'b00010;Write_Reg = 1;W_Data = 32'h2222_2222; Clk = 1;Reset = 0;#100;R_Addr_A = 5'b00001; R_Addr_B = 5'b00010; W_Addr = 0;Write_Reg = 0;W Data = 0;Clk = 0;Reset = 0;#100;R_Addr_A = 5

10、'b00001;R_Addr_B = 5'b00010;W_Addr = 0;Write_Reg = 0;W_Data = 0;Clk = 0;Reset = 1;end en dmodule二、仿真波形p|3jMMiR_Dat*_A|31firQWOOOdODMQOOMoooaoooolllkJLlllW_Mar ami3DOOODODMQQOOKRg R_Dita._Bil：DI.R.AddrA& Wrtte-_Rea¥klut三、電路圖頂層電路模塊Top_Register_fileAddr(4iO)T1C1(tOClkC2ResetWrite RegkJ

11、LED(7：0)Top_Register_file頂層電路內(nèi)部結(jié)構(gòu):四、引腳配置（約束文件）NET "Clk" LOC = C9;NET "Reset" LOC = D9;NET "Write_Reg" LOC = T5;NET "C2" LOC =C4;# Pla nAhead Gen erated physical con stra intsNET "LED7" LOC=T11;NET "LED6" LOC=R11;NET "LED4" LOC=M11

12、;NET "LED3" LOC=V15;NET "LED1" LOC=V16;NET "LED0" LOC=U16;NET "LED2" LOC=U15;NET "LED5" LOC=N11;NET "Addr0" LOC =T10;NET "Addr2" LOC=V9;NET "Addr3" LOC=M8;NET "Addr4" LOC=N8;NET "C10" LOC =U8;NET "C11" LOC =V8;NET "Addr1" LOC=T9;五、思考與探索(1)實(shí)驗(yàn)四實(shí)驗(yàn)結(jié)果記錄表寄存器地址寫入數(shù)據(jù)讀出數(shù)據(jù)$132'h0000_000332'h0000_0003$232'h0000_060732'h0000_0607$332'hFFFF_FFF