FPGA驅(qū)動(dòng)SDRAM

1、FPGA驅(qū)動(dòng)SDRAM-verilog語(yǔ)言之前已經(jīng)對(duì)初始化進(jìn)行了說(shuō)明,網(wǎng)上看了資料不少,但是很多挺浪費(fèi)時(shí)間的,希望我寫這篇能為大家節(jié)省點(diǎn)時(shí)間,下面對(duì)于總體的控制做一下總結(jié)吧,直接放狀態(tài)機(jī)不便以后回顧還是寫吧,時(shí)序整體如下:初始化完成后(初始化時(shí)序見初始化篇;等待信號(hào)-自刷新信號(hào)、讀寫信號(hào);1.如果寫信號(hào)到來(lái):行地址&行有效指令;tRCD最小20ns,具體看手冊(cè);列地址&列有效指令、寫指令;等待burst長(zhǎng)度;tDAL等待預(yù)刷新及后續(xù)時(shí)間4clocks;以上過程完成一次寫操作。2.如果讀信號(hào)到來(lái):行地址&行有效指令;tRCD最小20ns,具體看手冊(cè);列地址&列有效

2、指令、讀指令;tCL潛伏期2clocks;等待burst長(zhǎng)度;tDAL等待預(yù)刷新及后續(xù)時(shí)間4clocks;以上過程完成一次寫操作。3.如果自刷新信號(hào):優(yōu)先級(jí)最高,同時(shí)發(fā)生時(shí)只進(jìn)行自刷新命令,其后續(xù)等待時(shí)間tRFC。以下是幾部分的verilog代碼1.自刷新因?yàn)镾DRAM是動(dòng)態(tài)存儲(chǔ)器,內(nèi)部是電容構(gòu)成(可能是,有點(diǎn)記不清了,所以需要在一段時(shí)間就對(duì)其刷新。每行最大的刷新間隔是64ms,而此SDRAM共有4096行,所以每隔15us(64ms/4096就需要發(fā)出刷新命令.就是定時(shí)產(chǎn)生高電平。module sdram_auto_refresh(clk,rst_n,init_done,auto_refre

3、sh;input clk;input rst_n;input init_done;output auto_refresh;reg10:0cnt_clk;reg auto_refresh;always(posedge clk or negedge rst_nbeginif(!rst_nbegincnt_clk<=11'd0;auto_refresh<=1'b0;endelse if(cnt_clk=11'd1500&&init_donebeginauto_refresh<=1'b1;cnt_clk<=11'd0;en

4、delsebegincnt_clk<=cnt_clk+11'd1;auto_refresh<=1'b0;endendendmodule2.讀寫時(shí)序控制。具體時(shí)序如上所述,所以直接上代碼。空格比較多,大家湊活看,但是是正確的。下面出現(xiàn)的宏定義大家自己寫上,我就不再貼上了。timescale1ns/1psmodule sdram_wr(clk,rst_n,write_req,read_req,auto_refresh,init_done,work_state;input clk;input rst_n;input write_req,read_req;input ini

5、t_done;input auto_refresh;output3:0work_state;include"sdram_para.v"/parameter tRCD=4'd2,tBURST=4'd8,tRFC=4'd7,/auto refresh to new commandstCL=4'd2,tDAL=4'd5;/reg3:0cnt_clk;reg3:0work_state_r;reg write_req_r;reg read_req_r;always(posedge clk or negedge rst_nbeginif(!rst

6、_nwork_state_r<=Wr_idle;elsecase(work_state_rWr_idle:beginif(init_done&& auto_refreshbeginwork_state_r<=Wr_auto_refresh;write_req_r <=1'b0;read_req_r <=1'b0;endelse if(init_done &&!auto_refresh&&write_reqbeginwork_state_r<=Wr_row_active;write_req_r <

7、=1'b1;read_req_r <=1'b0;endelse if(init_done &&!auto_refresh&&read_reqbeginwork_state_r<=Wr_row_active;write_req_r <=1'b0;read_req_r <=1'b1;endelsebeginwork_state_r<=Wr_idle;write_req_r <=1'b1;read_req_r <=1'b0;endendWr_row_active:work_sta

8、te_r<=Wr_row_period;/send row active command&addressWr_row_period:beginif(cnt_clk!=tRCDwork_state_r<= Wr_row_period;else if(write_req_rwork_state_r<= Wr_write;else if(read_req_rwork_state_r<= Wr_read;elsework_state_r<= Wr_idle;end/write data/Wr_write:work_state_r<=Wr_wr_burst;/

9、col address&write commandWr_wr_burst:work_state_r<=(cnt_clk=(tBURST-4'd1?Wr_wr_pre:Wr_wr_burst;/successive burst write for8(data inWr_wr_pre:work_state_r<=(cnt_clk=(tBURST +tDAL?Wr_idle:Wr_wr_pre;/time for auto precharge actual6clocks/read data/Wr_read:work_state_r<=Wr_rd_CL;/col ad

10、dress&read commandWr_rd_CL:work_state_r<=(cnt_clk=tCL? Wr_rd_CL:Wr_rd_burst;/time for CASWr_rd_burst:work_state_r<=(cnt_clk=(tCL+ tBURST-4'd1?Wr_rd_pre:Wr_rd_burst;/successive burst read for8(data outWr_rd_pre:work_state_r<=(cnt_clk= (tBURST+tCL+tDAL?Wr_idle:Wr_rd_pre;/time for auto

11、 precharge/auto_refresh/ Wr_auto_refresh refresh command Wr_ar_period default endcase end assign work_state = work_state_r ; /control of cnt_clk/ reg cnt_clk_rst_n ; always (posedge clk or negedge rst_n begin if ( ! rst_n cnt_clk <= 4'd0; else if ( ! cnt_clk_rst_n cnt_clk <= 4'd0; else

12、 if ( cnt_clk = 4'd15 cnt_clk <= 4'd0; else cnt_clk <= cnt_clk + 4'd1; end always ( posedge clk or negedge rst_n begin if ( ! rst_n cnt_clk_rst_n <= 1'b0; else case ( work_state_r Wr_row_period,Wr_wr_burst,Wr_wr_pre, Wr_rd_CL,Wr_rd_burst,Wr_rd_pre, Wr_ar_period : cnt_clk_rst

13、_n <= 1'b1; : work_state_r <= ( cnt_clk = tRFC : work_state_r <= Wr_idle; 4'd1 ? Wr_idle : Wr_ar_period ;/wait for tRFC : work_state_r <= Wr_ar_period;/auto default : cnt_clk_rst_n <= 1'b0; endcase end endmodule 3.命令發(fā)出模塊。 timescale 1ns / 1ps module sdram_cmd ( clk,rst_n, i

14、nit_state,work_state, / / ; input clk ; input rst_n ; input 4:0 init_state ; input 3:0 work_state; /input 1:0 address_bank; /input 11:0 address_row; /input 11:0 address_col; output cken,cs_n,ras_n,cas_n,we_n; /output 1:0 address_b; /output 11:0 address_a; include "sdram_para.v" /command ou

15、tput/ reg 4:0 ctrl_cmd ; assign cken,cs_n,ras_n,cas_n,we_n = ctrl_cmd; always ( posedge clk or negedge rst_n begin if ( ! rst_n address_bank,address_row,address_col, address_b,address_a, cken,cs_n,ras_n,cas_n,we_n ctrl_cmd <= Ctrl_nop; else case ( init_state Init_idle Init_precharge : ctrl_cmd &l

16、t;= Ctrl_nop ; : ctrl_cmd <= Ctrl_precharge ; Init_refresh_1,Init_refresh_2,Init_refresh_3, Init_refresh_4,Init_refresh_5,Init_refresh_6, Init_refresh_7,Init_refresh_8 : Init_MRS Init_finish : case ( work_state Wr_idle : ctrl_cmd <= Ctrl_nop ; Wr_row_active ctrl_cmd <= Ctrl_row_active ; Wr_write : : ctrl_cmd <= Ctrl_write ; Wr_read ctrl_cmd <= Ctrl_read ; Wr_auto_refresh: ctrl_cmd &l