模型機(jī)課程設(shè)計(jì)

1、哈爾濱理工大學(xué)軟件學(xué)院課程設(shè)計(jì)報(bào)告課壬口 程片上計(jì)算機(jī)系統(tǒng)題CPU模型機(jī)設(shè)計(jì)班級(jí)集成12-1班專業(yè)集成電路設(shè)計(jì)與集成系統(tǒng)學(xué)生張銘學(xué)口， 號(hào)1214020130指-導(dǎo)教師崔林海2014年07月 02日1課程設(shè)計(jì)的目的及要求索 引：2處理器的設(shè)計(jì)思想和設(shè)計(jì)內(nèi)容3設(shè)計(jì)處理器的結(jié)構(gòu)和實(shí)現(xiàn)方法4模型機(jī)的指令系統(tǒng)5處理器的狀態(tài)跳轉(zhuǎn)操作過(guò)程6. CPU 的 VHDL 代碼7. 模型機(jī)在 Quartus II 環(huán)境下的應(yīng)用328. 仿真波形339. 課程設(shè)計(jì)的總結(jié)35課程設(shè)計(jì)的目的及要求:1. 目的：了解Quartus II軟件的應(yīng)用，學(xué)習(xí)Quartus II環(huán)境下設(shè)計(jì)CPU的基 本過(guò)程；掌握CPU設(shè)計(jì)代碼的

2、含義以及CPU的工作原理；了解CPU與內(nèi)存RAM 間的連接數(shù)據(jù)的傳輸過(guò)程；學(xué)習(xí)在 Quartus II環(huán)境下建立模型機(jī)的具體過(guò)程。融 會(huì)貫通本課程各章節(jié)的內(nèi)容，通過(guò)知識(shí)的綜合運(yùn)用，加深對(duì)計(jì)算機(jī)系統(tǒng)各模塊的 工作原理及相互聯(lián)系的認(rèn)識(shí)。學(xué)習(xí)設(shè)計(jì)和調(diào)試計(jì)算機(jī)的基本步驟和方法，提高使 用軟件仿真工具和集成電路的基本技能。培養(yǎng)科學(xué)研究的獨(dú)立工作能力，取得工 程設(shè)計(jì)與組裝調(diào)試的實(shí)踐和經(jīng)驗(yàn)。2. 要求：以計(jì)算機(jī)組成與設(shè)計(jì)書中123頁(yè)的簡(jiǎn)化模型為基礎(chǔ)，更改其指 令系統(tǒng)，形成設(shè)計(jì)者的CPU,在Quartus II環(huán)境下與主存連接，調(diào)試程序，觀察 指令的執(zhí)行是否達(dá)到設(shè)計(jì)構(gòu)想。二.處理器的設(shè)計(jì)思想和設(shè)計(jì)內(nèi)容：處理器

3、的字長(zhǎng)為16b;包括四種指令格式，格式1、格式2、格式3的指令 字長(zhǎng)度為8b,格式4的指令字長(zhǎng)度為16b；處理器內(nèi)部的狀態(tài)機(jī)包括6個(gè)狀態(tài)。關(guān)于CPU:操作碼5位，一共設(shè)計(jì)20條指令，主要包括空操作指令、中斷指令、加法 指令、減法指令、三種邏輯運(yùn)算指令、循環(huán)移位操作指令，數(shù)據(jù)傳輸指令，轉(zhuǎn)移 類指令，特權(quán)指令，取反，取絕對(duì)值等等。關(guān)于RAM :地址線設(shè)置成16bits，主存空間為64words。書中原CPU的主要修改：（1）模型機(jī)CPU指令集中的邏輯左移與邏輯右移改成邏輯循環(huán)右移與邏 輯循環(huán)左移。（2）模型機(jī)CPU指令集中的or改成not。（3）模型機(jī)CPU指令的執(zhí)行流程及狀態(tài)跳轉(zhuǎn)。三. 設(shè)計(jì)處理

4、器的結(jié)構(gòu)和實(shí)現(xiàn)方法:（指令格式） 格式1:寄存器尋址方式1514131211 109876 54 32100PRx1Ry空白格式2:立即數(shù)尋址方式1514131211 10987654321 0OPI1空白格式3:無(wú)操作數(shù)尋址方式1514131211 10987654321 0OP空白1空白格式4:直接尋址方式1514131211 10987654321 0OPAddr內(nèi)存（2的12次方）四. 模型機(jī)的指令系統(tǒng)CPU的指令集:操作碼OPIR(15.12)指令 格式指令的助記符指令的內(nèi)容000003Idle無(wú)操作PC=P C+1000012Load DataR0 I立即數(shù)操作000101Move

5、 Rx RyRx (Ry)PC=P C+1000111Add Rx RyRx (Rx)+(Ry)PC=P C+101001Sub Rx RyRx (Rx)-(Ry)PC=P C+1001011AND Rx RyRx (Rx) AND(Ry)PC=P C+1001101NOT Rx RyRx (Rx) NOT (Ry)PC=P C+1001111XOR Rx RyRx (Rx) XOR (Ry) PC=PC+1010001Swa p Rx RyA (Ry) Ry (Rx) Rx (A) PC=PC+1010011Shr Rx Ry倒置數(shù)據(jù)PC=PC+1010101Shi Rx Ry邏輯循環(huán)左移P

6、C=PC+1010114Jmp AddrPC AddrPC=PC+1011004Jz AddrIf (R0)=0 then PC Addr elsePC=P C+1011014Read AddrR0 (Addr)PC=P C+1011104Write AddrAddr (R0)PC=P C+1011113Sto p無(wú)操作 PC保持不變100001comp比較pc=p c+1100011n ot p取反pc=pc+1100101clearpc=pc+1100111abs ppc=pc+1五. 處理器的狀態(tài)跳轉(zhuǎn)操作過(guò)程:（一）、模型機(jī)每一狀態(tài)下的操作及狀態(tài)跳轉(zhuǎn)當(dāng)前狀態(tài)執(zhí)行操作I次態(tài)與讀下一條指令的

7、有關(guān)的St_0St_1IFOP=MoveTHENRx(Ry)IFOP= Shr THENRx(Rx)倒置數(shù)據(jù)IFOP= Shl THENRx(Rx)邏輯循環(huán)左移IF OP =AddTHEN A (Ry)IF OP =Sub THEN A (Ry)IF OP= AND THEN A (Ry)IF OP=NOT THEN A (Ry)IF OP =XOR THEN A (Ry)IF OP =Swap THEN A (Ry)IF OP=St op THEN NULLIF OP=IdleTHEN NULLIF OP=Jmp THEN NULLIF OP=JzTHEN NULLIF OP=Read TH

8、EN NULL取指令I(lǐng)R(15.0) M_data_in (15.0)IF OP=Load THENR0 IR(11.8)000000000000操作St_iWrite-Read PC=PC+1 MAR_PCIF( OP=Sto p)rHENSt_1ELSE St_2END IFSt_2IF OP=Write THEN NULLIF OP= Load OR OP=Move OR OP=Shr OR OP=Shl OR OP=ldle THEN NULLIFOP= Add(Rx)+AIFOP= SubTHENRx(Rx)-AIFOP= AND THENRx(Rx)ANDAIF OP= NOT T

9、HEN Rx (Rx) NOT AIF OP= XOR THEN Rx (Rx) XORAIF OP= Swap THEN Ry (Rx)IF OP= Jmp THEN(PC IR(1.0) MAR IR(11.0)st_o Write-Read THEN RxSt_3Write-Read 讀內(nèi)存指令：(1)St_O:取指令執(zhí)行以下操作;1)2)3)4)IF 0P= Jz THEN IF (R0)=0 THEN (PC IR(1.0)MAR IR(11.0) ELSE MAR PCIFOP= Read THENMAR IR(11.0)IF OP= Write THENMAR IR(11.0)

10、MDA R0St_3IF OP =Swa p THEN Rx (A)St_0 Write-Read IF OP= Jmp NOT OP= JzSt_0MAR PC Write-Read IF OP= WriteSt_4MAR PC Write-Read IF OP= ReadSt_4MAR PC Write-Read St_4IF OP= Read THENR0 M data inSt_0 Write-Read St-5IF OP=ABS P THEN R0-M_data_inSt_0IF OP=NOT P THEN R0-M_data_inSt_0IF OP=CLEAR THENR0,R1,

11、R2,R3,IRv-0St_0IF OP=CO MP THENR0-M_data_inR1-M data inSt_0(二)、簡(jiǎn)單指令執(zhí)行狀態(tài)描述M_address (MAR)把指令地址送到地址總線令Write-Read 向內(nèi)存發(fā)出讀命令(取指令)IR(15.O) M_data_in( 15.0)將讀出的指令加載于 IR(15.O)PC=PC+1至此指令已經(jīng)全部取出，存在于IR(15.O)，為取下一條指令準(zhǔn)備地址(2)St_1(3)St_2(4)St_31)M_address (MAR) 把數(shù)據(jù)地址送到地址總線 令 Write-Read 0 向內(nèi)存發(fā)出讀命令(取數(shù)據(jù)) MAR PC 把下一條指

12、令地址加載于 MARNULL 直接跳轉(zhuǎn)到下一狀態(tài)MAR IR(11.0)將數(shù)據(jù)地址加載于 MAR2)3)5) st_4：R0 M data in將來(lái)自內(nèi)存的數(shù)據(jù)加載于R0,本指令執(zhí)行完畢 M_address (MAR)把下一條指令地址送到地址總線 令 Write-Read 0 下一狀態(tài)跳轉(zhuǎn)到 st_1)2)3)4)向內(nèi)存發(fā)出讀命令(取下一條指令)0無(wú)條件轉(zhuǎn)移指令(1) st_o：取指令執(zhí)行以下操作；M_address (MAR) 把指令地址送到地址總線 令 Write-Read o 向內(nèi)存發(fā)出讀命令(取指令) IR(15.o) PC=PC+11)2)3)4) 目的)M_data_in(15.0

13、) 將讀出的指令加載于 IR(15.0) 此語(yǔ)句無(wú)用， 因?yàn)槌绦蛴?jì)數(shù)器后續(xù)重新復(fù)制達(dá)到無(wú)條件轉(zhuǎn)移( 2) st_1： NULL( 3) st_2：1) MAR IR(11.0) 將轉(zhuǎn)移目標(biāo)地址加載于 MAR2) PC IR(11.0)將轉(zhuǎn)移目標(biāo)地址加載于 PC( 4) st_3：1) M_address (MAR) 把下一條指令地址送到地址總線2) 令 Write-Read 0 向內(nèi)存發(fā)出讀命令(取下一條指令)3) 下一狀態(tài)跳轉(zhuǎn)到 st_0直接跳轉(zhuǎn)到下一狀態(tài)六CPU的VHDL代碼:LIBRARY ieee;USE ieee.std_logic_1164.ALL;PACKAGE namespac

14、k ISCONSTANTcompstd_logic_vector(4 DOWNTOCONSTANTnotp: std_logic_vector(4 DOWNTOCONSTANTidlestd_logic_vector(4 DOWNTO0) :=00000;CONSTANT load: std_logic_vector(4 DOWNTO 0) :=00001;CONSTANT move: std_logic_vector(4 DOWNTO 0) :=00010;CONSTANT addP: std_logic_vector(4 DOWNTO 0) :=00011;CONSTANT subp: s

15、td_logic_vector(4 DOWNTO 0) :=00100;CONSTANT andp: std_logic_vector(4 DOWNTO 0) :=00101;CONSTANT orp: std_logic_vector(4 DOWNTO 0) :=00110;CONSTANT xorp: std_logic_vector(4 DOWNTO 0) :=00111;CONSTANT shrp: std_logic_vector(4 DOWNTO 0) :=01000;CONSTANT shlp: std_logic_vector(4 DOWNTO 0) :=01001;CONST

16、ANT swap: std_logic_vector(4 DOWNTO 0) :=01010;CONSTANT jmp: std_logic_vector(4 DOWNTO 0) :=01011;CONSTANT jz: std_logic_vector(4 DOWNTO 0) :=01100;CONSTANT read: std_logic_vector(4 DOWNTO 0) :=01101;CONSTANT write : std_logic_vector(4 DOWNTO 0) :=01110;CONSTANT stop: std_logic_vector(4 DOWNTO 0) :=

17、01111;0) :=10000;0) :=10001;CONSTANTclearstd_logic_vector(4DOWNTOclock : IN std_logic;-時(shí)鐘信號(hào)Write_Read: OUT std_logic;-讀寫信0) :=10010;CONSTANTabsp: std_logic_vector(4DOWNTO0) :=10011;CONSTANTmodp: std_logic_vector(4DOWNTO0) :=10100;END namespack;LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_lo

18、gic_unsigned.ALL;USE WORK.namespack.ALL;ENTITY cpu IS-清零信號(hào)低PORT(reset : IN std_logic;有效號(hào),1為寫M_address: OUT std_logic_vector(10 DOWNTO0);-地址線SIGNAL status: integer RANGE 0 TO 6;-狀態(tài)-數(shù)據(jù)M_data_in: IN std_logic_vector(7 DOWNTO 0);輸入線M_data_out: OUT std_logic_vector(7 DOWNTO0);-數(shù)據(jù)輸出線overflow: OUT std_logi

19、c-溢出標(biāo)志);END cpu;ARCHITECTURE RTL OF cpu ISSIGNAL IR: std_logic_vector(15 DOWNTO 0);-指令寄存器SIGNAL MDR: std_logic_vector(7 DOWNTO 0);-數(shù)據(jù)寄存器SIGNAL MAR: std_logic_vector(10 DOWNTO 0);-地址寄存器寄存器BEGINstatus_change: PROCESS(reset, clock, status )BEGIN進(jìn)入初始狀I(lǐng)F reset = 0 THEN status status IF IR(15 DOWNTO 11)=

20、Stop THENstatus = 1;ELSE status CASE IR(15 DOWNTO 11) ISWHEN Swap|Jmp|Jz|Read|Write =status END CASE;status IF IR(15 DOWNTO 11)= Swap THEN status = 0;ELSE status status CASE IR(15 DOWNTO 11) ISWHEN Read|Write =status status CASE IR(15 DOWNTO 11) ISWHEN Comp=statusstatus=0;statusWHEN AbsP=statusstatu

21、sstatus = 0;END CASE;END CASE;END IF;END PROCESS status_change;seq: PROCESS(reset,clock)VARIABLE PC:std_logic_vector(10 DOWNTO 0);-程序計(jì)數(shù)器VARIABLER0,R1,R2,R3: std_logic_vector(7 DOWNTO0);VARIABLERC:std_logic_vector(7DOWNTO0);-通用寄存器VARIABLEA:std_logic_vector(7DOWNTO0);-臨時(shí)寄存器-比較結(jié)果寄存器VARIABLERM:std_logic

22、_vector(7DOWNTO0);-取模結(jié)果寄存器VARIABLE temp: std_logic_vector(8 DOWNTO 0);IR -臨時(shí)變量BEGINIF(reset=0) THEN- 進(jìn)入初始狀態(tài)IR 0);PC := (OTHERS=0);R0 := (OTHERS=0);R1 := (OTHERS=0);R2 := (OTHERS=0);R3 := (OTHERS=0);A := (OTHERS=0);MAR 0);MDR 0);ELSIF(clockevent AND clock=1) THENoverflow 狀態(tài) 0PC := PC+1;-程序計(jì)數(shù)器加 1狀態(tài) 1I

23、F (IR(15 DOWNTO 11) /= Stop) THENMAR R0:=0000 & IR(10 DOWNTO 7);WHENMove=WHEN 1011= R2:=R3;WHEN 1100= R3:=R0;WHEN 1101= R3:=R1;-Move Rx,Ry;CASE IR(10 DOWNTO 7) ISWHEN 0001= R0:=R1;WHEN 0010= R0:=R2;WHEN 0011= R0:=R3;WHEN 0100= R1:=R0;WHEN 0110= R1:=R2;WHEN 0111= R1:=R3;WHEN 1000= R2:=R0;WHEN 1001= R

24、2:=R1;WHEN 1110= R3:=R2;WHEN OTHERS= NULL;END CASE;WHEN Shrp =R0:=R0(6 DOWNTO 0)&0;WHEN 01=WHEN 11=邏輯右移 1 位；輯左移 1 位；、皿-邏CASE IR(10 DOWNTO 9) ISWHEN 00=R0:=0&R0(7 DOWNTO 1);WHEN 01=R1:=0&R1(7 DOWNTO 1);WHEN 10=R2:=0&R2(7 DOWNTO 1);WHEN OTHERS=R3:=0&R3(7 DOWNTO 1);END CASE;WHEN Shlp =CASE IR(10 DOWNTO

25、 9) ISWHEN 00=R1:=R1(6 DOWNTO 0)&0;R2:=R2(6 DOWNTO 0)&0;WHENAddp=WHEN 13=WHEN OTHERS=R3:=R3(6 DOWNTO 0)&0;END CASE;WHEN Addp|Subp|Andp|Orp|Xorp|Swap =CASE IR(8 DOWNTO 7) ISWHEN 00= A:=R0;WHEN 01= A:=R1;WHEN 10= A:=R2;WHEN OTHERS= A:=R3;END CASE;WHEN OTHERS = NULL;END CASE;WHEN 2=狀態(tài) 2CASE IR(15 DOWNT

26、O 11) IS-Rx:= Rx+A;CASE IR(10 DOWNTO 9) IStemp := (R0(7) & R0(7 DOWNTO0)+WHENSubp=(A(7) & A(7 DOWNTO 0);R0:=temp(7 DOWNTO 0);overflow temp :=(R1(7) & R1(7 DOWNTO0)(A(7) & A(7 DOWNTO 0);R1:=temp(7 DOWNTO 0);overflow temp :=(R2(7) & R2(7 DOWNTO0)(A(7) & A(7 DOWNTO 0);R2:=temp(7 DOWNTO 0);overflow temp

27、 :=(R3(7) & R3(7 DOWNTO0)(A(7) & A(7 DOWNTO 0);R3:=temp(7 DOWNTO 0);overflow temp :=(R0(7) & R0(7 DOWNTO0)NOT(A(7) & A(7 DOWNTO 0) + 1;R0:=temp(7 DOWNTO 0);overflow temp :=(R1(7) & R1(7 DOWNTO0)NOT(A(7) & A(7 DOWNTO 0) + 1;R1:=temp(7 DOWNTO 0);overflow temp :=(R2(7) & R2(7 DOWNTO0)NOT(A(7) & A(7 DOW

28、NTO 0) + 1;R2:=temp(7 DOWNTO 0);overflow temp :=(R3(7) & R3(7 DOWNTO0)NOT(A(7) & A(7 DOWNTO 0) + 1;R3:=temp(7 DOWNTO 0);overflow CASE IR(10 DOWNTO 9) ISWHEN 00=R0:=R0 and A;WHEN 01=R1:=R1 and A;WHEN 10=R2:=R2 and A;WHEN OTHERS=R3:=R3 and A;END CASE;WHEN Orp =CASE IR(10 DOWNTO 9) ISWHEN 00=R0:=R0 or

29、A;WHEN 01=R1:=R1 or A;R2:=R2 or A;WHEN 10=WHEN OTHERS=R3:=R3 or A;END CASE;WHEN 1000=WHEN 1100=WHENXorp=-Rx=Rx XOR A;WHENSwap=-Swap: Rx to Ry;CASE IR(10 DOWNTO 9) ISWHEN 00=R0:=R0 XOR A;WHEN 01=R1:=R1 XOR A;WHEN 10=R2:=R2 XOR A;WHEN OTHERS=R3:=R3 XOR A;END CASE;CASE IR(10 DOWNTO 7) ISWHEN 0100=R0:=R

30、1;R0:=R2;R0:=R3;WHEN 0001=R1:=R0;WHEN 1001=R1:=R2;WHEN 1101=R1:=R3;WHEN 0010=R2:=R0;WHEN 0110=R2:=R1;WHEN 1110=R2:=R3;WHEN 0111=R3:=R1;WHEN 1011=R3:=R2;WHEN 0011=R3:=R0;NULL;END CASE;WHEN OTHERS=WHEN OTHERS = NULL;END CASE;WHEN 3=WHEN 4=CASE IR(15 DOWNTO 11) IS狀態(tài) 3CASE IR(15 DOWNTO 11) ISWHEN01010=-

31、SwapCASE IR(10 DOWNTO 9) ISWHEN 00= R0:=A;WHEN 01= R1:=A;WHEN 10= R2:=A;WHEN OTHERS= R3:=A;END CASE;WHEN Jmp|Jz|Read|Write =IR(7 DOWNTO 0) NULL;END CASE;狀態(tài) 4WHEN Jmp =PC := IR(10 DOWNTO 0);MAR IF(R0=00000000) THENPC := IR(10 DOWNTO 0);MAR = IR(10 DOWNTO 0);ELSEMAR MAR MAR = IR(10 DOWNTO 0);MDR NULL;

32、END CASE;WHEN 5=狀態(tài) 5MAR CASE IR(15 DOWNTO 11) ISWHEN Comp =RC(7 DOWNTO 6):=01;ELSE RC(7 DOWNTO 6):=10 ;比較THENRC(7 DOWNTO 6):=00;相等ELSIF A(7)=1 THEN-R0R1-R0 A:=R1-R0;IF A(7 DOWNTO 0)=00000000END IF;WHEN 0010= A:=R2-R0;IF A(7 DOWNTO 0)=00000000 THENRC(7 DOWNTO 6):=00;ELSIF A(7)=1 THENEND IF;WHEN 0011=

33、 A:=R3-R0;IF A(7 DOWNTO 0)=00000000RC(7 DOWNTO 6):=00;RC(7 DOWNTO 6):=01;THENRC(7 DOWNTO 6):=00;ELSIF A(7)=1 THENRC(7 DOWNTO 6):=01;ELSE RC(7 DOWNTO 6):=10;END IF;WHEN 0100= A:=R0-R1;IF A(7 DOWNTO 0)=00000000THENRC(7 DOWNTO 6):=00;ELSIF A(7)=1 THENRC(7 DOWNTO 6):=01;ELSE RC(7 DOWNTO 6):=10;END IF;WH

34、EN 0110= A:=R2-R1;IF A(7 DOWNTO 0)=00000000THENELSIF A(7)=1 THENELSE RC(7 DOWNTO 6):=11;IF A(7 DOWNTO 0)=00000000RC(7 DOWNTO 6):=00;THENTHENTHENEND IF;WHEN 0111= A:=R3-R1;IF A(7 DOWNTO 0)=00000000RC(7 DOWNTO 6):=00;ELSIF A(7)=1 THENRC(7 DOWNTO 6):=01;ELSE RC(7 DOWNTO 6):=10;END IF;WHEN 1000= A:=R0-R

35、2;IF A(7 DOWNTO 0)=00000000RC(7 DOWNTO 6):=00;ELSIF A(7)=1 THENRC(7 DOWNTO 6):=01;ELSE RC(7 DOWNTO 6):=10;END IF;WHEN 1001= A:=R1-R2;THENTHENELSIF A(7)=1 THENRC(7 DOWNTO 6):=01;ELSE RC(7 DOWNTO 6):=10;END IF;WHEN 1011= A:=R3-R2;IF A(7 DOWNTO 0)=00000000RC(7 DOWNTO 6):=00;ELSIF A(7)=1 THENRC(7 DOWNTO

36、 6):=01;ELSE RC(7 DOWNTO 6):=10;END IF;WHEN 1100= A:=R0-R3;IF A(7 DOWNTO 0)=00000000RC(7 DOWNTO 6):=00;ELSIF A(7)=1 THENRC(7 DOWNTO 6):=01;END IF;ELSE RC(7 DOWNTO 6):=10;WHEN 1101= A:=R1-R3;IF A(7 DOWNTO 0)=00000000RC(7 DOWNTO 6):=00;THENCASE IR(10 DOWNTO 9) ISWHEN 00=THENELSIF A(7)=1 THENRC(7 DOWNT

37、O 6):=01;ELSE RC(7 DOWNTO 6):=10;END IF;WHEN 1110= A:=R2-R3;IF A(7 DOWNTO 0)=00000000RC(7 DOWNTO 6):=00;ELSIF A(7)=1 THENRC(7 DOWNTO 6):=01;ELSE RC(7 DOWNTO 6):=10;END IF;WHEN OTHERS= NULL;-取反END CASE;WHEN Notp =R0:=Not R0;WHEN Absp =-取絕對(duì)WHEN 01=R1:=Not R1;WHEN 10=R2:=Not R2;WHEN 11=R3:=Not R3;END C

38、ASE;-清空WHEN Clear =IR 0);PC := (OTHERS=0);R0 := (OTHERS=0);R1 := (OTHERS=0);R2 := (OTHERS=0);R3 := (OTHERS=0);A := (OTHERS=0);MAR 0);MDR 0);overflow CASE IR(10 DOWNTO 9) ISWHEN 00=IF(R0(7)=1) THENR0:=0&R0(6 DOWNTO 0);ELSER0:=R0;END IF;WHEN 01=IF(R1(7)=1) THENR1:=0&R1(6 DOWNTO 0);ELSER1:=R1;END IF;WH

39、EN 10=IF(R2(7)=1) THENR2:=0&R2(6 DOWNTO 0);ELSER2:=R2;END IF;IF(R3(7)=1) THENR3:=0&R0(6 DOWNTO 0);ELSER3:=R3;END IF;END CASE;WHEN OTHERS = NULL;END CASE;END CASE;END IF;END PROCESS seq;M_address = MAR;M_data_out = MDR;Write_Read = 1 WHEN reset = 1 AND status = 5 ANDIR(15 downto 12) = WriteELSE0 ;END RTL;Quartus II 環(huán)境下的應(yīng)用：cpu七 模型機(jī)在 步驟： 1.建立工程：工程名 2編寫cpu的VHDL代碼，將其添加到工程3. 生成cpu的符號(hào)圖4. 建立內(nèi)存數(shù)據(jù)的mif文件5. 生成 16bits 的 ram6建立computer的block進(jìn)行編譯7. 對(duì)computer進(jìn)行功能模擬8. 分析仿真波形八.仿真波形:1） cpu的