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1、DLX 指令集, BYU 版本注意8條指令已經(jīng)加入到此版本的指令集中。這些指令既沒有出現(xiàn)在Hennessy 和 Patterson的課本中,也沒有列在Sailer 和 Kaeli 合編的The DLX Instruction Set Architecture Handbook一書中。新的指令是:sgeu, sgtu, sleu, sltu - all compares using unsigned values - along with an immediate form of each. The new instructions were added to simplify the DLX

2、backend for lcc. 標(biāo)記 符號(hào) 意義 x_y bit y of x x_y.z bits y to z of x (right justified) xy xxx (x repeated y times) x#y xy (x concatenated with y) IR 指令寄存器 IAR 中斷地址寄存器 PC 程序計(jì)數(shù)器 Rrega 整數(shù)寄存器IR_6.10 Rregb 整數(shù)寄存器IR_11.15 Rregc 整數(shù)寄存器IR_16.20 Ffrega 浮點(diǎn)寄存器IR_6.10 Ffregb 浮點(diǎn)寄存器IR_11.15 Ffregc 浮點(diǎn)寄存器IR_16.20 Ddrega d

3、ouble registerIR_6.10 Ddregb double registerIR_11.15 Ddregc double registerIR_16.20 imm16 value of (IR_16)16 # IR_16.31 uimm16 value of 016 # IR_16.31 imm26 value of (IR_6)6 # IR_6.0 fps floating point status bit - a 32-bit transfer -n an n-bit transfer注意/假設(shè)Bits are numbered from 0 (the most signifi

4、cant bit) to 31 (the least significant bit). All transfers are 32 bits unless otherwise specified, with the exception of double precision fp operations which are 64 bit transfers unless otherwise noted. All integer operations are on 32-bit integers. All assignments to integer registerx are condition

5、al on x not being zero. Register 0 has a hardwired em zero value and cannot be modified. Double registerx is a 64 bit quantity that represents the same storage as fp registerx and fp registerx+1. Only even values of x are allowed (double register addresses are aligned).Single precision floating poin

6、t is 32 bits and double precision floating point is 64 bits. The exact floating point format used is that of the machine on which the simulator is running. The specifications for branches and jumps assume that the PC has not yet been incremented (for the next instruction) when the specified actions

7、are performed. Note that this does not represent the actual behavior in any reasonable pipelined implementation; it is assumed merely to simplify the description. Memory will be stored in big endian format and all effective addresses must be aligned with the data type. InstructionsaddEx: add r1,r2,r

8、3Rregc - Rrega + RregbAll are signed integers. adddEx: addd f4,f4,f6Ddregc - Ddrega + DdregbAll are double precision floating point numbers. addfEx: addf f3,f4,f5Ffregc - Ffrega + FfregbAll are single precision floating point numbers. addiEx: addi r5,r2,#5Rregb - Rrega + imm16All are signed integers

9、. adduEx: addu r2,r3,r4Rregc - Rrega + RregbAll are unsigned integers. adduiEx: addui r2,r3,#28Rregb - Rrega + uimm16All are unsigned integers. andEx: and r2,r3,r4Rregc - Rrega & RregbAll are unsigned integers. Logical and is performed on a bitwise basis. andiEx: andi r3,r4,#5Rregb - Rrega & uimm16A

10、ll are unsigned integers. Logical and is performed on a bitwise basis. beqzEx: beqz r1,labelif (Rrega = 0) PC - PC + imm16 + 4bfpfEx: bfpf labelif (fps = 0) PC - PC + imm16 + 4fps is the floating point status bit. bfptEx: bfpt labelif (fps = 1) PC - PC + imm16 + 4fps is the floating point status bit

11、. bnezEx: bnez r1,labelif (Rrega != 0) PC - PC + imm16 + 4cvtd2fEx: cvtd2f f1,f4Ffregc - (float) DdregaConverts double precision floating point value to single precision floating point value. cvtd2iEx: cvtd2i f1,f0Ffregc - (int) DdregaConverts double precision floating point value to integer. cvtf2d

12、Ex: cvtf2d f4,f9Ddregc - (double) FfregaConverts single precision float to double. cvtf2iEx: cvtf2i f3,f4Ffregc - (int) FfregaConverts single precision float to integer. cvti2dEx: cvti2d f2,f9Ddregc - (double) FfregaConverts a signed integer to double precision float. cvti2fEx: cvti2f f2,f5Ffregc -

13、(float) FfregaConverts a signed integer to single precision float. divEx: div f2,f2,f3Ffregc - Ffrega / FfregbAll are signed integers. divdEx: divd f4,f4,f6Ddregc - Ddrega / DdregbAll are double precision floats. divfEx: divf f2,f3,f6Ffregc - Ffrega / FfregbAll are single precision floats. divuEx: d

14、ivu f2,f3,f4Ffregc = Ddregb) fps = 1 else fps = 0Both are double precision floats. gefEx: gef f3,f6if (Ffrega = Ffregb) fps = 1 else fps = 0Both are single precision floats. gtdEx: gtd f8,f6if (Ddrega Ddregb) fps = 1 else fps = 0Both are double precision floats. gtfEx: gtf f3,f6if (Ffrega Ffregb) fp

15、s = 1 else fps = 0Both are single precision floats. jEx: j labelPC - PC + imm26 + 4Unconditionally jumps relative to the PC of the next instruction. imm26 is a 26-bit signed integer. jalEx: jal labelR31 - PC + 8; PC - PC + imm26 + 4Saves a return address in register 31 and jumps relative to the PC o

16、f the next instruction. imm26 is a 26-bit signed integer. jalrEx: jalr r2R31 - PC + 8; PC - RregaSaves a return address in register 31 and does an absolute jump to the target address contained in Rrega. jrEx: jr r3PC - RregaRrega is treated as an unsigned integer. Does an absolute jump to the target

17、 address contained in Rrega. lbEx: lb r1,40-4(r2)Rregb - (sign extended) Mimm16 + RregaOne byte of data is read from the effective address computed by adding signed integer imm16 and signed integer Rrega. The byte from memory is then sign extended to 32-bits and stored in register Rregb. lbuEx: lbu

18、r2,label-786+4(r3)Rregb - 024 # Mimm16 + RregaOne byte of data is read from the effective address computed by adding signed integer imm16 and signed integer Rrega. The byte from memory is then zero extended to 32 bits and stored in register Rregb. ldEx: ld f2,240(r1)Ddregb -64 Mimm16 + RregaTwo word

19、s of data are read from the effective address computed by adding signed integer imm16 and unsigned integer Rrega and stored in double register Ddregb. This is equivalent to two lf instructions: Ffregb - Mimm16 + Rrega Ffreg(b+1) - Mimm16 + Rrega + 4where Ffreg(b+1) is the next fp register after Ffre

20、gb in sequence, and all values are simply copied and not converted.) ledEx: led f8,f6if (Ddrega = Ddregb) fps = 1 else fps = 0Both are double precision floats. lefEx: lef f3,f6if (Ffrega = Ffregb) fps = 1 else fps = 0Both are single precision floats. lfEx: lf f6,76(r4)Ffregb - Mimm16 + RregaOne word

21、 of data is read from the effective address computed by adding signed integer imm16 and signed integer Rrega and stored in fp register Ffregb. lhEx: lh r1,32(r3)Rregb - (sign extended) Mimm16 + RregaTwo bytes of data are read from the effective address computed by adding signed integer imm16 and sig

22、ned integer Rrega. The address must be half-word aligned. The half-word from memory is then sign extended to 32 bits and stored in register Rregb. lhiEx: lhi r3,#-40Rregb - imm16 # 016Loads the 16 bit immediate value imm16 into the most significant half of an integer register and clears the least si

23、gnificant half. lhuEx: lhu r2,-40+4(r3)Rregb - 016 # Mimm16 + RregaTwo bytes of data are read from the effective address computed by adding signed integer imm16 and signed integer Rrega. The address must be half-word aligned. The half-word from memory is then zero extended to 32 bits and stored in r

24、egister Rregb. ltdEx: ltd f8,f6if (Ddrega Ddregb) fps = 1 else fps = 0Both are double precision floats. ltfEx: ltf f3,f6if (Ffrega Ffregb) fps = 1 else fps = 0Both are single precision floats. lwEx: lw r19,label+63(r8)Rregb - Mimm16 + RregaOne word is read from the effective address computed by addi

25、ng signed integer imm16 and unsigned integer Rrega and is stored in Rregb. movdEx: movd f2,f4Ddregc - DdregaCopies two words from double register Ddrega to double register Ddregc. movfEx: movf f1,f2Ffregc - FfregaCopies one word from fp register Ffrega to fp register Ffregc. movfp2iEx: movfp2i r3,f0

26、Rregc - FfregaCopies one word from fp register Ffrega to integer register Rregc. movi2fpEx: movi2fp f0,r3Ffregc - RregaCopies one word from integer register Rrega to fp register Ffregc. movi2sEx: movi2s r1UnspecifiedCopies one word from integer register Rrega to a special register. movs2iEx: movs2i

27、r2UnspecifiedCopies one word from a special register to integer register Rrega. multEx: mult f2,f3,f4Ffregc - Ffrega * FfregbAll are signed integers. multdEx: multd f2,f4,f6Ddregc - Ddrega * DdregbAll are double precision floats. multfEx: multf f3,f4,f5Ffregc - Ffrega * FfregbAll are single precisio

28、n floats. multuEx: multu f2,f3,f4Ffregc - Ffrega * FfregbAll are unsigned integers. nedEx: ned f8,f6if (Ddrega != Ddregb) fps = 1 else fps = 0Both are double precision floats. nefEx: nef f3,f6if (Ffrega != Ffregb) fps = 1 else fps = 0Both are single precision floats. nopEx: nopIdles one cycle. orEx:

29、 or r2,r3,r4Rregc - Rrega | RregbAll are unsigned integers. Logical or is performed on a bitwise basis. oriEx: ori r3,r4,#5Rregb - Rrega | uimm16All are unsigned integers. Logical or is performed on a bitwise basis. rfeEx: rfeUnspecifiedReturn from exception. sbEx: sb label-41(r3),r2Mimm16 + Rrega -

30、8 Rregb_24.31One byte of data from the least significant byte of register Rregb is written to the effective address computed by adding signed integer imm16 and signed integer Rrega. sdEx: sd 200(r4),f6Mimm16 + Rrega -64 DdregbTwo words from double register Ddregb are written to the effective address

31、 computed by adding signed integer imm16 and signed integer Rrega. seqEx: seq r1,r2,r3if (Rrega = Rregb) Rregc - 1 else Rregc - 0All are signed integers. seqiEx: seqi r14,r3,#3if (Rrega = imm16) Rregb - 1 else Rregb - 0All are signed integers. sfEx: sf 121(r3),f1Mimm16 + Rrega = Rregb) Rregc - 1 els

32、e Rregc = imm16) Rregb - 1 else Rregb = Rregb) Rregc - 1 else Rregc = uimm16) Rregb - 1 else Rregb Rregb) Rregc - 1 else Rregc imm16) Rregb - 1 else Rregb Rregb) Rregc - 1 else Rregc uimm16) Rregb - 1 else Rregb - 0All are unsigned integers. shEx: sh 421(r3),r5Mimm16 + Rrega -16 Rregb_16.31Two bytes

33、 of data from the least significant half of register Rregb are written to the effective address computed by adding signed integer imm16 and unsigned integer Rrega. The effective address must be halfword aligned. sleEx: sle r1,r2,r3if (Rrega = Rregb) Rregc - 1 else Rregc - 0All are signed integers. s

34、leiEx: slei r8,r5,#345if (Rrega = imm16) Rregb - 1 else Rregb - 0All are signed integers. sleuEx: sleu r1,r2,r3if (Rrega = Rregb) Rregc - 1 else Rregc - 0All are unsigned integers. sleuiEx: sleui r8,r5,#345if (Rrega = uimm16) Rregb - 1 else Rregb - 0All are unsigned integers. sllEx: sll r6,r7,r11Rre

35、gc - Rrega Rregb_27.31All are unsigned integers. Rrega is logically shifted left by the low five bits of Rregb. Zeros are shifted into the least-significant bit. slliEx: slli r1,r2,#3Rregb - Rrega uimm16_27.31All are unsigned integers. Rrega is logically shifted left by the low five bits of uimm16.

36、Zeros are shifted into the least-significant bit. (Actually only the bottom five bits of Rregb are used.) slt Ex: slt r3,r4,r5if (Rrega Rregb) Rregc - 1 else Rregc - 0All are signed integers. sltiEx: slti r1,r2,#22if (Rrega imm16) Rregb - 1 else Rregb - 0All are signed integers. sltuEx: sltu r3,r4,r

37、5if (Rrega Rregb) Rregc - 1 else Rregc - 0All are unsigned integers. sltuiEx: sltui r1,r2,#22if (Rrega uimm16) Rregb - 1 else Rregb - 0All are unsigned integers. sneEx: sne r1,r2,r3if (Rrega != Rregb) Rregc - 1 else Rregc - 0All are signed integers. sneiEx: snei r4,r5,#89if (Rrega != imm16) Rregb -

38、1 else Rregb - 0All are signed integers. sraEx: sra r1,r2,r3Rregc Rregb)_Rregb.31Rrega and Rregc are signed integers. Rregb is an unsigned integer. Rrega is arithmetically shifted right by Rregb. The sign bit is shifted into the most-significant bit. (Actually uses only the five low order bits of Rr

39、egb.) sraiEx: srai r2,r3,#5Rregb uimm16)_uimm16.31Rrega and Rregc are signed integers. uimm16 is an unsigned integer. Rrega is arithmetically shifted right by Rregb. The sign bit is shifted into the most-significant bit. (Actually uses only the five low order bits of uimm16.) srlEx: srl r15,r2,r3Rre

40、gc Rregb_27.31All are unsigned integers. Rrega is arithmetically shifted right by Rregb. Zeros are shifted into the most significant bit. srliEx: srli r1,r2,#5Rregb uimm16_27.31All are unsigned integers. Rrega is arithmetically shifted right by uimm16. Zeros are shifted into the most significant bit

41、. subEx: sub r3,r2,r1Ex: Rregc - Rrega - RregbAll are signed integers. subdEx: subd f2,f4,f6Ddregc - Ddrega - DdregbAll are double precision floats. subfEx: subf f3,f4,f6Ffregc - Ffrega - FfregbAll are single precision floats. subiEx: subi r15,r16,#964Rregb - Rrega - imm16All are signed integers. su

42、buEx: subu r3,r2,r1Rregc - Rrega - RregbAll are unsigned integers. subuiEx: subui r1,r2,#53Rregb - Rrega - uimm16All are unsigned integers. swEx: sw 21(r13),r6Mimm16 + Rrega - RregbOne word from integer register Rregb is written to the effective address computed by adding signed integer imm16 and un

43、signed integer Rrega. trapEx: trap #3Execute trap with number in immediate fieldSaves state and jumps to an operating system procedure located at an address in the interrupt vector table. In our systems, this is simulated by calling the procedure corresponding to the trap number. xorEx: xor r2,r3,r4

44、Rregc - Frega XOR RregbAll are unsigned integers. Logical xor is performed on a bitwise basis. xoriEx: xori r3,r4,#5Rregb - Rrega XOR uimm16All are unsigned integers. Logical xor is performed on a bitwise basis. Instruction EncodingThe general instruction layout for DLX is shown on page 99 of H&P (2

45、nd Ed.). This specifies the encodings (the 6-bit opcode and the 11-bit function code) assumed in the BYU ECEn Departments tool set. (This is not intended to be compatible with DLX tools from any other source. Encodings were chosen to keep things simple.) The following is a portion of an include file

46、 used by the assembler and simulator. Note that it defines a struct for each instruction, specifying (1) the mnemonic used by the assembler and disassemblers, (2) the 6 bit opcode value, (3) the value used in the func bits. /* dlxdef.h */struct mapper char *name; int op; int func; int optype;struct

47、mapper mainops = special, 0 x00, 0 x00, UNIMP, fparith, 0 x01, 0 x00, UNIMP, addi, 0 x02, 0 x00, REG2IMM, addui, 0 x03, 0 x00, REG2IMM, andi, 0 x04, 0 x00, REG2IMM, beqz, 0 x05, 0 x00, REGLAB, bfpf, 0 x06, 0 x00, LEXP16, bfpt, 0 x07, 0 x00, LEXP16, bnez, 0 x08, 0 x00, REGLAB, j, 0 x09, 0 x00, LEXP26

48、, jal, 0 x0a, 0 x00, LEXP26, jalr, 0 x0b, 0 x00, IREG1, jr, 0 x0c, 0 x00, IREG1, lb, 0 x0d, 0 x00, LOADI, lbu, 0 x0e, 0 x00, LOADI, ld, 0 x0f, 0 x00, LOADD, lf, 0 x10, 0 x00, LOADF, lh, 0 x11, 0 x00, LOADI, lhi, 0 x12, 0 x00, REG1IMM, lhu, 0 x13, 0 x00, LOADI, lw, 0 x14, 0 x00, LOADI, ori, 0 x15, 0

49、x00, REG2IMM, rfe, 0 x16, 0 x00, UNIMP, sb, 0 x17, 0 x00, STRI, sd, 0 x18, 0 x00, STRD, seqi, 0 x19, 0 x00, REG2IMM, sf, 0 x1a, 0 x00, STRF, sgei, 0 x1b, 0 x00, REG2IMM, sgeui, 0 x1c, 0 x00, REG2IMM, /* added instruction */ sgti, 0 x1d, 0 x00, REG2IMM, sgtui, 0 x1e, 0 x00, REG2IMM, /* added instruct

50、ion */ sh, 0 x1f, 0 x00, STRI, slei, 0 x20, 0 x00, REG2IMM, sleui, 0 x21, 0 x00, REG2IMM, /* added instruction */ slli, 0 x22, 0 x00, REG2IMM, slti, 0 x23, 0 x00, REG2IMM, sltui, 0 x24, 0 x00, REG2IMM, /* added instruction */ snei, 0 x25, 0 x00, REG2IMM, srai, 0 x26, 0 x00, REG2IMM, srli, 0 x27, 0 x00, REG2IMM, subi, 0 x28, 0 x00, REG2IMM, subui, 0 x29, 0 x00, REG2IMM, sw, 0 x2a, 0 x00, STRI, trap, 0 x2b, 0 x00, IMM1, xori, 0 x2c, 0 x00, REG2IMM, la, 0 x30, 0 x00, PSEUDO;struct mapper spec = nop, 0 x00, 0 x00, NONEOP, add, 0 x0

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