數(shù)字邏輯設(shè)計及應(yīng)用教學(xué)英文課件：Lec11-Chap 6

1、1Digital Logic Design and ApplicationLecture #11Chapter 6 Combinational Logic Design PracticesDecodersUESTC, Spring 20132Some Useful Combinational ComponentsDecoders（譯碼器）Encoders（編碼器）Three-State Devices（三態(tài)器件）Multiplexers（多路復(fù)用器）Parity Circuits（奇偶校驗電路）Comparators（比較器）Adders（加法器）36.4 DecodersOne-to-one

2、 mapping between input code and output code (一一映射)Multiple-Input, Multiple-Output Logic Circuit(多入多出)Enable Inputs must be asserted to perform normal mapping function（使能端可控制允許譯碼或禁止譯碼）enableinputsInputcord wordoutput cord word Map 譯碼是編碼的逆過程。譯碼器是可以將輸入二進制代碼的狀態(tài)翻譯成輸出信號，以表示其原來含義的電路。6.4 DecodersBinary Deco

3、der（二進制譯碼器）Also known as: 變量譯碼器/最小項譯碼器/m中取一譯碼器Map n bits input to m bits(m2n).將n位輸入變?yōu)閙(m2n)位輸出output code indicates the combination state of the of input.輸出表示輸入的狀態(tài)Output corresponds to each combination of input is 1 only. 對應(yīng)于每個輸入組合的輸出為1的情況僅一次任何需要在眾多可選設(shè)備中獨立驅(qū)動一項的情況都可以用二進制編碼器。用于作寄存器地址譯碼或作指令譯碼4Binary co

4、deOne- out-of-m6.4 DecodersCode system conversion decoder碼制轉(zhuǎn)換譯碼器8421-to-Decimal 74LS428Digital display decoder數(shù)字顯示譯碼器，用于驅(qū)動LED或LCD等發(fā)光器件，用于顯示十進制數(shù)字。Seven segment decoder 74Ls47566.4 Decoders2-4 Binary Decoder(2-4譯碼器)2-to-4decoderY0Y1Y2Y3I0I1EN 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1

5、 1 1 0 0 0InputsEN I1 I0Outputs Y3 Y2 Y1 Y0Truth table for a 2-to-4 binary decoderMSBLSBMSBLSBAll outputs are active high.76.4 Decoders 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0InputsEN I1 I0Outputs Y3 Y2 Y1 Y0Truth table for a 2-to-4 binary decoderY0 = EN ( I1 I0 )Y1 = E

6、N ( I1 I0 )Y2 = EN ( I1 I0 )Y3 = EN ( I1 I0 )Yi = EN mi All outputs are active high.6.4 Decoders8Input: n-bit binaryOutput: 1-out-of-2n2-4 Binary Decoder (2-4譯碼器)Yi = EN mi 6.4 Decoders二進制譯碼器可以看做是最小項發(fā)生器，每個輸出代表n輸入函數(shù)的一個最小項。一個n變量輸入的變量譯碼器，其輸出包含了n個輸入變量的全部最小項。用n變量譯碼器加上邏輯或門就能實現(xiàn)任何形式的n變量組合邏輯函數(shù)。910The 74x139

7、dual 2-to-4 Decoder 74x139 1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1InputsG iB iAOutputs iY3_L iY2_L iY1_L iY0_LTruth Table for 1/2 74x139TTL family ：LS，S，AS, ALCMOS family：H,HCT,VHCT , AC110 0 0 0 0 0 0 10 0 0 0 0 0 1 00 0 0 0 0 1 0 00 0 0 0 1 0 0 00 0 0 1 0 0 0 00 0 1 0

8、 0 0 0 00 1 0 0 0 0 0 01 0 0 0 0 0 0 00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1I2I1I0Y7Y1Y0Y2Y3Y4Y5Y6Truth Table for a 3-to- 8 Binary Decoder 3-to-8decoderI0I1I2Y0Y1Y7Yi = mi1 1 1 1 1 1 1 01 1 1 1 1 1 0 11 1 1 1 1 0 1 11 1 1 1 0 1 1 11 1 1 0 1 1 1 11 1 0 1 1 1 1 11 0 1 1 1 1 1 10 1 1 1 1 1 1 1All out

9、puts are active low.6.4 DecodersYi _L= mi=Mi3-8 Binary Decoder6.4 Decoders12 Y0Y1Y2Y3Y0Y1Y2Y3I0I1ENENI0I1I23-to-8 decoderY0Y1Y7Y2Y3Y4Y5Y63-8 Binary Decoder (3-8譯碼器)2-to-4 decoderI0I1EN13The 74x138 3-to-8 DecoderG1G2A_LG2B_LY3 = G1G2AG2B CBAenableselectY3_L = Y3 = (G1G2A_LG2B_L CBA)= G1 + G2A_L + G2B

10、_L + C+B+AMSBLSBYi = EN mi14logic diagram for the 74x138 3-to-8 decoder153. Logic Symbols for Large-Scale Element Y0Y1Y2Y3GAB1/2 74x139Y0Y1Y2Y3GAB1/2 74x139Y0Y1Y2Y3GAB1/2 74x139G_LABY0_LY1_LY2_LY3_L correct butto be avoidedincorrect大規(guī)模元件總是依據(jù)其符號框內(nèi)實現(xiàn)的功能來定義信號名 164. Cascading Binary Decoders 74x139 EN17

11、N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_LConsider:How many 74x138s do you need? Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2At any time only one chip is working.In 4 inputs,which should be used to select devices?and which should be used to perform input?Design of a 4-to-16 decoder using 74x138s18How many 74x138s to be

12、 used for 32 outputs?How to control that only one chip works at any time? Use the enable inputsControl inputs of three low-order bits of a 5-bit code wordControl chips of two high-order bits of a 5-bit code word Use 2-to-4 decoder/ 3-to-8 decoderFig.6-37 Design of a 5-to-32 decoder using 74x138sN3N4

13、ENG2A_L for Chip 1G2A_L for Chip 2G2A_L for Chip 3G2A_L for Chip 4Y0Y7Y8Y15Y16Y23Y24Y31y0y1y2y3I0I1EN195. Realize logic functions using decodersExample: build the following logic function using 74x138 and gate. F = (X,Y,Z) (0,3,6,7) Yi = ENmi when the decoder is enabled, Yi = miwith active-low outpu

14、ts: Yi_L = Yi= mi = Mi ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x13820Example 1. Sum of Products form (積之和形式)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF = (X,Y,Z) (0,3,6,7)When all of enable inputs are asserted, output Yi = miConfirm the LSB and MSB21Example 1. Sum of Products form(積之和形式)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y

15、5Y6Y774x138+5VFF = (X,Y,Z) (0,3,6,7)22= M1 M2 M4 M5= m1 m2 m4 m5F = (X,Y,Z) (0,3,6,7) = (X,Y,Z) ( 1, 2, 4, 5 )ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFExample 2. Product of Sums form(和之積形式)Yi_LQuiz:用3-8譯碼器能否實現(xiàn)變量多于3個的函數(shù)？236. BCD Decoder (4-to-10 decoder)Inputs: 4-bit BCD code（or binary code ）Outputs:

16、1-out-of 10 code Y0Y9I0I1I2I3多余的6個狀態(tài)如何處理？ 輸出均無效：拒絕“翻譯” 作為任意項處理 電路內(nèi)部結(jié)構(gòu)簡單 24二-十進制譯碼器0 0 0 0 0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10 1 1 1 1 1 1 1 1 11 0 1 1 1 1 1 1 1 11 1 0 1 1 1 1 1 1 11 1 1 0 1 1 1 1 1 11 1 1 1 0 1 1 1 1 11 1 1 1 1

17、0 1 1 1 11 1 1 1 1 1 0 1 1 11 1 1 1 1 1 1 0 1 11 1 1 1 1 1 1 1 0 11 1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1I3 I2 I1 I00123456789Y0_L Y9_L偽碼Arbitrary term257. Seven-Segment Decodersabcdefgdpcommunity cathodeHigh level assertedabcdefgdpNormally use:light-emittin