嵌入式軟件系統(tǒng)設(shè)計(jì)：08_memory

1、1Embedded System Architecture lecture 08-MemoryJun WANG2ContentsMemory array overviewType of memoryRAMSRAMDRAMROMLogic by memoryFPGA3Memory ArraysEfficiently store large amounts of dataThree common types:Dynamic random access memory (DRAM)Static random access memory (SRAM)Read only memory (ROM)An M-

2、bit data value can be read or written at each unique N-bit address.4Two-dimensional array of bit cells Each bit cell stores one bitAn array with N address bits and M data bits:2N rows and M columnsDepth: number of rows (number of words)Width: number of columns (size of word)Array size: depth width =

3、 2N M Memory Arrays522 3-bit arrayNumber of words: 4Word size: 3-bitsFor example, the 3-bit word stored at address 10 is 100Memory Array: ExampleExample:6Memory Arrays7Memory Array Bit CellsExample:8Memory Array Bit CellsExample:01ZZ9Wordline: similar to an enableallows a single row in the memory ar

4、ray to be read or writtencorresponds to a unique addressonly one wordline is HIGH at any given timeMemory Array10Types of MemoryRandom access memory (RAM): volatileRead only memory (ROM): nonvolatile11RAM: Random Access MemoryVolatile: loses its data when the power is turned offRead and written quic

5、klyMain memory in your computer is RAM (DRAM)Historically called random access memory because any data word can be accessed as easily as any other (in contrast to sequential access memories such as a tape recorder)12ROM: Read Only MemoryNonvolatile: retains data when power is turned offRead quickly,

6、 but writing is impossible or slowFlash memory in cameras, thumb drives, and digital cameras are all ROMsHistorically called read only memory because ROMs were written at manufacturing time or by burning fuses. Once ROM was configured, it could not be written again. This is no longer the case for Fl

7、ash memory and other types of ROMs.13Types of RAMTwo main types of RAM:Dynamic random access memory (DRAM)Static random access memory (SRAM)Differ in how they store data:DRAM uses a capacitorSRAM uses cross-coupled inverters14Robert Dennard, 1932 -Invented DRAM in 1966 at IBMOthers were skeptical th

8、at the idea would workBy the mid-1970s DRAM was in virtually all computers15Data bits stored on a capacitorCalled dynamic because the value needs to be refreshed (rewritten) periodically and after being read:Charge leakage from the capacitor degrades the valueReading destroys the stored valueDRAM16D

9、RAM17SRAM18Memory ArraysDRAM bit cell:SRAM bit cell:19ROMs: Dot Notation20Fujio Masuoka, 1944-Developed memories and high speed circuits at Toshiba from 1971-1994. Invented Flash memory as an unauthorized project pursued during nights and weekends in the late 1970s. The process of erasing the memory

10、 reminded him of the flash of a camera Toshiba slow to commercialize the idea; Intel was first to market in 1988 Flash has grown into a $25 billion per year market.21ROM Storage22ROM LogicData2 = A1 A0Data1 = A1 + A0Data0 = A1A023Example: Logic with ROMsImplement the following logic functions using

11、a 22 3-bit ROM:X = ABY = A + BZ = AB24Example: Logic with ROMsImplement the following logic functions using a 22 3-bit ROM:X = ABY = A + BZ = A B25Logic with Any Memory ArrayData2 = A1 A0Data1 = A1 + A0Data0 = A1A026Logic with Memory ArraysImplement the following logic functions using a 22 3-bit mem

12、ory array:X = ABY = A + BZ = A B27Logic with Memory ArraysCalled lookup tables (LUTs): look up output at each input combination (address)28Multi-ported MemoriesPort: address/data pair3-ported memory2 read ports (A1/RD1, A2/RD2)1 write port (A3/WD3, WE3 enables writing)Small multi-ported memories are

13、 called register files29/ 256 x 3 memory module with one read/write portmodule dmem(input clk, we, input 7:0 ainput 2:0 wd, output 2:0 rd); reg 2:0RAM255:0; assign rd = RAMa; always (posedge clk) if (we) RAMa = wd;endmoduleVerilog Memory Arrays30Logic ArraysField programmable gate arrays (FPGAs)Arra

14、y of configurable logic blocks (CLBs)LUT as key componentPerform combinational and sequential logicConfiguration is based on SRAM31FPGAs: Field Programmable Gate ArraysComposed of:CLBs (Configurable logic blocks): perform logicIOBs (Input/output buffers): interface with outside worldProgrammable interconnection: connect CLBs and IOBsSome FPGAs include other building blocks such as multipliers and RAMs32Xilinx Spartan 3 FPGA Schematic33CLBs: Configurable Logic BlocksComposed of:LUTs (lookup tables): perform combinational logicFlip-flops: perform sequential functionsMultiplexers: