嵌入式軟件系統(tǒng)設(shè)計：01_02_03_verilog_combinational

1、1Embedded System Architecture Design-Verilog with Combinational CircuitsDigital System, SMIESYSU2Research Topics 1智能視頻傳輸 Intelligent Video transmission應(yīng)用場合可穿戴設(shè)備/智能硬件Google glass智能移動終端Smart phone、Pad車聯(lián)網(wǎng)/物聯(lián)網(wǎng)車載多媒體監(jiān)控網(wǎng)絡(luò)科學問題視頻壓縮Content based compressionTriple play機器視覺Super resolutionGaze detectionDigital

2、System, SMIESYSU32022/7/213Evolution of Handsets and TechnologyNokia Version Digital System, SMIESYSU42022/7/214Evolution of Handsets and TechnologyiPhone Version Digital System, SMIESYSU5Research Topics 2CPU設(shè)計應(yīng)用場合國產(chǎn)化系統(tǒng)開源化系統(tǒng)差異化系統(tǒng)智能硬件、物聯(lián)網(wǎng)科學問題多核運算異構(gòu)運算CPU+GPU+FPGADigital System, SMIESYSU6AchievementChi

3、p for video transmission (co-work with Toshiba)Primitive Demonstration for “Pupil-Corneal Reflection based Vision Capture”Low power based ARM Cortex M0 compatible Processor design3rd prize of National electronics design contest supported by Xilinx30% power saved vs. original Cortex M0Embedde System

4、Architecture Design7ContentsLecture IntroductionEmbedded systemVerilog for combinational logicEmbedde System Architecture Design88OverviewNovel lecture2.5 traditional lectures involvedEDA practice (1)HDL leant by exampleComputer architecture (0.5)Embedded architecture (1)Introduced from UCBerkley an

5、d Waseda葛守仁(Ernest S.Kun), 后藤敏(Satoshi Goto)Design by HDLImplemented in FPGAXilinx Nexys3Embedde System Architecture Design999OverviewProjectCPU DesignVery useful for Job HuntingEvaluation10% attendance30% Lab50% Project10% Exam (not fixed)Embedde System Architecture Design1010OverviewPlanning (15)H

6、DL for Combination Logic (2)HDL for Sequential Logic (4)Memory (1)Embedded CPU design (8)TextbooksDigital Design and Computer Architecture, David Money Harris and Sarah L. Harris, published by Morgan Kaufmann, 2007Given Lab Tutorial Lecture Notes more importantTAwebsiteEmbedde System Architecture De

7、sign11What is Embedded System?An embedded system is a special-purpose system in which the computer is completely encapsulated by the device it controls.An embedded system performs pre-defined tasks, usually with very specific requirements.Mobile phones, MP3 Players, Digital Cameras are very common e

8、mbedded systems in our life.Embedde System Architecture Design12What is Embedded System?Since the system is dedicated to a specific task, design engineers can optimize it, reducing the size and cost of the product.Embedded systems are often mass-produced, so the cost savings may be multiplied by mil

9、lions of items.Embedde System Architecture Design13Embedded System DesignComponents of embedded system:HardwareProcessor, memory, ASIC, controllers, peripheralsFirmware/softwareBoot loader, embedded OS, device drivers, applicationsDesign and Development Skills:HDL: Verilog, VHDL I/O, analog and digi

10、tal interfacing, peripherals Development kits: Compiler, linker Firmware design: Assembly and Low-level C languageDevice driver designEmbedded operating system design or portingSystem programming: System calls, IPC, Socket Application software design: JAVA, C+ Embedde System Architecture Design14Exa

11、mple: Digital camera hardware block diagramEmbedded System DesignProcessorCoreMemoryInterfacePIOInterfaceUSBControllerADCDSPImageCodecSDRAMSRAMFlashSPILCDControllerRTCSoCEmbedde System Architecture Design15Embedded System DesignExample: Digital camera firmware/softwareLow level initializing code (Bo

12、ot loader)Device drivers: LCD, Sensor, SD Card Embedded OSGUIImage CapturerImage ProcessingSystem ConfigureFile ManagerEmbedde System Architecture Design16Embedded System Design IssuesCost and PerformanceLowering the cost affects the speed of embedded system.Most often speed issue doesnt matter and

13、one achieves the task at lower cost.Simplifying the hardware allows cost reduction.Specifications and User ConstraintsSpecifications define that what task is to be achieved.The constraints help the designer to select appropriate hardware and software setup to develop an embedded system.Embedde Syste

14、m Architecture Design17Embedded System Design IssuesCPU ArchitectureARM or MIPS or ?Storage Size and SpeedSDRAM or DDR ?RAM, ROM, Flash memory size ?InterfacesPIO or RS232 or ?Touch screen or keypad ?Development kitsGNU tools or others ?Embedded OSReal-time or not?Kernel size ?Multi-task supported ?

15、Easy to port ?Embedded ApplicationsImplement with C, C+ or JAVA ?GUI: Microwindows or MiniGUI or ?Selection of hardware and software of an embedded systemEmbedde System Architecture Design18Embedded Hardware DesignHardware Design TechnologySystem on a Chip (SoC)Integrating all components of a comput

16、er or other electronic system into a single chip.System on a Programmable Chip (SoPC)SoPC is a family of mixed-signal arrays made by Cypress Semiconductor, featuring a microcontroller and integrated analog and digital peripherals.Embedde System Architecture Design19Embedded Hardware DesignFigure: So

17、C Design Flow (Top-half)Source: Wikipedia, the free encyclopedia 1 Embedde System Architecture Design20Embedded Hardware DesignFigure: SoC Design Flow (Bottom-half)Source: Wikipedia, the free encyclopedia 1 Embedde System Architecture Design21Embedded Hardware DesignHardware Description Language (HD

18、L)VHDL and VerilogThe two most widely-used and well-supported HDL varieties used in industry.Others includeABEL (Advanced Boolean Expression Language)AHDL (Altera HDL, a proprietary language from Altera)JHDL (based on Java)Lava (based on Haskell)MyHDL (based on Python)PALASMRHDL (based on Ruby) Embe

19、dde System Architecture Design22Embedded Hardware DesignDesign, Synthesis ToolsAlteraQuartus IIXilinxISESynplicitySynplifySimulation ToolsModel TechnologyModelSimEmbedde System Architecture Design2323Hardware description language (HDL): specifies logic function onlyComputer-aided design (CAD) tool p

20、roduces or synthesizes the optimized gatesMost commercial designs built using HDLsTwo leading HDLs:SystemVerilogdeveloped in 1984 by Gateway Design AutomationIEEE standard (1364) in 1995Extended in 2005 (IEEE STD 1800-2009)VHDL 2008Developed in 1981 by the Department of DefenseIEEE standard (1076) i

21、n 1987Updated in 2008 (IEEE STD 1076-2008)Hardware Description LanguageEmbedde System Architecture Design2424Hardware Description LanguageVerilog HDLIntroduced by Gateway Design System Corporation, now a part of Cadence Design SystemsC like descriptionVs. VHDL (the other popular HDLVHDL is Ada-like

22、language a little bit higher level of abstraction than that of VerilogHardware structure can be modelled equally effectively in both languagesThe choice of which to use, is therefore not based on technical capability, but on personal preferences, tool availability or business issuesWe use Verilog/ S

23、ystemVerilogEmbedde System Architecture Design2525Simulation How to use tool will be shown in Lab session Inputs applied to circuitOutputs checked for correctnessMillions of dollars saved by debugging in simulation instead of hardwareSynthesis How to use tool will be shown in Lab session Transforms

24、HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them)IMPORTANT:When using an HDL, think of the hardware the HDL should produceHDL to GatesEmbedde System Architecture Design2626Three types of Modules:Behavioral: describe what a module doesSequential log

25、icData-Flow: describe how data flowsCombinational logicStructural: describe how it is built from simpler modulesPrimitive logicSystemVerilog ModulesEmbedde System Architecture Design2727module example(input logic a, b, c, output logic y); assign y = a & b & c | a & b & c | a & b & c;EndmoduleVerilog

26、:module example(input wire a, b, c, output wire y); assign y = a & b & c | a & b & c | a & b & c;EndmoduleOR:module example (a, b, c, y);input a, b, c;output y;wire y;SystemVerilog:Data-Flow Modelingwire can be omitted, but not recommendedEmbedde System Architecture Design2828HDL Simulationmodule ex

27、ample(input logic a, b, c, output logic y); assign y = a & b & c | a & b & c | a & b & c;endmoduleSystemVerilog:Think in hardware, always waiting for input change, NOT like C, executed only once.a, b, c are sensitive listEmbedde System Architecture Design2929HDL Synthesismodule example(input logic a

28、, b, c, output logic y); assign y = a & b & c | a & b & c | a & b & c;endmoduleSystemVerilog:Synthesis:Embedde System Architecture Design3030Case sensitiveExample: reset and Reset are not the same signal.No names that start with numbers Example: 2mux is an invalid nameWhitespace ignoredComments:/ si

29、ngle line comment/* multiline comment */SystemVerilog SyntaxEmbedde System Architecture Design3131module and3(input logic a, b, c, output logic y); assign y = a & b & c;endmodulemodule inv(input logic a, output logic y); assign y = a;endmodulemodule nand3(input logic a, b, c output logic y); logic n

30、1; / internal signal and3 andgate(a, b, c, n1); / instance of and3 inv inverter(n1, y); / instance of inverterendmoduleStructural Modeling - HierarchyEmbedde System Architecture Design3232module gates(input logic 3:0 a, b, output logic 3:0 y1, y2, y3, y4, y5); /* Five different two-input logic gates

31、 acting on 4 bit busses */ assign y1 = a & b; / AND assign y2 = a | b; / OR assign y3 = a b; / XOR assign y4 = (a & b); / NAND assign y5 = (a | b); / NORendmodule/ single line comment/*/ multiline comment Bitwise OperatorsEmbedde System Architecture Design3333module and8(input logic 7:0 a, output lo

32、gic y); assign y = &a; / &a is much easier to write than / assign y = a7 & a6 & a5 & a4 & / a3 & a2 & a1 & a0;endmoduleReduction OperatorsEmbedde System Architecture Design3434module mux2(input logic 3:0 d0, d1, input logic s, output logic 3:0 y); assign y = s ? d1 : d0; endmodule? : is also called

33、a ternary operator because it operates on 3 inputs: s, d1, and d0.Conditional AssignmentEmbedde System Architecture Design3535module fulladder(input logic a, b, cin, output logic s, cout); logic p, g; / internal nodes assign p = a b; assign g = a & b; assign s = p cin; assign cout = g | (p & cin);en

34、dmoduleInternal VariablesEmbedde System Architecture Design3636NOT*, /, %mult, div, mod+, -add,subshiftarithmetic shift, , =comparison=, !=equal, not equal&, &AND, NAND, XOR, XNOR|, |OR, NOR?:ternary operatorOrder of operationsHighestLowestPrecedenceEmbedde System Architecture Design3737Number# Bits

35、BaseDecimal EquivalentStored3b1013binary5101b11unsizedbinary30000118b118binary3000000118b1010_10118binary171101010113d63decimal61106o426octal341000108hAB8hexadecimal1711010101142Unsizeddecimal42000101010Format: NBvalueN = number of bits, B = baseNB is optional but recommended (default is decimal)Num

36、bersEmbedde System Architecture Design3838assign y = a2:1, 3b0, a0, 6b100_010;/ if y is a 12-bit signal, the above statement produces:y = a2 a1 b0 b0 b0 a0 1 0 0 0 1 0/ underscores (_) are used for formatting only to make it easier to read. SystemVerilog ignores them. Bit Manipulations: Example 1Emb

37、edde System Architecture Design3939module mux2_8(input logic 7:0 d0, d1, input logic s, output logic 7:0 y); mux2 lsbmux(d03:0, d13:0, s, y3:0); mux2 msbmux(d07:4, d17:4, s, y7:4);endmoduleBit Manipulations: Example 2SystemVerilog:Embedde System Architecture Design4040module tristate(input logic 3:0

38、 a, input logic en, output logic 3:0 y); assign y = en ? a : 4bz;endmoduleZ: Floating OutputSystemVerilog:Embedde System Architecture Design4141timescale 1ns/1ps /timescale directive with unit/precisionmodule example(input logic a, b, c, output logic y); logic ab, bb, cb, n1, n2, n3; assign #1 ab, b

39、b, cb = a, b, c; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3;endmodule Delays (CANOT be synthesized)Embedde System Architecture Design4242module example(input logic a, b, c, output logic y); logic ab, bb, cb, n1, n2, n3; assign #1 ab

40、, bb, cb = a, b, c; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3;endmodule DelaysEmbedde System Architecture Design4343HDL that tests another module: device under test (dut)Not synthesizeableTypes:SimpleSelf-checkingSelf-checking with

41、 testvectorsUse tools to check waveformsTestbenchesEmbedde System Architecture Design4444Write SystemVerilog code to implement the following function in hardware: y = bc + abName the module sillyfunctionTestbench ExampleEmbedde System Architecture Design4545Write SystemVerilog code to implement the

42、following function in hardware: y = bc + abmodule sillyfunction(input logic a, b, c, output logic y); assign y = b & c | a & b;endmoduleTestbench ExampleEmbedde System Architecture Design4646module testbench1(); logic a, b, c; logic y; / instantiate device under test sillyfunction dut(a, b, c, y); /

43、 apply inputs one at a time initial begin a = 0; b = 0; c = 0; #10; c = 1; #10; b = 1; c = 0; #10; c = 1; #10; a = 1; b = 0; c = 0; #10; c = 1; #10; b = 1; c = 0; #10; c = 1; #10; endendmodule Simple TestbenchExecuted when simulation started, Executed only once, not like always, discussed laterEmbed

44、de System Architecture Design4747module testbench2(); logic a, b, c; logic y; sillyfunction dut(a, b, c, y); / instantiate dut initial begin / apply inputs, check results one at a time a = 0; b = 0; c = 0; #10; if (y != 1) $display(000 failed.); c = 1; #10; if (y != 0) $display(001 failed.); b = 1;

45、c = 0; #10; if (y != 0) $display(010 failed.); c = 1; #10; if (y != 0) $display(011 failed.); a = 1; b = 0; c = 0; #10; if (y != 1) $display(100 failed.); c = 1; #10; if (y != 1) $display(101 failed.); b = 1; c = 0; #10; if (y != 0) $display(110 failed.); c = 1; #10; if (y != 0) $display(111 failed.

46、); endendmodule Self-checking TestbenchEmbedde System Architecture Design4848SummaryThree Very Important concepts in HDL:1, Think in hardwareassign- always waiting 2, Register-Wire, Register-Transmission, Sequential Logic- Combinational Logic3, Not synthesizeable and synthesizeableassign can, # cann

47、ot, Testbench cannot Embedde System Architecture Design49Two-Input MUXmodule Mux2 (A, / A inputB,/ B inputSel,/ SelectorY/ Output);/ Port modesinput A,B,Sel;output Y; / Registered identifiersreg Y;/ Functionalityalways (A or B or Sel)if (Sel=0)Y = A;elseY = B;endmodule always (A or B or Sel)Y = (Sel) ? B : A;module Mux2 (input A, / A inp