東北大學(xué)實(shí)時(shí)信號(hào)處理大作業(yè)

1、 實(shí)時(shí)信號(hào)處理 實(shí)驗(yàn)報(bào)告 課名：實(shí)時(shí)信號(hào)處理 課程號(hào)：B130500151 班級(jí)：電子1303班 學(xué)號(hào)：20217680 姓名：丁翊第一題： 1計(jì)算基準(zhǔn)數(shù)你的學(xué)號(hào)對(duì) 3 的余數(shù)，你的學(xué)號(hào)對(duì) 5 的余數(shù)，你的學(xué)號(hào)對(duì) 7 的余數(shù)。 2計(jì)算并設(shè)計(jì) 11 階的半波帶濾波器 F5 的 RAG， 求出系數(shù)，給出計(jì)算具體過(guò)程，畫出 RAG 模塊的電路簡(jiǎn)圖，并指出加法器的路徑延遲。 3如果輸入位寬為 8，那么該濾波器的最小輸出位寬是多少？ 4編寫該濾波器的 HDL 代碼并用 Modelsim 進(jìn)行仿真。 5基于分布式算法，用狀態(tài)機(jī)方法和已經(jīng)實(shí)現(xiàn)的 LPM_ROM 表或類似方式編寫該濾波器的 HDL 代碼并用

2、Modelsim1： 20217680=6712560*3+0; 20217680=4027536*5+0; 20217680=2876811*7+3;余數(shù)之和：0+0+3=3；2：f0=259=100000011B 本錢為2f+1=153=10011001B 本錢為3f+3=-28=-11100B 本錢為1f+5=6=110B 本錢為16=(1+2)*2,7=(1+2+4)*4,153=(32+4)*4-(1+2+4)259=256+(1+2)x3=2x+x;時(shí)延為1 x7=x3+4xz-1;時(shí)延為2 x259=256x+x3z-1;時(shí)延為2x40=32xz-1+8xz-1;時(shí)延為2 x15

3、3=4x40-x7;時(shí)延為33： min=-259*128-153*127-28*128-6*127=-56929max=259*127+153*128+28*127+6*128=56801max-min=113730=217 輸出位寬為174：程序：PACKAGE seventeen_bit_int IS SUBTYPE BYTE IS INTEGER RANGE -128 TO 127;SUBTYPE TWO_BYTE IS INTEGER RANGE -32768 TO 32767;SUBTYPE SEVENTEEN_BIT IS INTEGER RANGE -65536 TO 6553

4、5;TYPE ARRAY_SEVENTEEN_BIT IS ARRAY (0 TO 5) OF SEVENTEEN_BIT;END seventeen_bit_int;LIBRARY work;USE ;LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ;ENTITY lvboqi IS PORT (clk : IN STD_LOGIC; x : IN BYTE; y : OUT SEVENTEEN_BIT);END lvboqi;ARCHITECTURE one OF lvboqi ISSIGNAL t0,t1,t2,t3,t4,t5,tap0,tap

5、1,tap2,tap3,tap4,tap5,tap_1,tap_2,tap_3,tap_4,tap_5: SEVENTEEN_BIT:=0;BEGIN p1: PROCESS(clk) BEGINIF clkevent and (clk = 1) THEN - 6,-28,153,259,153,-28,6. t0=x;-1t1=2*t0+t0;-3t2=256*t0+t1;-259t3=4*t0+t1;-7t4=16*t0+4*t0;-20t5=8*t4-t3;-153tap5=2*t1;-6tap4=tap5;tap3=-4*t3+tap4;- -28+6tap2=tap3;tap1=t5

6、+tap2;-153+6-28tap0=t2+tap1;-259+153+6-28tap_1=t5+tap0;-153+259+.tap_2=tap_1;tap_3=-4*t3+tap_2;- -28+153+.tap_4=tap_3;tap_5=tap_4+2*t1; -6=28+.y =tap_5; end if; END PROCESS;END one;(5)基于分布式算法xb5xb4xb3xb2xb1xb0fck,xbn00000000000012590000101530000114120001000000101259000110153000111412001000-280010012

7、31001010125001011384001100-2800110123100111012500111138401000000100012590100101530100114120101000010101259010110153010111412011000-28011001231011010125011011384011100-2801110123101111012501111138410000061000012651000101591000114181001006100101265100110159100111418101000-22101001237101010131101011390

8、101100-2210110123710111013110111139011000061100012651100101591100114181101006110101265110110159110111418111000-22111001227111010131111011390111100-22111101237111110131111111390頂層文件：library ieee;use ieee.std_logic_1164.all;use ;entity ad isport(clk, reset : in std_logic;x0 ,x1,x2,x3,x4,x5 : in std_lo

9、gic_vector(7 downto 0);lut : out integer range -64 to 512;y : out integer range -65536 to 65535);end ad;architecture behave of ad iscomponent case4port(table_in:in std_logic_vector(5 downto 0);table_out:out integer range -64 to 512);end component;type state_type is(s0, s1);signal state : state_type;

10、signal table_in : std_logic_vector(5 downto 0);signal xin0, xin1, xin2 : std_logic_vector(7 downto 0);signal xin3, xin4, xin5 : std_logic_vector(7 downto 0);signal table_out : integer range -64 to 512;begintable_in(0) = xin0(0);table_in(1) = xin1(0);table_in(2) = xin2(0);table_in(3) = xin3(0);table_

11、in(4) = xin4(0);table_in(5) = xin5(0);process(reset, clk)variable p : integer range -65536 to 65535 := 0;variable count : integer range 0 to 8;beginif reset = 1 thenstate state = s1;count := 0;p := 0;xin0 = x0;xin1 = x1;xin2 = x2;xin3 = x3;xin4 = x4;xin5 if count = 8 theny = p;state = s0;elseif coun

12、t = 7 thenp := p - table_out * 64;elsep := p / 2 + table_out * 64;end if;for k in 0 to 6 loopxin0(k) = xin0(k + 1);xin1(k) = xin1(k + 1);xin2(k) = xin2(k + 1);xin3(k) = xin3(k + 1);xin4(k) = xin4(k + 1);xin5(k) = xin5(k + 1);end loop;count := count + 1;state = s1;end if;end case;end if;end process;N

13、0:case4port map(table_in, table_out);lut table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out

14、 table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out table_out

15、 table_out table_out table_out table_out table_out table_out table_out table_out table_out = 0;end case;end process;end behave;y =c0 x0+c1x1+c2x2+c3x3+c4x4 =259*1+153*2-28*3+6*4=5052.Hartly 發(fā)現(xiàn)了一種通過(guò)采用公共子表達(dá)式交叉系數(shù)實(shí)現(xiàn)常系數(shù)濾波器的方法，例如，濾波器其中 3 個(gè)系數(shù)，3 個(gè)系數(shù)的 CSD 編碼如下：從表中可以看到的結(jié)構(gòu)出現(xiàn)了 4 次。如果構(gòu)造一個(gè)臨時(shí)變量，就可以用來(lái)計(jì)算濾波器的輸入。1把 帶入

16、進(jìn)行驗(yàn)證上式。濾波器，其中三個(gè)系數(shù)ak=480,-302,31,yn=480 xn-302xn-1+31xn-22把hn=2xn-xn-1帶入yn=256hn-16hn-32hn-1+hn-1yn=256hn-16hn-32hn-1+hn-1 = 256(2xn-xn-1)-16(2xn-xn-1) -32(2xn-1-xn-2)+(2xn-1-xn-2) =480 xn-302xn-1+31xn-2 直接CSD實(shí)現(xiàn)共需要1+2+2+2=7個(gè)加法器。 子表達(dá)式共享共需要3+1=4個(gè)加法器。3 用 HDL 實(shí)現(xiàn) 8 位輸入的子表達(dá)式共享濾波器，并用 Modelsim 進(jìn)行仿真，輸入向量為你的學(xué)號(hào)

17、的每個(gè)十進(jìn)制位的循環(huán)， 例如學(xué)號(hào)為 20211907， 輸入向量為 x0=2， x1=0，x2=1， x3=3， x4=1， x5=9， x6=0， x7=7。4程序代碼：PACKAGE EIGHT ISSUBTYPE BYTTE IS INTEGER RANGE -128 TO 127;SUBTYPE BYTTE0 IS INTEGER RANGE -131072 TO 131071;END EIGHT;LIBRARY WORK;USE WORK.EIGHT.ALL;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARI

18、TH.ALL;ENTITY second ISPORT(CLK:IN STD_LOGIC; X:IN BYTTE; Y:OUT BYTTE0; EN:IN STD_LOGIC);END second;architecture ONE OF second is SIGNAL XTP1,XTP0,XTP1T:BYTTE:=0;SIGNAL HTP1,HTP2,HTP2T:BYTTE0:=0;BEGINPROCESS(CLK,EN)BEGIN IF(EN=1) THENHTP1=0;HTP2=0;XTP1=0; ELSEIF(CLKEVENT AND CLK =1)THEN HTP1=2*X-XTP

19、1;Y=256*HTP1-16*HTP1-32*HTP2+HTP2;-XTP1=XTP0;-XTP0=X;-TP2=TP1;-Tp1=x;-TP1=2*X-XTP1;XTP1=X;HTP2 CLK,EN = EN,X = X,Y = Y);init : PROCESS - variable declarations BEGIN - code that executes only once WAIT; END PROCESS init; always : PROCESS - optional sensitivity list - ( ) - variable declarations BEGIN

20、 - code executes for every event on sensitivity list WAIT for 50ns;CLK=not CLK;END PROCESS always; X_gen:PROCESS BEGINEN=1;wait for 30ns;EN=not EN;x=2;wait for 100 ns;x=0;wait for 100 ns;x=1;wait for 100 ns;x=3;wait for 100 ns;x=3;wait for 100 ns;x=5;wait for 100 ns;x=1;wait for 100 ns;x=5;wait for

21、100 ns;x=2;wait for 100 ns;x=0;wait for 100 ns;x=1;wait for 100 ns;x=3;wait for 100 ns;x=3;wait for 100 ns;x=5;wait for 100 ns;x=1;wait for 100 ns;x=5;wait for 100 ns;x=2;wait for 100 ns;x=0;wait for 100 ns;x=1;wait for 100 ns;x=3;wait for 100 ns;x=3;wait for 100 ns;x=5;wait for 100 ns;x=1;wait for 100 ns;x=5;wait for 100 ns;x=2;wait for 100 ns;x=0;wait for 100 ns;x=1;wait for 100 ns;x=3;wait for 100 ns;x=3;wait for 100 ns;x=5;wait for 100 ns;x=1;wai