集成電路設計 07 時序邏輯設計課件

集成電路設計第七章

時序邏輯電路設計 DesigningSequentialLogicCircuits1EIS-WuhanUniversity集成電路設計第七章時序邏輯電路設計1EIS-WuhanU綱要基本概念組合邏輯與時序邏輯電路有限狀態(tài)機（FSM）LatchversusRegister鎖存器寄存器動態(tài)鎖存器/寄存器時鐘控制寄存器C2MOS流水線非雙穩(wěn)態(tài)時序電路時序問題2EIS-WuhanUniversity綱要基本概念2EIS-WuhanUniversityLogicCircuits:

(1)CombinationalLogic (2)SequentialLogic7-1基本概念

3EIS-WuhanUniversityLogicCircuits:7-1基本概念

3EISItismemoryless;i.e.,withoutstates.CombinationalCircuitsInputOutputCombinationalLogic

4EIS-WuhanUniversityItismemoryless;CombinationalCombinationalLogicDesignProcedures1.Constructthetruthtable2.Basedonthetruthtable (a)Simplifythelogicandimplementby (i)randomlogicgates (ii)multiplexers (iii)PLA’sorPAL’s (b)ImplementthecircuitbyROM’s5EIS-WuhanUniversityCombinationalLogicDesignPro——SequentialLogicSequentialLogicAsynchronousCircuitsSynchronousCircuits6EIS-WuhanUniversity——SequentialLogicSequentialLDuetothetimedelayproblems(races,hazards,…etc.)peoplerarelydesignsequentialcircuitsinasynchronousapproach.Synchronouscircuitsneedasystemclocktostrobethewholesystem.Itiseasiertocontroltheinputsandstates.Thespeedmaybeslowerinthesynchronouscircuits.7EIS-WuhanUniversityDuetothetimedelayproblemsCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsDQFiniteStateMachine（FSM)8EIS-WuhanUniversityCombinationalclockOutputsStateExternalinputsandstatesastheinputsOutputs，andNextstateClock，edgesensitive（positiveornegative）MealyversusMoorestatemachines9EIS-WuhanUniversityExternalinputsandstatesasMooremachineFF—Flip-Flop

outputdependsonlyonthecurrentstateZ=f(y)potentialimplementationadvantagesinspeedandsize；initialstateFFCombinationalLogicYyXZCLK10EIS-WuhanUniversityMooremachineFFCombinationalMealymachineboththeinputandthecurrentstateisusedtodeterminetheoutput

Z=f(x,y) Y=f(x,y)XyCombinationalCircuitsFFCLKZY11EIS-WuhanUniversityMealymachineXyCombinationalCSixDesign-StepProcessesforFSM1.Understandthestatementofthespecification2.ObtainanabstractspecificationoftheFSM3.Performastateminimization4.Performstateassignment5.ChooseFFtypestoimplementFSMstateregister6.ImplementtheFSM12EIS-WuhanUniversitySixDesign-StepProcessesforStaticvsDynamicStorageStaticstoragepreservestateaslongasthepowerisonhavepositivefeedback(regeneration)withaninternalconnectionbetweentheoutputandtheinputusefulwhenupdatesareinfrequent(clockgating)Dynamicstoragestorestateonparasiticcapacitorsonlyholdstateforshortperiodsoftime(milliseconds)requireperiodicrefreshusuallysimpler,sohigherspeedandlowerpower13EIS-WuhanUniversityStaticvsDynamicStorageStatiLatchesvsFlipflopsLatcheslevelsensitivecircuitthatpassesinputstoQwhentheclockishigh(orlow)-transparentmodeinputsampledonthefallingedgeoftheclockisheldstablewhenclockislow(orhigh)-holdmodeFlipflops(edge-triggered)一般指觸發(fā)器edgesensitivecircuitsthatsampletheinputsonaclocktransitionpositiveedge-triggered:01

negativeedge-triggered:10builtusinglatches(e.g.,master-slaveflipflops)14EIS-WuhanUniversityLatchesvsFlipflopsLatches14ELatchversusRegisterLatch storesdatawhenclockislowRegister storesdatawhenclockrisesDClkQClkDQDClkQClkDQTransparent15EIS-WuhanUniversityLatchversusRegisterLatchRegi7-2鎖存器（Latches）類型Latch-BasedDesign時間定義與約束改變輸出多路開關型鎖存器16EIS-WuhanUniversity7-2鎖存器（Latches）類型16EIS-Wuhan類型17EIS-WuhanUniversity類型17EIS-WuhanUniversityLatch-BasedDesign—forsequentialNlatchistransparent

whenf=0Platchistransparent

whenf=1PLatchLogicLogicNLatchf18EIS-WuhanUniversityLatch-BasedDesign—forsequen時間定義（TimingDefinitions）tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQtsuSetup建起時間——時鐘翻轉之前數據必須有效的時間；thold維持時間——時鐘觸發(fā)之后數據仍然有效的時間；tc-q傳播延遲時間——CLK到Q19EIS-WuhanUniversity時間定義（TimingDefinitions）tCLKtCharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q20EIS-WuhanUniversityCharacterizingTimingRegisterL約束（SystemTimingConstraints）約束1： 最小時鐘周期：Ttc-q+tplogic+tsu一個CLK周期必須容納任何一級電路的最大延遲時間tplogicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT(clockperiod)21EIS-WuhanUniversity約束（SystemTimingConstraints）約約束2寄存器維持時間：tholdtcd-register+tcd-logic

tholdtcd-register寄存器最小傳播延遲cd---ContaminationDelaytcd-logic邏輯電路最小傳播延遲保證時序元件的輸入數據在CLK邊沿之后能夠維持足夠的時間，不會因為新進入的數據流而過早改變。tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ22EIS-WuhanUniversity約束2寄存器維持時間：tholdtCLKtDtc-qtholPositiveFeedback:Bi-Stabilitycascadedinverters23EIS-WuhanUniversityPositiveFeedback:Bi-StabilitVTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1Ifthegaininthetransientregionislargerthan1,onlyAandBarestableoperationpoints.Cisameta-stableoperationpoint.24EIS-WuhanUniversityVTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2VMeta-StabilityGainshouldbelargerthan1inthetransitionregion====25EIS-WuhanUniversityMeta-StabilityGainshouldbelBistableCircuits（flip-flops）改變輸出cuttingthefeedbackloop(muxbasedlatch)overpoweringthefeedbackloop(asusedinSRAMs)Vi1Vi226EIS-WuhanUniversityBistableCircuits（flip-flopsWritingintoaStaticLatchDCLKCLKDConvertingintoaMUXForcingthestate(canimplementasNMOS-only)Usetheclockasadecouplingsignal,thatdistinguishesbetweenthetransparentandopaquestates弱輸出27EIS-WuhanUniversityWritingintoaStaticLatchDCL多路開關型鎖存器

（Mux-BasedLatches）Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQ28EIS-WuhanUniversity多路開關型鎖存器

（Mux-BasedLatches）NeMux-BasedLatch傳輸階段（透明）維持階段29EIS-WuhanUniversityMux-BasedLatch傳輸階段（透明）29EISMux-BasedLatchNMOSonlyNon-overlappingclocks30EIS-WuhanUniversityMux-BasedLatchNMOSonlyNon-ov7-3寄存器主從式邊沿觸發(fā)寄存器降低時鐘負載非理想時鐘—時鐘重疊靜態(tài)RS觸發(fā)器—強信號寫數據31EIS-WuhanUniversity7-3寄存器主從式邊沿觸發(fā)寄存器31EIS-WuhanUMaster-Slave(Edge-Triggered)RegisterTwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpair

32EIS-WuhanUniversityMaster-Slave(Edge-Triggered)Master-SlaveRegisterMultiplexer-basedlatchpair33EIS-WuhanUniversityMaster-SlaveRegisterMultiplex多路開關型寄存器的時序特性寄存器時序參數SetupTime,HoldTime,PropagationDelayassume：反相器傳播延遲:tinv傳輸門傳播延遲:tTGClkinverter:

tclk-int=0tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ34EIS-WuhanUniversity多路開關型寄存器的時序特性寄存器時序參數tCLKtDtc-qTimingofRegisterSetupTimeData在Clk上升沿前必須有效的時間—QM穩(wěn)定時間傳播路徑：Inv1—

TG1—

Inv3—

TG2Tsetup=

3tinv+tTGPropagationDelayTc-q—

QM傳播到輸出的時間傳播路徑：TG3—

Inv6Tc-q=tTG+tinvHoldTimeClk上升沿之后輸入必須保持穩(wěn)定的時間TG1關斷Thold=

035EIS-WuhanUniversityTimingofRegisterSetupTime35CharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q36EIS-WuhanUniversityCharacterizingTimingRegisterL降低時鐘負載（ReducedClockLoad）設計復雜性提高（I2、I4強度）反向傳導(可能影響前級存儲結果）37EIS-WuhanUniversity降低時鐘負載（ReducedClockLoad）設時鐘偏差（ClockSkew）

——時鐘重疊（ClockOverlap）CLKCLKAB(a)Schematicdiagram(b)OverlappingclockpairsXDQCLKCLKCLKCLK時鐘變?yōu)樯仙貢r，從級應為維持狀態(tài)；由于時鐘重疊，D與Q之間形成直接通路；產生競爭：A同時被D、B驅動；減弱B的強度；輸出不確定狀態(tài)。clkskew產生原因？38EIS-WuhanUniversity時鐘偏差（ClockSkew）

——時鐘重疊（Clo偽靜態(tài)兩相D寄存器——不重疊時鐘兩相時鐘；時間間隔足夠長；偽靜態(tài)—保持時間長，漏電影響；不會產生重疊。CLK1CLK1ABXDQCLK2CLK2CLK2CLK139EIS-WuhanUniversity偽靜態(tài)兩相D寄存器——不重疊時鐘兩相時鐘；CLK1CLK1A靜態(tài)RS觸發(fā)器—強信號寫數據（OverpoweringtheFeedbackLoop

─Cross-CoupledPairs）NOR-basedset-reset40EIS-WuhanUniversity靜態(tài)RS觸發(fā)器—強信號寫數據（OverpoweringthCross-CoupledNANDCross-coupledNANDsAddedclockThisisnotusedindatapathsanymore,

butisabasicbuildingmemorycell41EIS-WuhanUniversityCross-CoupledNANDCross-couple7-4動態(tài)鎖存器/寄存器DCLKCLKQDynamic(charge-based)StaticStorageMechanisms42EIS-WuhanUniversity7-4動態(tài)鎖存器/寄存器DCLKCLKQDynamic(StaticvsDynamicStorageStaticstoragepreservestateaslongasthepowerisonhavepositivefeedback(regeneration)withaninternalconnectionbetweentheoutputandtheinputusefulwhenupdatesareinfrequent(clockgating)Dynamicstoragestorestateonparasiticcapacitorsonlyholdstateforshortperiodsoftime(milliseconds)requireperiodicrefreshusuallysimpler,sohigherspeedandlowerpower43EIS-WuhanUniversityStaticvsDynamicStorageStati動態(tài)邊沿觸發(fā)寄存器CLKCLKQDCLKCLKSetupTime傳播路徑：TG1Tsetup=tTG

PropagationDelay傳播路徑：Inv1—TG2—Inv3Tc-q=tTG+2tinv

HoldTimeThold=044EIS-WuhanUniversity動態(tài)邊沿觸發(fā)寄存器CLKCLKQDCLKCLKSetupTMakingaDynamicLatchPseudo-Static針對噪聲干擾和漏電影響；偽靜態(tài)—弱反饋；增加延時，提高抗干擾能力。45EIS-WuhanUniversityMakingaDynamicLatchPseudo-7-5時鐘控制寄存器C2MOS

——時鐘偏差不敏感方法“Keepers”canbeaddedtomakecircuitpseudo-static主從式；正沿觸發(fā)；CLK=0時X=D求值，從級維持（高阻態(tài)）；CLK=1時相反。只要時鐘邊沿的上升和下降時間足夠小，對時鐘重疊不敏感。46EIS-WuhanUniversity7-5時鐘控制寄存器C2MOS

——時鐘偏差不敏感方InsensitivetoClock-OverlapM1DQM4M200VDDXM5M8M6VDD(a)(0-0)overlapM3M1DQM21VDDXM71M5M6VDD(b)(1-1)overlap47EIS-WuhanUniversityInsensitivetoClock-OverlapM17-6真單相時鐘寄存器

（TrueSinglePhaseClockRegister）Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)無時鐘重疊；減少時鐘負載。48EIS-WuhanUniversity7-6真單相時鐘寄存器

（TrueSinglePhasIncludingLogicinTSPCANDlatchExample:logicinsidethelatch可嵌入邏輯功能。49EIS-WuhanUniversityIncludingLogicinTSPCANDlatTSPCRegisterCLK=0X=反相的D，Y預充電，Q維持；CLK=1X高阻，Y=X的反相，Q=Y。50EIS-WuhanUniversityTSPCRegisterCLK=050EIS-WuhanPulse-TriggeredLatchesMaster-SlaveLatchesDClkQDClkQClkDataDClkQClkDataPulse-TriggeredLatchL1L2LWaystodesignanedge-triggeredsequentialcell:51EIS-WuhanUniversityPulse-TriggeredLatchesMaster-PulsedLatches52EIS-WuhanUniversityPulsedLatches52EIS-WuhanUniv7-7流水線（Pipelining）ReferencePipelined寄存器傳播延遲寄存器建立時間組合邏輯最壞延遲53EIS-WuhanUniversity7-7流水線（Pipelining）ReferencePiLatch-BasedPipeline54EIS-WuhanUniversityLatch-BasedPipeline54EIS-Wuha7-8非雙穩(wěn)態(tài)時序電路

Non-BistableSequentialCircuitsSchmittTriggerMonostableTriggerAstableMultivibratorsVCO55EIS-WuhanUniversity7-8非雙穩(wěn)態(tài)時序電路

Non-BistableSequSchmittTrigger對于緩慢的輸入，快速翻轉的輸出響應；VTC正向、負向變化的輸入信號有不同的閾值；滯回電壓為其差；用于提高抗干擾能力，減少振鈴現象。InOutVinVoutVOHVOLVM–VM+56EIS-WuhanUniversitySchmittTrigger對于緩慢的輸入，快速翻轉的輸出NoiseSuppressionusingSchmittTrigger57EIS-WuhanUniversityNoiseSuppressionusingSchmitCMOSSchmittTriggerMovesswitchingthresholdofthefirstinverter反相器等效晶體管比：β1/（β

2+β

4）開關閾值提高反相器等效晶體管比：（β

1+β

3）/β2開關閾值降低58EIS-WuhanUniversityCMOSSchmittTriggerMovesswitMultivibratorCircuitsBistableMultivibratorMonostableMultivibratorAstableMultivibratorflip-flop,SchmittTriggerone-shotoscillatorSRT59EIS-WuhanUniversityMultivibratorCircuitsBistableTransition-TriggeredMonostableDELAYtdInOuttd60EIS-WuhanUniversityTransition-TriggeredMonostablMonostableTrigger(RC-based)VDDInOutABCRInBOuttVMt2t1(a)Triggercircuit.(b)Waveforms.61EIS-WuhanUniversityMonostableTrigger(RC-based)VAstableMultivibrators(Oscillators)RingOscillator奇數個反相器T=2N*tpsimulatedresponseof5-stageoscillator012N-162EIS-WuhanUniversityAstableMultivibrators(OscillRelaxationOscillator—弛緩Out2CROut1IntI1I2T=2(log3)RCanoscillatorinwhichacapacitorischargedgraduallyandthendischargedrapidly63EIS-WuhanUniversityRelaxationOscillator—弛緩Out2CRVoltageControllerOscillator(VCO)InVDDM3M1M2M4M5VDDM6VcontrCurrentstarvedinverterIrefIrefSchmittTriggerrestoressignalslopesVcontr

(V)0.0246tpHL

(nsec)propagationdelayasafunctionofcontrolvoltage64EIS-WuhanUniversityVoltageControllerOscillatorDifferentialDelayElementandVCOin2twostageVCOv1v2v3v4VctrlVo2Vo1in1delaycell

simulatedwaveformsof2-stageVCO0.50.00.51.01.52.02.53.020.51.5V1V2V3V4time(ns)2.53.565EIS-WuhanUniversityDifferentialDelayElementand7-9時序問題

——數據路徑（Datapath）設計基本問題時序邏輯靜態(tài)與動態(tài)存儲同步/異步時鐘偏差與抖動來源時鐘偏差時鐘抖動時鐘分布網絡時鐘技術設計準則66EIS-WuhanUniversity7-9時序問題

——數據路徑（Datapath）設計基本Review:SequentialDefinitions寄存器兩個電平觸發(fā)latches

ofoppositetypemaster-slavechangesstateonaclockedge67EIS-WuhanUniversityReview:SequentialDefinitionStaticstorage——Dynamicstorage

Staticstorage雙穩(wěn)態(tài)——bistable反饋——withfeedbacktostoreitsstate保持——preservesstateaslongasthepowerison更新數據cuttingthefeedbackpath(muxbased);overpoweringthefeedbackpath(SRAMbased)Dynamicstorage寄生電容——parasiticcapacitorsonlyaperiodoftime(milliseconds)刷新——periodicrefreshfewertransistorshigherspeedlowerpower偽靜態(tài)pseudostaticduetonoise68EIS-WuhanUniversityStaticstorage——DynamicstoragTimingClassifications同步系統(tǒng)（Synchronoussystems）所有存儲單元同步更新使用同步clocksignalstrictconstraintsontheclocksignalgenerationanddistributiontominimize時鐘偏差Clockskew(spatialvariationsinclockedges)時鐘抖動Clockjitter(temporalvariationsinclockedges)異步系統(tǒng)（Asynchronoussystems）自定時Self-timedsystems不需要全局時鐘globallydistributedclock握手協(xié)議控制handshaking69EIS-WuhanUniversityTimingClassifications同步系統(tǒng)（SynSynchronousTimingBasicsUnderidealconditions(i.e.,whentclk1=tclk2)Ttc-q+tplogic+tsuthold

≤tcdlogic+tcdregUnderrealconditionsskewisconstantfromcycletocycleskewcanbepositiveornegativejittercausesTtochangeonacycle-by-cyclebasisDQR1CombinationallogicDQR2clkIntclk1tclk2tc-q,tsu,thold,tcdregtplogic,tcdlogic70EIS-WuhanUniversitySynchronousTimingBasicsUnderSourcesofClockSkewandJitterinClockNetworkPLL1243567clockgenerationclockdriverspowersupplyinterconnectcapacitiveloadcapacitivecouplingtemperatureSkewmanufacturingdevicevariationsinclockdriversinterconnectvariationsenvironmentalvariations(powersupplyandtemperature)Jitterclockgenerationcapacitiveloadingandcouplingenvironmentalvariations(powersupplyandtemperature)71EIS-WuhanUniversitySourcesofClockSkewandJittPositiveClockSkew>0:Improvesperformance,butmakestholdhardertomeet.Iftholdisnotmet(raceconditions).T+

tc-q+tplogic+tsusoTtc-q+tplogic+tsu-thold+≤tcdlogic+tcdregsothold≤tcdlogic+tcdreg-DQR1CombinationallogicDQR2clkIntclk1tclk2delayTT+>0+thold123472EIS-WuhanUniversityPositiveClockSkew>0:ImprNegativeClockSkewClockanddataflowinoppositedirectionsT+

tc-q+tplogic+tsusoTtc-q+tplogic+tsu-thold+≤tcdlogic+tcdregsothold≤tcdlogic+tcdreg-DQR1CombinationallogicDQR2clkIntclk1tclk2delayTT+<01234<0:Degradesperformance,butthold

iseasiertomeet73EIS-WuhanUniversityNegativeClockSkewClockanddClockJitterJittercausesTtovaryonacycle-by-cyclebasisR1CombinationallogicclkIntclkT-tjitter+tjitterT-2tjitter

tc-q+tplogic+tsuTtc-q+tplogic+tsu+2tjitterJitterdirectlyreducestheperformanceofasequentialcircuit74EIS-WuhanUniversityClockJitterJittercausesTtoCombinedImpactofSkewandJitterConstraintsontheminimumclockperiod(>0)DQR1CombinationallogicDQR2Intclk1tclk2TT+>01612-tjitterTtc-q+tplogic+tsu-+2tjitter

thold≤tcdlogic+tcdreg––2tjitter75EIS-WuhanUniversityCombinedImpactofSkewandJiClockDistributionNetworksClockskewandjitter影響性能消耗能量dynamicpower應支持時鐘控制clockgating(shuttingdownunits)時鐘分布技術ClockdistributionBalancedpaths(H-treenetwork,matchedRCtrees)Intheidealcase,caneliminateskewCouldtakemultiplecyclesfortheclocksignaltopropagatetotheleavesofthetreeClockgridsTypicallyusedinthefinalstageoftheclockdistributionnetworkMinimizesabsolutedelay(notrelativedelay)76EIS-WuhanUniversityClockDistributionNetworksCloH-TreeClockNetworkClockClockIdleconditionGatedclockIfthepathsareperfectlybalanced,clockskewiszero;Caninsertclockgatingatmultiplelevelsinclocktree;Canshutoffentiresubtreeifallgatingconditionsaresatisfied.77EIS-WuhanUniversityH-TreeClockNetworkClockClockDECAlpha21164(EV5)300MHzclock(9.3milliontransistorsona16.5x18.1mmdiein0.5micronCMOStechnology)singlephaseclock3.75nFtotalclockloadExtensiveuseofdynamiclogic20W(outof50)inclockdistributionnetworkTwolevelclockdistributionSingle6stagedriveratthecenterofthechipSecondarybuffersdrivetheleftandrightsidesoftheclockgridinm3andm4Totalequivalentdriversize(寬度)of58cm!!78EIS-WuhanUniversityDECAlpha21164(EV5)300MHzc79EIS-WuhanUniversity79EIS-WuhanUniversityClockSkewinAlphaProcessorAbsoluteskewsmallerthan90psThecriticalinstructionandexecutionunitsallseetheclockwithin65ps80EIS-WuhanUniversityClockSkewinAlphaProcessorADealingwithClockSkewandJitterTominimizeskew,balanceclockpathsusingH-treeormatched-treeclockdistributionstructures.Ifpossible,routedataandclockinoppositedirections;eliminatesracesatthecostofperformance.Theuseofgatedclockstohelpwithdynamicpowerconsumptionmakejitterworse.Shieldclockwires(routepowerlines–VDDorGND–nexttoclocklines)tominimize/eliminatecouplingwithneighboringsignalnets.改善層間絕緣介質一致性Usedummyfillstoreduceskewbyreducingvariationsininterconnectcapacitancesduetointerlayerdielectricthicknessvariations.Powersupplynoisefundamentallylimitstheperformanceofclocknetworks.81EIS-WuhanUniversityDealingwithClockSkewandJi集成電路設計第七章

時序邏輯電路設計 DesigningSequentialLogicCircuits82EIS-WuhanUniversity集成電路設計第七章時序邏輯電路設計1EIS-WuhanU綱要基本概念組合邏輯與時序邏輯電路有限狀態(tài)機（FSM）LatchversusRegister鎖存器寄存器動態(tài)鎖存器/寄存器時鐘控制寄存器C2MOS流水線非雙穩(wěn)態(tài)時序電路時序問題83EIS-WuhanUniversity綱要基本概念2EIS-WuhanUniversityLogicCircuits:

(1)CombinationalLogic (2)SequentialLogic7-1基本概念

84EIS-WuhanUniversityLogicCircuits:7-1基本概念

3EISItismemoryless;i.e.,withoutstates.CombinationalCircuitsInputOutputCombinationalLogic

85EIS-WuhanUniversityItismemoryless;CombinationalCombinationalLogicDesignProcedures1.Constructthetruthtable2.Basedonthetruthtable (a)Simplifythelogicandimplementby (i)randomlogicgates (ii)multiplexers (iii)PLA’sorPAL’s (b)ImplementthecircuitbyROM’s86EIS-WuhanUniversityCombinationalLogicDesignPro——SequentialLogicSequentialLogicAsynchronousCircuitsSynchronousCircuits87EIS-WuhanUniversity——SequentialLogicSequentialLDuetothetimedelayproblems(races,hazards,…etc.)peoplerarelydesignsequentialcircuitsinasynchronousapproach.Synchronouscircuitsneedasystemclocktostrobethewholesystem.Itiseasiertocontroltheinputsandstates.Thespeedmaybeslowerinthesynchronouscircuits.88EIS-WuhanUniversityDuetothetimedelayproblemsCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsDQFiniteStateMachine（FSM)89EIS-WuhanUniversityCombinationalclockOutputsStateExternalinputsandstatesastheinputsOutputs，andNextstateClock，edgesensitive（positiveornegative）MealyversusMoorestatemachines90EIS-WuhanUniversityExternalinputsandstatesasMooremachineFF—Flip-Flop

outputdependsonlyonthecurrentstateZ=f(y)potentialimplementationadvantagesinspeedandsize；initialstateFFCombinationalLogicYyXZCLK91EIS-WuhanUniversityMooremachineFFCombinationalMealymachineboththeinputandthecurrentstateisusedtodeterminetheoutput

Z=f(x,y) Y=f(x,y)XyCombinationalCircuitsFFCLKZY92EIS-WuhanUniversityMealymachineXyCombinationalCSixDesign-StepProcessesforFSM1.Understandthestatementofthespecification2.ObtainanabstractspecificationoftheFSM3.Performastateminimization4.Performstateassignment5.ChooseFFtypestoimplementFSMstateregister6.ImplementtheFSM93EIS-WuhanUniversitySixDesign-StepProcessesforStaticvsDynamicStorageStaticstoragepreservestateaslongasthepowerisonhavepositivefeedback(regeneration)withaninternalconnectionbetweentheoutputandtheinputusefulwhenupdatesareinfrequent(clockgating)Dynamicstoragestorestateonparasiticcapacitorsonlyholdstateforshortperiodsoftime(milliseconds)requireperiodicrefreshusuallysimpler,sohigherspeedandlowerpower94EIS-WuhanUniversityStaticvsDynamicStorageStatiLatchesvsFlipflopsLatcheslevelsensitivecircuitthatpassesinputstoQwhentheclockishigh(orlow)-transparentmodeinputsampledonthefallingedgeoftheclockisheldstablewhenclockislow(orhigh)-holdmodeFlipflops(edge-triggered)一般指觸發(fā)器edgesensitivecircuitsthatsampletheinputsonaclocktransitionpositiveedge-triggered:01

negativeedge-triggered:10builtusinglatches(e.g.,master-slaveflipflops)95EIS-WuhanUniversityLatchesvsFlipflopsLatches14ELatchversusRegisterLatch storesdatawhenclockislowRegister storesdatawhenclockrisesDClkQClkDQDClkQClkDQTransparent96EIS-WuhanUniversityLatchversusRegisterLatchRegi7-2鎖存器（Latches）類型Latch-BasedDesign時間定義與約束改變輸出多路開關型鎖存器97EIS-WuhanUniversity7-2鎖存器（Latches）類型16EIS-Wuhan類型98EIS-WuhanUniversity類型17EIS-WuhanUniversityLatch-BasedDesign—forsequentialNlatchistransparent

whenf=0Platchistransparent

whenf=1PLatchLogicLogicNLatchf99EIS-WuhanUniversityLatch-BasedDesign—forsequen時間定義（TimingDefinitions）tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQtsuSetup建起時間——時鐘翻轉之前數據必須有效的時間；thold維持時間——時鐘觸發(fā)之后數據仍然有效的時間；tc-q傳播延遲時間——CLK到Q100EIS-WuhanUniversity時間定義（TimingDefinitions）tCLKtCharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q101EIS-WuhanUniversityCharacterizingTimingRegisterL約束（SystemTimingConstraints）約束1： 最小時鐘周期：Ttc-q+tplogic+tsu一個CLK周期必須容納任何一級電路的最大延遲時間tplogicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT(clockperiod)102EIS-WuhanUniversity約束（SystemTimingConstraints）約約束2寄存器維持時間：tholdtcd-register+tcd-logic

tholdtcd-register寄存器最小傳播延遲cd---ContaminationDelaytcd-logic邏輯電路最小傳播延遲保證時序元件的輸入數據在CLK邊沿之后能夠維持足夠的時間，不會因為新進入的數據流而過早改變。tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ103EIS-WuhanUniversity約束2寄存器維持時間：tholdtCLKtDtc-qtholPositiveFeedback:Bi-Stabilitycascadedinverters104EIS-WuhanUniversityPositiveFeedback:Bi-StabilitVTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1Ifthegaininthetransientregionislargerthan1,onlyAandBarestableoperationpoints.Cisameta-stableoperationpoint.105EIS-WuhanUniversityVTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2VMeta-StabilityGainshouldbelargerthan1inthetransitionregion====106EIS-WuhanUniversityMeta-StabilityGainshouldbelBistableCircuits（flip-flops）改變輸出cuttingthefeedbackloop(muxbasedlatch)overpoweringthefeedbackloop(asusedinSRAMs)Vi1Vi2107EIS-WuhanUniversityBistableCircuits（flip-flopsWritingintoaStaticLatchDCLKCLKDConvertingintoaMUXForcingthestate(canimplementasNMOS-only)Usetheclockasadecouplingsignal,thatdistinguishesbetweenthetransparentandopaquestates弱輸出108EIS-WuhanUniversityWritingintoaStaticLatchDCL多路開關型鎖存器

（Mux-BasedLatches）Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQ109EIS-WuhanUniversity多路開關型鎖存器

（Mux-BasedLatches）NeMux-BasedLatch傳輸階段（透明）維持階段110EIS-WuhanUniversityMux-BasedLatch傳輸階段（透明）29EISMux-BasedLatchNMOSonlyNon-overlappingclocks111EIS-WuhanUniversityMux-BasedLatchNMOSonlyNon-ov7-3寄存器主從式邊沿觸發(fā)寄存器降低時鐘負載非理想時鐘—時鐘重疊靜態(tài)RS觸發(fā)器—強信號寫數據112EIS-WuhanUniversity7-3寄存器主從式邊沿觸發(fā)寄存器31EIS-WuhanUMaster-Slave(Edge-Triggered)RegisterTwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpair

113EIS-WuhanUniversityMaster-Slave(Edge-Triggered)Master-SlaveRegisterMultiplexer-basedlatchpair114EIS-WuhanUniversityMaster-SlaveRegisterMultiplex多路開關型寄存器的時序特性寄存器時序參數SetupTime,HoldTime,PropagationDelayassume：反相器傳播延遲:tinv傳輸門傳播延遲:tTGClkinverter:

tclk-int=0tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ115EIS-WuhanUniversity多路開關型寄存器的時序特性寄存器時序參數tCLKtDtc-qTimingofRegisterSetupTimeData在Clk上升沿前必須有效的時間—QM穩(wěn)定時間傳播路徑：Inv1—

TG1—

Inv3—

TG2Tsetup=

3tinv+tTGPropagationDelayTc-q—

QM傳播到輸出的時間傳播路徑：TG3—

Inv6Tc-q=tTG+tinvHoldTimeClk上升沿之后輸入必須保持穩(wěn)定的時間TG1關斷Thold=

0116EIS-WuhanUniversityTimingofRegisterSetupTime35CharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q117EIS-WuhanUniversityCharacterizingTimingRegisterL降低時鐘負載（ReducedClockLoad）設計復雜性提高（I2、I4強度）反向傳導(可能影響前級存儲結果）118EIS-WuhanUniversity降低時鐘負載（ReducedClockLoad）設時鐘偏差（ClockSkew）

——時鐘重疊（ClockOverlap）CLKCLKAB(a)Schematicdiagram(b)OverlappingclockpairsXDQCLKCLKCLKCLK時鐘變?yōu)樯仙貢r，從級應為維持狀態(tài)；由于時鐘重疊，D與Q之間形成直接通路；產生競爭：A同時被D、B驅動；減弱B的強度；輸出不確定狀態(tài)。clkskew產生原因？119EIS-WuhanUniversity時鐘偏差（ClockSkew）

——時鐘重疊（Clo偽靜態(tài)兩相D寄存器——不重疊時鐘兩相時鐘；時間間隔足夠長；偽靜態(tài)—保持時間長，漏電影響；不會產生重疊。CLK1CLK1ABXDQCLK2CLK2CLK2CLK1120EIS-WuhanUniversity偽靜態(tài)兩相D寄存器——不重疊時鐘兩相時鐘；CLK1CLK1A靜態(tài)RS觸發(fā)器—強信號寫數據（OverpoweringtheFeedbackLoop

─Cross-CoupledPairs）NOR-basedset-reset121EIS-WuhanUniversity靜態(tài)RS觸發(fā)器—強信號寫數據（OverpoweringthC