基于FPGA的四位加法器設計

基于FPGA的四位加法器設計4位加法器設計。取開發(fā)板上的4位按鍵作為4位被加數(shù)，取4位撥碼開關(guān)作為4位被加數(shù)，其中8個led燈取5位作為輸出結(jié)果，led0-led3作為相加的結(jié)果，led4作為進位（LED亮表示低電平0，LED滅表示高電平1，）數(shù)碼管以十進制數(shù)顯示被加數(shù)，加數(shù)和相加的結(jié)果。包括vhdl文件、和vwf文件。利用兩組按鍵作為兩個加數(shù)輸入，用數(shù)碼管做加數(shù)顯示和結(jié)果顯示，開發(fā)板上只有4個數(shù)碼管，但加數(shù)都是兩位的，所以只能做輪流顯示，用“=”鍵做顯示切換。程序如下：libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;useieee.std_logic_arith.all;entityadder_4isport( clk:instd_logic;--時鐘輸入，應該輸入分頻后的clk enter:instd_logic;--顯示切換，可以理解位“=”鍵 clear:instd_logic;--清除鍵，預留接口可擴展 key_num1:instd_logic_vector(3downto0);--加數(shù)1 key_num2:instd_logic_vector(3downto0);--加數(shù)2 duan:outstd_logic_vector(6downto0);--輸出結(jié)果 wei:outstd_logic_vector(3downto0); led5:outstd_logic_vector(4downto0)--led結(jié)果顯示 );endentity;architecturefunofadder_4issignalnum1,num2:std_logic_vector(3downto0);--中間信號定義signaladd_num1:integerrange15downto0;signaladd_num2:integerrange15downto0;signaladd_sum:integerrange30downto0;signalten_data:integerrange9downto0;signaladd_num1ge,add_num1shi,add_num2ge,add_num2shi,sumge,sumshi:integerrange9downto0;signalwei_data:integerrange0to3;begin duan<="1000000"whenten_data=0else--顯示部分，數(shù)碼管共陽 "1111001"whenten_data=1else "0100100"whenten_data=2else "0110000"whenten_data=3else "0111001"whenten_data=4else "0010010"whenten_data=5else "0000010"whenten_data=6else "1111000"whenten_data=7else "0000000"whenten_data=8else "0010000"; process(clk,clear,enter,key_num1,key_num2,num1,num2,add_num1ge,add_num1shi,add_num2ge,add_num2shi,sumge,sumshi) begin ifclear='0'then add_num1<=0; add_num2<=0; add_sum<=0; else --ifkey_num1/="1111"orkey_num2/="1111"then num1<=notkey_num1; num2<=notkey_num2;--加數(shù)處理，二進制轉(zhuǎn)十進制。 add_num1<=conv_integer(num1(0))*1+conv_integer(num1(1))*2+conv_integer(num1(2))*4+conv_integer(num1(3))*8;add_num1ge<=(add_num1rem10);--個位，十位分離 add_num1shi<=((add_num1-add_num1ge)/10); add_num2<=conv_integer(num2(0))*1+conv_integer(num2(1))*2+conv_integer(num2(2))*4+conv_integer(num2(3))*8; add_num2ge<=(add_num2rem10); add_num2shi<=((add_num2-add_num2ge)/10); add_sum<=add_num1+add_num2; sumge<=(add_sumrem10); sumshi<=((add_sum-sumge)/10); led5<=('0'&num1)+('0'&num2); --endif; endif; ifclk'eventandclk='1'then wei_data<=wei_data+1; endif; ifenter='1'then casewei_datais when0=>ten_data<=add_num1ge;wei<="0001"; when1=>ten_data<=add_num1shi;wei<="0010"; when2=>ten_data<=add_num2ge;wei<="0100"; whenothers=>ten_data<=add_num2shi;wei<="1000"; endcase; else casewei_datais when0=>ten_data<=sumge;wei<="0001"; when1=>ten_data<=sumshi;wei<="0010"; when2=>ten_data<=0;wei<="0100"; whenothers=>ten_data<=0;wei<="1000"; endcase; endif; endprocess;endarchitecture;此程序為，在調(diào)試兩周之后的沒有問題的，學習班用的CYCLONE_IV_E:以下為50MHZ分頻程序：libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;useieee.std_logic_arith.all;entitydefrequanceisport( in_5khz:instd_logic; out_1hz:outstd_logic );endentitydefrequance;architecturefunofdefrequanceissignalnum:integerrange0to50000;beginprocess(in_5khz,num)beginifin_5khz'eventandin_5khz='1'then num<=num+1; ifnum<25000then-- num<=0; out_1hz<='1'; elsifnum>25000andnum<50000then out_1hz<='0'; endif;endif;endpr