簡化RISCCPU相關(guān)設(shè)計方案

簡化RISCCPU相關(guān)設(shè)計方案17.1什么是CPUCPU：中央處理單元，是計算機(jī)的核心部件計算機(jī)進(jìn)行信息處理分兩個步驟：將數(shù)據(jù)和程序（指令序列）輸入到計算機(jī)的存儲器中從第一條指令的地址起開始執(zhí)行程序，得到所需結(jié)果，結(jié)束運(yùn)行。CPU的作用：協(xié)調(diào)并控制計算機(jī)的各部件，使之有條不紊的執(zhí)行程序CPU的基本功能：取指令-地址與控制信號分析指令-即指令譯碼，操作和操作控制信號執(zhí)行指令-操作控制信號作用于各部件CPU的基本功能概括：能對指令進(jìn)行譯碼并執(zhí)行規(guī)定的動作可以進(jìn)行算術(shù)和邏輯運(yùn)算能與存儲器和外設(shè)交換數(shù)據(jù)提供系統(tǒng)所需的控制CPU的內(nèi)部結(jié)構(gòu)：算術(shù)邏輯運(yùn)算單元（ALU）累加器程序計數(shù)器指令寄存器和譯碼器時序和控制部件RISC即精簡指令集計算機(jī)：ReducedInstructionSetComputer時序控制信號由硬件而不是微程序控制cpuABDB地址譯碼器ROMRAMclockresetMICROCOMPUTERSYSTEMreadwriteD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0高8位低8位地址碼指令碼指令指令數(shù)目：8條地址空間：213=8K助記符操作碼功能HLT3'b000

暫停SKZ3‘b001累加器為零轉(zhuǎn)移ADD3’b010加ANDD3‘b011與XORR3‘b100或LDA3‘b101取數(shù)STO3‘b110存數(shù)JMP3‘b111轉(zhuǎn)移指令集CPU的基本功能：取指令-地址與控制信號分析指令-即指令譯碼，操作和操作控制信號執(zhí)行指令-操作控制信號作用于各部件CPU的基本功能概括：能對指令進(jìn)行譯碼并執(zhí)行規(guī)定的動作可以進(jìn)行算術(shù)和邏輯運(yùn)算能與存儲器和外設(shè)交換數(shù)據(jù)提供系統(tǒng)所需的控制CPU的內(nèi)部結(jié)構(gòu)：算術(shù)邏輯運(yùn)算單元（ALU）累加器程序計數(shù)器指令寄存器和譯碼器時序和控制部件alu_ena累加器A指令寄存器IR算邏單元ALU數(shù)據(jù)控制地址選擇程序計數(shù)器PC控制狀態(tài)機(jī)時鐘信號ABDBhaltrdwrclkrstload_accinc_pcload_pcload_irfetchdatactl_enaCPU的結(jié)構(gòu)功能圖累加器A指令寄存器IR算邏單元ALU數(shù)據(jù)控制地址選擇程序計數(shù)器PC控制狀態(tài)機(jī)時鐘信號ABDBhaltrdwrclkrstload_accfetchinc_pcload_pcload_iralu_enadatactl_enahaltload_irrdinc_pcalu_enafetchclk01234567halt指令累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機(jī)時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567LDA1000B000EE0110001001RAMEEload_accaddress000000011000B00000000001ROM0000020002累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機(jī)時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567ADD10015001EE1110001001RAM11load_accaddress000200031001500100020003ROM00040004累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機(jī)時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567STO1001D001EE0110001001RAMFFwraddress000400051001D00100040005ROM0006000617.3.1時鐘發(fā)生器fetch是控制信號，clk的8分頻信號alu_ena用于控制算術(shù)邏輯運(yùn)算單元clk是時鐘信號reset是復(fù)位信號狀態(tài)轉(zhuǎn)移圖Idle

S117.3.1時鐘發(fā)生器

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idle//-------clk_gen.v--------`timescale1ns/1nsmoduleclk_gen(clk,reset,fetch,alu_ena);

inputclk,reset;outputfetch,alu_ena;wireclk,reset;regfetch,alu_ena;reg[7:0]state;parameterS1=8'b00000001, S2=8'b00000010,S3=8'b00000100,S4=8'b00001000,S5=8'b00010000,S6=8'b00100000,S7=8'b01000000,S8=8'b10000000,idle=8'b00000000;17.3.1時鐘發(fā)生器always@(posedgeclk)if(reset)beginfetch<=0;alu_ena<=0;state<=idle;endelsebegin case(state) … … … …default:state<=idle; endcase endcase(state)S1:begin fetch<=1; state<=S2;endS2:state<=S3; S3:state<=S4;S4:state<=S5;S5:beginstate<=S6; fetch=0;end S6:begin state<=S7; alu_ena<=1;end S7:beginalu_ena<=0;state<=S8;endS8:state<=S1;idle:state<=S1;default:state<=idle;endcase17.3.2指令寄存器resetclkload_iropcode[2:0]ir_addr[12:0]`timescale1ns/1nsmoduleregister(opc_iraddr,data,ena,clk,rst);output[15:0]opc_iraddr;input[7:0]data;inputena,clk,rst;reg[15:0]opc_iraddr;regstate;always@(posedgeclk)beginif(rst)beginopc_iraddr<=16'b0000_0000_0000_0000;state<=1'b0;endelseif(ena)casex(state)1'b0:beginopc_iraddr[15:8]<=data;state<=1;end1'b1:beginopc_iraddr[7:0]<=data;state<=0;enddefault:beginopc_iraddr[15:0]<=16'bx;state<=1'bx;endendcase elsestate<=1'b0;endendmodule17.3.3累加器resetclkload_accalu_out[7:0]moduleaccum(accum,data,ena,clk,rst);output[7:0]accum;input[7:0]data;inputena,clk,rst;reg[7:0]accum;always@(posedgeclk)beginif(rst)accum<=8'b0000_0000;elseif(ena)accum<=data;endendmodule17.3.4算術(shù)邏輯運(yùn)算器助記符操作碼功能HLT3'b000

暫停SKZ3‘b001累加器為零轉(zhuǎn)移ADD3’b010加ANDD3‘b011與XORR3‘b100或LDA3‘b101取數(shù)STO3‘b110存數(shù)JMP3‘b111轉(zhuǎn)移`timescale1ns/1nsmodulealu(alu_out,zero,data,accum,alu_ena,opcode,clk);output[7:0]alu_out;outputzero;input[7:0]data,accum;input[2:0]opcode;inputalu_ena,clk;reg[7:0]alu_out;parameterHLT=3'b000,SKZ=3'b001,ADD=3'b010,ANDD=3'b011,XORR=3'b100,LDA=3'b101,STO=3'b110,JMP=3'b111;

assignzero=!accum;always@(posedgeclk)if(alu_ena)begincasex(opcode)HLT:alu_out<=accum;SKZ:alu_out<=accum;ADD:alu_out<=data+accum;ANDD:alu_out<=data&accum;XORR:alu_out<=data^accum;LDA:alu_out<=data;STO:alu_out<=accum;JMP:alu_out<=accum;default:alu_out<=8'bxxxx_xxxx;endcaseend

endmodule17.3.5數(shù)據(jù)控制器data[7:0]alu_out[7:0]datactl_enamoduledatactl(data,in,data_ena);output[7:0]data;input[7:0]in;inputdata_ena;assigndata=(data_ena)?in:8'bz;endmodule17.3.6地址多路器moduleadr(addr,fetch,pc_addr,ir_addr);inputfetch;input[12:0]pc_addr,ir_addr;output[12:0]addr;assignaddr=fetch?pc_addr:ir_addr;endmodule17.3.7程序計數(shù)器modulecounter(pc_addr,ir_addr,load,clk,rst);inputload,clk,rst;input[12:0]ir_addr;output[12:0]pc_addr;reg[12:0]pc_addr;always@(posedgeclkorposedgerst) if(rst)pc_addr<=13'b0_0000_0000_0000;elseif(load)pc_addr<=ir_addr;elsepc_addr<=pc_addr+1;endmodule17.3.8狀態(tài)控制器`timescale1ns/1nsmodulemachinectl(ena,fetch,rst,clk);inputfetch,rst,clk;outputena;regena;always@(posedgeclk)beginif(rst)ena<=0;elseif(fetch)ena<=1;endendmodule17.3.8狀態(tài)控制器狀態(tài)控制器兩部分：狀態(tài)機(jī)（machine）狀態(tài)控制器machinectl rst有效，ena=0， 狀態(tài)機(jī)停止工作。17.3.8狀態(tài)控制器000001010011100101110111狀態(tài)機(jī)是CPU的核心部件，用于產(chǎn)生控制信號：啟動、停止某些部件CPU執(zhí)行讀指令來讀寫接口、存儲器狀態(tài)變量state的值，是指令周期已經(jīng)過的時鐘數(shù)指令周期中8個時鐘完成的操作第0個時鐘：rd和load_ir為高電平，ROM中高八位指令代碼-->指令寄存器第1個時鐘：rd和load_ir為高電平，inc_pc加1，故PC+1，ROM中低八位指令代碼-->指令寄存器第2個時鐘：空操作第3個時鐘：PC+1，指向下一條指令；若HLT指令，halt=1；其它指令控制線輸出為0指令周期中8個時鐘完成的操作第4個時鐘：若ANDADDXORLDA，讀相應(yīng)地址數(shù)據(jù);若JMP,目的地址-->PC;若STO,輸出累加器數(shù)據(jù)。第5個時鐘：若ANDADDXOR,進(jìn)行相應(yīng)運(yùn)算;若LDA,數(shù)據(jù)-->運(yùn)算器-->累加器;若JMP，鎖存目的地址；若STO，數(shù)據(jù)到地址處。第6個時鐘：空操作第7個時鐘：若SKZ指令，PC+1跳過一條指令；否則PC無變化`timescale1ns/1nsmodulemachine(inc_pc,load_acc,load_pc,rd,wr,load_ir,datactl_ena,halt,clk,zero,ena,opcode);outputinc_pc,load_acc,load_pc,rd,wr,load_ir;outputdatactl_ena,halt;inputclk,zero,ena;input[2:0]opcode;reginc_pc,load_acc,load_pc,rd,wr,load_ir;regdatactl_ena,halt;reg[2:0]state;parameterHLT=3'B000,SKZ=3'b001,ADD=3'b010,ANDD=3'b011,XORR=3'b100,LDA=3'b101,STO=3'b110,JMP=3'b111;

always@(negedgeclk)beginif(!ena)beginstate<=3'b000;{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0000;endelsectl_cycle;end

//-------beginoftaskctl_cycle-------taskctl_cycle;begincasex(state)3'b000:begin{inc_pc,load_acc,load_pc,rd}<=4'b0001;{wr,load_ir,datactl_ena,halt}<=4'b0100;state<=3'b001;end3'b001:begin{inc_pc,load_acc,load_pc,rd}<=4'b1001;{wr,load_ir,datactl_ena,halt}<=4'b0100;state<=3'b010;end

3'b010:begin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0000;state<=3'b011;end

3'b011:beginif(opcode==HLT)begin{inc_pc,load_acc,load_pc,rd}<=4'b1000;{wr,load_ir,datactl_ena,halt}<=4'b0001;state<=3'b100;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4'b1000;{wr,load_ir,datactl_ena,halt}<=4'b0000;state<=3'b100;endend3'b100:beginif(opcode==JMP)begin{inc_pc,load_acc,load_pc,rd}<=4'b0010;{wr,load_ir,datactl_ena,halt}<=4'b0000;endelseif(opcode==ADD||opcode==ANDD||opcode==XORR||opcode==LDA)begin{inc_pc,load_acc,load_pc,rd}<=4'b0001;{wr,load_ir,datactl_ena,halt}<=4'b0000;endelseif(opcode==STO)begin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0010;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0000;endstate<=3'b101;end

3'b101:begin//operationif(opcode==ADD||opcode==ANDD||opcode==XORR||opcode==LDA)begin{inc_pc,load_acc,load_pc,rd}<=4'b0101;{wr,load_ir,datactl_ena,halt}<=4'b0000;endelseif(opcode==SKZ&&zero==1)begin{inc_pc,load_acc,load_pc,rd}<=4'b1000;{wr,load_ir,datactl_ena,halt}<=4'b0000;endelseif(opcode==JMP)begin{inc_pc,load_acc,load_pc,rd}<=4'b1010;{wr,load_ir,datactl_ena,halt}<=4'b0000;endelseif(opcode==STO)begin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b1010;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0000;endstate<=3'b110;end

3'b110://idlebeginif(opcode==STO)begin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0010;endelseif(opcode==ADD||opcode==ANDD||opcode==XORR||opcode==LDA)begin{inc_pc,load_acc,load_pc,rd}<=4'b0001;{wr,load_ir,datactl_ena,halt}<=4'b0000;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0000;endstate<=3'b111;end

3'b111:beginif(opcode==SKZ&&zero==1)begin{inc_pc,load_acc,load_pc,rd}<=4'b1000;{wr,load_ir,datactl_ena,halt}<=4'b0000;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0000;endstate<=3'b000;enddefault:begin{inc_pc,load_acc,load_pc,rd}<=4'b0000;{wr,load_ir,datactl_ena,halt}<=4'b0000;state<=3'b000;endendcaseendendtask//-----------endoftaskctl_cycle--------------

endmodulecpuABDB地址譯碼器ROMRAMclockresetMICROCOMPUTERSYSTEMreadwrite17.3.9外圍模塊（地址譯碼器）moduleaddr_decode(addr,rom_sel,ram_sel);outputrom_sel,ram_sel;input[12:0]addr;regrom_sel,ram_sel;always@(addr)casex(addr)13'b1_1xxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b01;13'b0_xxxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b10;13'b1_0xxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b10;default:{rom_sel,ram_sel}<=2'b00;endcaseendmodule17.3.9外圍模塊（RAM）moduleaddr_decode(addr,rom_sel,ram_sel);outputrom_sel,ram_sel;input[12:0]addr;regrom_sel,ram_sel;always@(addr)casex(addr)13'b1_1xxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b01;13'b0_xxxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b10;13'b1_0xxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b10;default:{rom_sel,ram_sel}<=2'b00;endcaseendmodule17.3.9外圍模塊（ROM）modulerom(data,addr,read,ena);output[7:0]data;input[12:0]addr;inputena,read;reg[7:0]mem[13'h1fff:0];assigndata=(read&&ena)?mem[addr]:8'hzz;endmodule17.4RISC_CPU操作和時序主要操作：系統(tǒng)的復(fù)位和啟動操作總線讀操作總線寫操作17.4.1系統(tǒng)的復(fù)位和啟動操作復(fù)位狀態(tài)reset=1：CPU內(nèi)部寄存器全為零數(shù)據(jù)總線為高阻狀態(tài)地址總線為0000H所有控制信號為無效狀態(tài)啟動狀態(tài)reset=0：fetch上升沿啟動CPU開始工作從ROM的000處讀指令并執(zhí)行17.4.2總線讀操作復(fù)位狀態(tài)reset=1：CPU內(nèi)部寄存器全為零數(shù)據(jù)總線為高阻狀態(tài)地址總線為0000H所有控制信號為無效狀態(tài)啟動狀態(tài)reset=0：fetch上升沿啟動CPU開始工作從ROM的000處讀指令并執(zhí)行D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0高8位低8位地址碼指令碼17.5RISC_CPU尋址方式和指令系統(tǒng)指令數(shù)目：8條地址空間：213=8K17.5RISC_CPU尋址方式和指令系統(tǒng)直接尋址方式數(shù)據(jù)放在存儲器中，尋址單元的地址由指令直接給出。LDA010FH8EH00H77H56HEDHFFHFFH00H010FH010EH010DH010CH56H1010000100001111地址碼指令碼17.5RISC_CPU尋址方式和指令系統(tǒng)HLT:停機(jī)操作該操作空一個指令周期，即8個時鐘SKZ:為零跳過下一條語句累加器結(jié)果為零，跳過下一語句；累加器結(jié)果不為零，順序執(zhí)行。ADD:相加累加器的值+地址所知的存儲器中的數(shù)據(jù)，結(jié)果送回累加器。17.5RISC_CPU尋址方式和指令系統(tǒng)ANDD:相與累加器的值&地址所知的存儲器中的數(shù)據(jù)，結(jié)果送回累加器。XORR:相異或累加器的值^地址所知的存儲器中的數(shù)據(jù)，結(jié)果送回累加器。LDA:讀數(shù)據(jù)地址所知的存儲器中的數(shù)據(jù)送累加器。17.5RISC_CPU尋址方式和指令系統(tǒng)STO:寫數(shù)據(jù)累加器中的數(shù)據(jù)送地址所指的存儲器中JMP:無條件跳轉(zhuǎn)語句該操作跳轉(zhuǎn)至指令給出的目的地址，繼續(xù)執(zhí)行。累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機(jī)時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567LDA1000B000EE0110001001RAMEEload_accaddress000000011000B00000000001ROM0000020002累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機(jī)時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567ADD10015001EE1110001001RAM11load_accaddress000200031001500100020003ROM00040004累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機(jī)時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567STO1001D001EE0110001001RAMFFwraddress000400051001D00100040005ROM00060006@00111_00000//00BEGIN:JMPTEST_JMP0011_1100000_00000//02HLT0000_0000000_00000//04HLT0000_0000101_11000//06JMP_OK:LDADATA_10000_0000001_00000//08SKZ0000_0000000_00000//0AHLT0000_0000101_11000//0CLDADATA_20000_0001001_00000//0ESKZ0000_0000111_00000//10JMPSKZ_OK0001_0100000_00000//12HLT0000_0000110_11000//14SKZ_OK:STOTEMP0000_0010101_11000//16LDADTAT_10000_0000110_11000//18STOTEMP0000_0010101_11000//1ALDATEMP0000_0010001_00000//1CSKZ0000_0000000_00000//1EHLT0000_0000100_11000//20XORRDTAT_20000_0001001_00000//22SKZ0000_0000000_00000//24HLT0000_0000111_00000//26JMPXORR_OK0010_0100100_11000//28XORR_OK:XORRDATA_20000_0001001_00000//2ASKZ0000_0000000_00000//2CHLT0000_0000000_00000//2EEDN:HLT0000_0000111_00000//30JMPBEGIN0000_0000@3C111_00000//3CTST_JMP:JMPJMP_OK0000_0110000_00000//3EHLTROM@0000000000//1800DATA_111111111//1801DATA_210101010//1802TEMP

RAM17.6RISC_CPU模塊的調(diào)試cpuABDB地址譯碼器ROMRAMclockresetreadwrite`include"clk_gen.v"`include"register.v"`include"accum.v"`include"adr.v"`include"alu.v"`include"machine.v"`include"machinectl.v"`include"counter.v"`include"datactl.v"`timescale1ns/1nsmodulecpu(clk,reset,halt,rd,wr,addr,data,opcode,fetch,ir_addr,pc_addr);inputclk,reset;outputrd,wr,halt;output[12:0]addr;output[2:0]opcode;outputfetch;output[12:0]ir_addr,pc_addr;inout[7:0]data;wireclk,reset,halt;wire[7:0]data;wire[12:0]addr;wirerd,wr，wirefetch,alu_ena;wire[2:0]opcode;wire[12:0]ir_addr,pc_addr;wire[7:0]alu_out,accum;wirezero,inc_pc,load_acc,load_pc,load_ir,data_ena,contrl_ena;endmodulemodulecpu(clk,reset,halt,rd,wr,addr,data,opcode,fetch,ir_addr,pc_addr);

clk_genm_clkgen(.clk(clk),.reset(reset),.fetch(fetch),.alu_ena(alu_ena));registerm_register(.data(data),.ena(load_ir),.rst(reset),.clk(clk),.opc_iraddr({opcode,ir_addr}));accumm_accum(.data(alu_out),.ena(load_acc),.clk(clk),.rst(reset),.accum(accum));alum_alu(.data(data),.accum(accum),.clk(clk),.alu_ena(alu_ena),.opcode(opcode),.alu_out(alu_out),.zero(zero));machinectlm_machinectl(.clk(clk),.rst(reset),.fetch(fetch),.ena(contrl_ena));machinem_machine(.inc_pc(inc_pc),.load_acc(load_acc),.load_pc(load_pc),.rd(rd),.wr(wr),.load_ir(load_ir),.clk(clk),.datactl_ena(data_ena),.halt(halt),.zero(zero),.ena(contrl_ena),.opcode(opcode));datactlm_datactl(.in(alu_out),.data_ena(data_ena),.data(data));adrm_adr(.fetch(fetch),.ir_addr(ir_addr),.pc_addr(pc_addr),.addr(addr));counterm_counter(.clk(inc_pc),.rst(reset),.ir_addr(ir_addr),.load(load_pc),.pc_addr(pc_addr));

endmodule`include"cpu.v"`include"ram.v"`include"rom.v"`include"addr