數(shù)字邏輯雙語(yǔ)courseware8analysis and synthesis of asynchronous sequential logic circuits

Analysis&DesignofAsynchronousSequentialLogicCircuitsDigitalLogic2StepsofAnalysisofSequentialLogicCircuitsTheGivenSequentialLogicCircuitListtheOutputEquation&drivingEquationBuildupTheStateTransitionTableOrStateTransitionDiagramBuildupTheExpressionOfNextStatesDrawtheTimingDiagramTellthelogicFunctionOfGivencircuitsDigitalLogic3PointsofAnalysisofSequentialLogicCircuitsPoints(Incomparisonwithsynchronousones)ShouldtakeintoaccounttherespectiveclockinputofeachFFwhileanalyzingthetransitionofstates.

ShouldbeginfromthefirsteffectedFFwhileanalyzingthetransitionofstates.DigitalLogic4Example1ofAnalysisofAsynchronousLogicCircuitsAnalyzethefollowingcircuitsTheClockEquation:drivingEquations:DigitalLogic5Example1CharacteristicEquationofDFF:Substitutein:CP

RisingEdgeDigitalLogic6Example1LogicFunctionWecansee,underClockPulse,the8stateschangeasfollowed.000→111→110→101→100→011→010→001→000→…Itisthe3-digitbinarydowncounter

withthemodule8.DigitalLogic7Example2Example.TrytoanalyzethecircuitsSteps:(1)Listoutthelogicequations①ClockEquationsCP0=CP(risingedge)CP1=Q0(Q0’srisingedge)DigitalLogic8Example2(3)MaketheSTT(2)Getthestateequations(CP↑)

(Q0↑)

PresentStateNextStateOutputCPQ1n

Q0n

Q1n+1

Q0n+1

ZCP1CP0

CP1=Q0①ClockEquation:CP0=CP001000↑↑1111↑0101010↑↑0100↑0②OutputEquations③drivingEquationsDigitalLogic9Example2(5)Tellthelogicfunction

Thereare4Statesinall:00,01,10,11.Andeverytimeitminus1,soitisa2-digitdowncounterwiththemodule4.andZtheborrowingsignal.

(4)MaketheSTD,TDDigitalLogic10Example1ofSynthesisofAsynchronousLogicCircuits(1)Appoint7statesaccordingtothedemands,S0～S6.

Encodethemandlistthestatetransitiontable.Example,Designaupcounterwiththemodule7SequencePresentStateNextStateOutputQ2n

Q1n

Q0n

Q2n+1

Q1n+1

Q0n+1

YS0S1S2S3S4S5S60000010100111001011100010100111001011100000000001

ThereshouldbeanadditionalstepwhichistoderivetheClockEquationofFFsincomparisonwithsynthesisofsynchronousCircuits.DigitalLogic11Example1WhatistheprinciplestodeterminetheCP?:①whilestatereverses,theremustexistclockpulse.②whilestatekeepsunchanged,thelessredundantCPthebetter.THETIMINGDIAGRAMFollowingprinciplesabove:(2)ChooseproperFFs,wetakeJKFF(↓)inthisexample.(3)DerivetheClockEquationofeachFF,thatistodetermineproperSignalinputofeachFF.DigitalLogic12(4)Derivethedrivingequationsandoutputequation.DerivethemfromK-mapofnextstatesandcharacteristicequationsExample1d111因?yàn)闀r(shí)鐘源是CP，所以與同步電路等同DigitalLogic13Example1d111(4)Derivethedrivingequationsandoutputequation.DerivethemfromK-mapofnextstatesandcharacteristicequations因?yàn)闀r(shí)鐘源是CP，所以與同步電路等同DigitalLogic14Example1d111(4)Derivethedrivingequationsandoutputequation.DerivethemfromK-mapofnextstatesandcharacteristicequationsIsthisright?DigitalLogic15Example1d111Itisnottrue,forCPnowisQ1在上述卡諾圖中，考察每格對(duì)應(yīng)的CP時(shí)鐘下降沿處是否有Q1的下降沿，如果沒(méi)有，則對(duì)應(yīng)處作為約束項(xiàng)處理。如果有，則其值有效。(4)Derivethedrivingequationsandoutputequation.DigitalLogic16Example1在上述卡諾圖中，考察每格對(duì)應(yīng)的CP時(shí)鐘下降沿處是否有Q1的下降沿，如果沒(méi)有，則對(duì)應(yīng)處作為約束項(xiàng)處理。如果有，則其值有效。CP7CP6CP5CP3CP4CP2CP1CP4,CP7

=>fallingedgeCP12356=>dCP7dddCP4dd(4)Derivethedrivingequationsandoutputequation.DigitalLogic17Example1CP7ddddCP4dd0dddd1dd(4)Derivethedrivingequationsandoutputequation.DigitalLogic18Thesum-up000000×1Example1(4)Derivethedrivingequationsandoutputequation.DigitalLogic19Example1(5)

DrawthecircuitsQCCQKJJJKKCQ2Q0QQ1CPYoutput≥11≥1&1<<<FF0FF1FF2Digital