第三講altera器件高級(jí)特性與應(yīng)用

西安電子科技大 信號(hào)處luofeng@xidianedu 布線工具對(duì)邏輯的。布線工具對(duì)邏輯的。PLLsprovideclocksynthesisandmanagementforon-chipclocks,externalsystemclocks,andhigh-speed/Ointerfaces CP mPLLsaligninputreferenceclocktofeedbackclockusingphase-frequencydetector(PFD)circuitloopfilter(LF)andchargepump(CP)useoutputsignalsfromPFDtobiasvoltagecontrolledoscillator(VCO)VCObiasdeterminesitsoperationalZeroDelayBufferExternalDedicatedClockOutputAlignedWithReferenceInputClockZeroDelayBufferExternalDedicatedClockOutputAlignedWithReferenceInputClock(outputclocktCOis0)IdealforSystemClockGeneration&(1)TheinternalclockoutputcanleadorlagthePLLclockoutputNormalZeroDelayInputclockalignedwithdedicatedexternalclockExternalInputclockalignedwithexternalfeedbackinputforsynchronizingmulti-chipsystemsStratixIIfeedanyoutputtotheNoClock-to-datarelationshipatinputpin(setup/hold)maintainedattheIOEregister NormalNormalClockatInputPinAlignedwithClockatIOEorCoreRegister,suchthatClockDelayis0ExternalFeedbackInputisAlignedWithReferenceInputClockNoNoCompensationClockDelayWithintheFPGAisNotProvidesBestJitterClockDelayisMatchedwithDataDelaytoIOEInputIdealforSourceSynchronousTransfersW/ODataclk[]SpectrumSpectrumGenGeneratiingSelecttheALTPLLMegafunctionforStratix,StratixIIGenGeneratiingOperatingPLLDeviceInputClockModifyBandwidthofOutputParameterConfigureEachOutput012469Single-PortSingle-PortSingle-PortRead&WriteAddressAretheSamePortSupportsNon-SimultaneousReadorWriteOperationAllInputsClockingSingle-Portaddress[]data[] q[SeparateRead&WriteReadandWriteAllInputsInput/OutputClockRead/WriteClockSimpleDual-Portwraddress[]data[]rdaddress[q[TrueTrueDual-PortTrueDual-PortTrueDual-PortPortA&PortReadandWriteOnEitherAddressAllInputsClockingInput/OutputClockIndependentClockaddress[]data[] data[address[]q[q[FirstinFirstOutIdealforRateAllInputsAreClockingSingleRead/WriteClockReadOnlyAllInputsAreClockingSingleInput/OutputM512/M4KBlocksOnlyforInputRegisterPipelineOutputMuxOutputX4個(gè)8個(gè)+X+X+XAdd/Sub/AccSimpleSimpleMultiplierInputRegisterPipeline18XOutputMuxOutput++X+XInputRegisterPipelineA[17XB[17OutputMuxOutputA[35XB[35+A[35B[17XA[17XB[35PartialProductInputRegisterPipelineOutputMuxOutputXX+XXSoftwareQuartusIISupportforDSPBlocksSupportsSoftwareQuartusIISupportforDSPBlocksSupportsMultiply-accumulateFloatingPointPutsMultipliersInMemoryConfigurableviaTwoTwoMultiplierAdderInputRegisterPipelineOutputMuxOutputXX+XX FourFourMultipliersAdderInputRegisterPipelineOutputMuxOutputXX+XXLocatedLocatedInArithmeticSelect#ofSignedvs.SerialShiftAdd/Subtract/DynamicFIRFilterEquationandy(n)h(k)*x(n)h(k)x(nkZXXXXXXDSPBlockDSPBlockXXOn-ChipOn-ChipDifferentialOn-Chip100,DifferentialSupportsLVDSandZZ50 No OnChipDifferentialDPAGeneratesSeveralPhasesoftheClock&UsesOptimumPhaseforEachChannelWithoutWithSampleTooClosetoSampleAtOptimumPointSupportsx1outputClockgeneratedbythePLLcanbedividedLogicisautomaticallygeneratedbyQuartusII ExampleDividex10OutputStratixIILogicArrayLVDSLVDSTransmitTransmitPhaseSinglePLLcanbeusedtocompensateforinputclock-dataalignmentaswellasoutputclock-dataalignment...WhyWhyParallelInterfaceWorkedforShortDistances&SlowDataRatesLongerDistancesandFasterDataRatesCreateTimingDifficultiesTightSkew&TimingWiderInterfacesIntroduceHostOfHigherPinCount,IncreasedPower,WiderConnectors,MoreComplexLayoutSimultaneousSwitchingNoiseandHigherSkewandTightTimingSerializationSolvesMostofTheseStratixStratixGXTransceiver&WordtoTxRxBackpBackpllane ne:30”Trace(FR-StratixGXBoard:5”onBothDataRate:3.125PointPointDaughterBackDrawingNotToLength:DataRate:3.125OutputVoltage:400mVPoint PointPre-emphasisScopeScopePre-EmphasisPre-EmphasisOpenstheLength:DataRate:3.125OutputVoltage:400mVPoint PointPre-emphasisSetToScopeScopeLength:DataRate:3.125OutputVoltage:400mVPoint PointPre-emphasisSetToScope ScopeLength:DataRate:3.125OutputVoltage:400mVPointPointPre-emphasisSetToScopeScopeEqu