EDA課程設計-DDS信號源

寧波理工學院寧波理工學院EDA課程設計題目DDS信號源一．函數(shù)信號發(fā)生器簡介函數(shù)信號發(fā)生器在生產實踐和科技領域有著廣泛的應用。本設計是采用了EDA技術設計的函數(shù)信號發(fā)生器。此函數(shù)信號發(fā)生器的實現(xiàn)是基于VHDL語言描述各個波形產生模塊，然后在QuartusⅡ軟件上實現(xiàn)波形的編譯，仿真和下載到Cyclone芯片上。整個系統(tǒng)由波形產生模塊和波形選擇模塊兩個部分組成。最后經過QuartusⅡ軟件仿真，證明此次設計可以輸出正弦波、方波、三角波等規(guī)定波形，并能根據(jù)波形選擇模塊的設定來選擇波形輸出。二．實驗軟件QuartusⅡ簡介QuartusII是Alera公司推出的一款功能強大，兼容性最好的EDA工具軟件。該軟件界面友好、使用便捷、功能強大，是一個完全集成化的可編程邏輯設計環(huán)境，具有開放性、與結構無關、多平臺完全集成化豐富的設計庫、模塊化工具、支持多種硬件描述語言及有多種高級編程語言接口等特點。QuartusII是Altera公司推出的CPLD/FPGA開發(fā)工具，QuartusII提供了完全集成且與電路結構無關的開發(fā)包環(huán)境，具有數(shù)字邏輯設計的全部特性，包括：可利用原理圖、結構框圖、VerilogHDL、AHDL和VHDL完成電路描述，并將其保存為設計實體文件；芯片平面布局連線編輯；功能強大的邏輯綜合工具；完備的電路功能仿真與時序邏輯仿真工具；定時/時序分析與關鍵路徑延時分析；可使用SignalTapII邏輯分析工具進行嵌入式的邏輯分析；支持軟件源文件的添加和創(chuàng)建，并將它們鏈接起來生成編程文件；使用組合編譯方式可一次完成整體設計流程；自動定位編譯錯誤；高效的期間編程與驗證工具；可讀入標準的EDIF網表文件、VHDL網表文件和Verilog網表文件；能生成第三方EDA軟件使用的VHDL網表文件和Verilog網表文件。三．設計主要任務及要求一．波形選擇：通過按鍵選擇不同的輸出波形。二．波形發(fā)生：通過軟件實現(xiàn)各類波形的產生。三．波形頻率控制：通過按鍵實現(xiàn)對輸出波形頻率的控制四．總體設計方案函數(shù)信號發(fā)生器主要由波形選擇部分，波形發(fā)生部分和輸出部分組成，其硬件結構圖如下圖。五．電路圖六．單元電路設計一．頻率控制模塊代碼LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; USEIEEE.STD_LOGIC_UNSIGNED.ALL; ENTITYFREQUENCYIS PORT(CLK:INSTD_LOGIC; A:INSTD_LOGIC_VECTOR(4DOWNTO0);--設置A的初值 FOUT:OUTSTD_LOGIC); END; ARCHITECTUREoneOFFREQUENCYIS SIGNALFULL:STD_LOGIC; BEGIN P_REG:PROCESS(CLK) VARIABLECNT1:STD_LOGIC_VECTOR(4DOWNTO0); BEGIN IFCLK'EVENTANDCLK='1'THEN IFCNT1="11111"THEN CNT1:=A;--當CNT1計數(shù)計滿時，輸入數(shù)據(jù)D被同步預置給計數(shù)器CNT1 FULL<='1';--同時使溢出標志信號FULL輸出為高電平 ELSECNT1:=CNT1+1;--否則繼續(xù)作加1計數(shù) FULL<='0';--且輸出溢出標志信號FULL為低電平 ENDIF; ENDIF; ENDPROCESSP_REG; P_DIV:PROCESS(FULL) VARIABLECNT2:STD_LOGIC; BEGIN IFFULL'EVENTANDFULL='1'THEN CNT2:=NOTCNT2;--如果溢出標志信號FULL為高電平，D觸發(fā)器輸出取反 IFCNT2='1'THENFOUT<='1'; ELSEFOUT<='0'; ENDIF; ENDIF; ENDPROCESSP_DIV; END;模塊元件圖二．按鍵選擇模塊代碼LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYBUTTONISPORT(d:INSTD_LOGIC_VECTOR(2DOWNTO0);a,b,c:OUTSTD_LOGIC);END;ARCHITECTUREONEOFBUTTONISBEGINPROCESS(d)BEGINCASEdISWHEN"000"=>NULL;WHENOTHERS=>a<=d(0);--dltb<=d(1);--sqrc<=d(2);--sin ENDCASE;ENDPROCESS;END;模塊元件圖三．三角波信號產生模塊代碼libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitydeltaisport(clk:instd_logic;clr:instd_logic;q:outstd_logic_vector(7downto0));enddelta;architectureoneofdeltaisbeginprocess(clk,clr)variablenum:std_logic_vector(7downto0);variableff:std_logic;beginifclr='0'thennum:="00000000";elseifclk'eventandclk='1'then--時鐘信號有上升沿時有效ifff='0'thenifnum="11111000"thenff:='1';elsenum:=num+8;endif;--以上，ff=0時，上升，直至num加到11111000時，使ff=1elseifnum="00000111"thennum:="00000000";ff:='0';elsenum:=num-8;--以上，ff=1時，下降，直至num減到00000111時，使ff=0endif;endif;endif;endif;q<=num;--每一次脈沖，將num的值給q以輸出endprocess;end;模塊元件圖四．方波信號產生模塊代碼libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityaquareisport(clk:instd_logic;clr:instd_logic;q:outstd_logic_vector(7downto0));endaquare;architectureoneofaquareissignalff:bit;beginp1:process(clk,clr)variablenum:std_logic_vector(5downto0);beginifclr='0'thenff<='0';elseifclk'eventandclk='1'then--當時鐘脈沖有一個上升沿ifnum<31thennum:=num+1;elsenum:="000000";ff<=notff;--num每次加1，加32次ff取反1次endif;endif;endif;endprocessp1;p2:process(clk,ff)beginifclk'eventandclk='1'thenifff='1'thenq<="11111111";--ff=1時輸出高電平elseq<="00000000";--ff=0時輸出低電平endif;endif;endprocessp2;end;模塊元件圖五．正弦波信號產生模塊代碼libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitysinisport(clk:instd_logic;--正弦信號的相位clr:instd_logic;d:outstd_logic_vector(7downto0));--正弦函數(shù)值end;architectureoneofsinis--結構體開始beginprocess(clk,clr)variablenum:std_logic_vector(5downto0);beginifclr='0'thend<="00000000";elseifclk'eventandclk='1'thenifnum="111111"thennum:="000000";--每加到111111時清零elsenum:=num+1;endif;endif;endif;casenumis--四個輸入，共有16總相位可能360/64=5.625when"000000"=>d<=CONV_STD_LOGIC_VECTOR(128,8);--每5.625取一個點 when"000001"=>d<=CONV_STD_LOGIC_VECTOR(141,8);--共64個點 when"000010"=>d<=CONV_STD_LOGIC_VECTOR(153,8); when"000011"=>d<=CONV_STD_LOGIC_VECTOR(165,8); when"000100"=>d<=CONV_STD_LOGIC_VECTOR(177,8); when"000101"=>d<=CONV_STD_LOGIC_VECTOR(188,8); when"000110"=>d<=CONV_STD_LOGIC_VECTOR(199,8); when"000111"=>d<=CONV_STD_LOGIC_VECTOR(209,8); when"001000"=>d<=CONV_STD_LOGIC_VECTOR(218,8); when"001001"=>d<=CONV_STD_LOGIC_VECTOR(227,8); when"001010"=>d<=CONV_STD_LOGIC_VECTOR(234,8); when"001011"=>d<=CONV_STD_LOGIC_VECTOR(240,8); when"001100"=>d<=CONV_STD_LOGIC_VECTOR(246,8); when"001101"=>d<=CONV_STD_LOGIC_VECTOR(250,8); when"001110"=>d<=CONV_STD_LOGIC_VECTOR(253,8); when"001111"=>d<=CONV_STD_LOGIC_VECTOR(254,8); when"010000"=>d<=CONV_STD_LOGIC_VECTOR(255,8); when"010001"=>d<=CONV_STD_LOGIC_VECTOR(254,8); when"010010"=>d<=CONV_STD_LOGIC_VECTOR(253,8); when"010011"=>d<=CONV_STD_LOGIC_VECTOR(250,8); when"010100"=>d<=CONV_STD_LOGIC_VECTOR(246,8); when"010101"=>d<=CONV_STD_LOGIC_VECTOR(240,8); when"010110"=>d<=CONV_STD_LOGIC_VECTOR(234,8); when"010111"=>d<=CONV_STD_LOGIC_VECTOR(227,8); when"011000"=>d<=CONV_STD_LOGIC_VECTOR(218,8); when"011001"=>d<=CONV_STD_LOGIC_VECTOR(209,8); when"011010"=>d<=CONV_STD_LOGIC_VECTOR(199,8); when"011011"=>d<=CONV_STD_LOGIC_VECTOR(188,8); when"011100"=>d<=CONV_STD_LOGIC_VECTOR(177,8); when"011101"=>d<=CONV_STD_LOGIC_VECTOR(165,8); when"011110"=>d<=CONV_STD_LOGIC_VECTOR(153,8); when"011111"=>d<=CONV_STD_LOGIC_VECTOR(141,8); when"100000"=>d<=CONV_STD_LOGIC_VECTOR(128,8); when"100001"=>d<=CONV_STD_LOGIC_VECTOR(115,8); when"100010"=>d<=CONV_STD_LOGIC_VECTOR(103,8); when"100011"=>d<=CONV_STD_LOGIC_VECTOR(91,8); when"100100"=>d<=CONV_STD_LOGIC_VECTOR(79,8); when"100101"=>d<=CONV_STD_LOGIC_VECTOR(68,8); when"100110"=>d<=CONV_STD_LOGIC_VECTOR(57,8); when"100111"=>d<=CONV_STD_LOGIC_VECTOR(47,8); when"101000"=>d<=CONV_STD_LOGIC_VECTOR(38,8); when"101001"=>d<=CONV_STD_LOGIC_VECTOR(29,8); when"101010"=>d<=CONV_STD_LOGIC_VECTOR(22,8); when"101011"=>d<=CONV_STD_LOGIC_VECTOR(16,8); when"101100"=>d<=CONV_STD_LOGIC_VECTOR(10,8); when"101101"=>d<=CONV_STD_LOGIC_VECTOR(6,8); when"101110"=>d<=CONV_STD_LOGIC_VECTOR(3,8); when"101111"=>d<=CONV_STD_LOGIC_VECTOR(1,8); when"110000"=>d<=CONV_STD_LOGIC_VECTOR(0,8); when"110001"=>d<=CONV_STD_LOGIC_VECTOR(1,8); when"110010"=>d<=CONV_STD_LOGIC_VECTOR(3,8); when"110011"=>d<=CONV_STD_LOGIC_VECTOR(6,8); when"110100"=>d<=CONV_STD_LOGIC_VECTOR(10,8); when"110101"=>d<=CONV_STD_LOGIC_VECTOR(16,8); when"110110"=>d<=CONV_STD_LOGIC_VECTOR(22,8); when"110111"=>d<=CONV_STD_LOGIC_VECTOR(29,8); when"111000"=>d<=CONV_STD_LOGIC_VECTOR(38,8); when"111001"=>d<=CONV_STD_LOGIC_VECTOR(47,8); when"111010"=>d<=CONV_STD_LOGIC_VECTOR(57,8); when"111011"=>d<=CONV_STD_LOGIC_VECTOR(68,8); when"111100"=>d<=CONV_STD_LOGIC_VECTOR(79,8); when"111101"=>d<=CONV_STD_LOGIC_VECTOR(91,8); when"111110"=>d<=CONV_STD_LOGIC_VECTOR(103,