電氣專業(yè)畢業(yè)設(shè)計(jì)外文文獻(xiàn)與中文翻譯

河南理工大學(xué)萬方科技學(xué)院本科畢業(yè)論文PAGE1附錄：外文資料與中文翻譯外文資料：NeedsofMultimediaProcessorDynamicPowerManagementTechnologyActivePowerManagementOn-chippowermanagementtechniquesfallintotwobroadcategories,themanagementofsystempowerconsumptionandstandbypowerconsumptionmanagement.ActivePowerManagementisdividedintothreeareas:dynamicvoltageandfrequencyscaling(DVFS),adaptivevoltagescaling(AVS)anddynamicpowerswitching(DPS).Staticpowermanagementsystemsneedtoensurethattheidleprocessingpowerneededbeforeahigherpowerinthestate,thatis,theuseoftheso-calledstaticleakagemanagement(SLM)technology,thiskindofmanagementisusuallydependentonpowerfromstandbytoseverallowpowerconsumptionpatterns.Let'stakealookattheactivemode.UsingDVFStechniques,applicationperformancecanbebasedondemandsoftwaretoreducetheclockspeedandvoltage.Forexample,wemayenvisageahigh-levelintegratedRISCmicroprocessor(ARM)anddigitalsignalprocessor(DSP)applicationsprocessor.AlthoughtheARMspeedcomponentscanbeashighas600MHz,butthesystemdoesnotalwaysneedsuchahighcomputingpower.Usually,wecanchoosesoftwaretopredefinedperformancepointprocessor(OPP),thevoltageatthistimetoensurethattheprocessorinthesystemcanmeetperformancerequirementsontheminimumfrequency.Inordertoadapttodifferentapplicationstofurtherenhancetheflexibilitytooptimizepower,wecaninterconnectforprocessorsandperipheralsinadditionasetofpredefinedcoredevicesOPP.OPPsoftwareinaccordancewithanexternalregulatorisrequiredtosendcontrolsignalstosettheminimumvoltage.Forexample,DVFSapplytothetwosupplyvoltageVDD1(DSPandARMprocessorssupplyvoltage)andVDD2(peripheralsubsystemsinterconnectionandpowersupplyvoltage),thetwovoltagerailstoprovidethemajorityofchippower(usually75%to80%).IntheimplementationofMP3decoder,theDSPprocessorcanbetransferredtolow-performancepoint,thusgreatlyreducingthepowerconsumptionforothertasks,whentheARMoperatingfrequencyupto125MHz.Inordertoachievethebestpowernecessaryfunctionality,weVDD1canbereducedto0.95voltsinsteadofthemaximumvoltageof1.35voltstoensurethattheworkingfrequencyof600MHz.Adaptivevoltagescaling(AVS)asasecondactivepowermanagementtechnology,basedonthechipmanufacturingprocess,aswellasthelifecycleofdeviceoperationgeneratedbasedonthedifference.Thetechnologyandallprocessorssharethesamepre-programmeddifferentDVFStheOPP.Itcanbeinferredthatthemajorityofthemanufacturingprocesshasmatured,thechip'sperformanceintheestablishedfrequencytofollowacertainrequestdistribution.Somedevices(theso-called"hot"devices)comparedtootherdevices(theso-called"cold"devices),thelowervoltagetoachieveagivenfrequency,andthisistheroleoftheprincipleofAVS-Processorsensorstotheirownperformancelevel,andadjustthesupplyvoltage.AVSdedicatedhardwarechipfeedbackloopcanbeimplementedwithoutprocessorinterventionvoltageleveldynamicoptimizationtomeettheneedsoftheprocess,temperatureandsiliconattenuationdifferencecausedbytherequirements(Figure1).Figure1Giventheperformanceofthedistributionofatypicalprocessor.Here's"cool"deviceinthefrequencyof125MHzneedto0.94volts,whilethe"hot"deviceinthefrequencyofonly0.83volts.Adaptivevoltagescaling(AVS)technologyusesthecorrespondingfeedbackloopsupplyvoltageregulatortoensurethatalldevicesrunningtasksinaspecificfrequencyrequiredSoftwarecanworkforeachOPPsetupAVShardware,andcontrolalgorithmsthroughI2Cbustosendcommandstoexternalvoltageregulatorinordertograduallyreducetheoutputoftheappropriateregulator,untiljustoverthetargetprocessorfrequencyrequirement.Forexample,developerscandesignafirsttomeetallofthevoltage,frequencyof125MHzat0.95volts(inFigure1inthetopoftheV1).However,ifthesystemusingAVStechnologytoinsertthe"hot"device,thenthefeedbackmechanismon-chipARMwillautomaticallybereducedto0.85voltsofthevoltageorlower(V2inFigure1above).Thefirsttwoactivepowermanagementtechnologycanminimizetheoperatingvoltagesothatacertainpartofthedeviceinthedesiredspeed.Incontrast,thethirdmethod-Dynamicpowerswitching(DPS)todeterminethedevicewhenitcancompletethecalculationofthecurrenttask,ifnoneed,thenallowthedevicetoenterlow-powerstandbymode(Figure2).Forexample,theprocessorsarewaitingforDMAtransfertocompletetheprocesswillenteralow-powerstate.Processorinafewmicrosecondsafterthewake-upcallwillbeabletoreturntonormalworkingcondition.Figure2Dynamicpowerswitching(DPS)inagivenpartofadeviceafterthecompletionofthetasktoenterthelow-powerstatePassivepowermanagementAlthoughtheDPSwillallowmulti-mediasystem-on-chip(SoC)aspartofenteringthelow-powerstate,butinsomecases,wecanhavetheentiredeviceintothelowpowermode-intheabsenceoftheapplicationtorunautomaticallyorthroughuserrequestsaccesstolow-power.Toachievethisend,wecanbestaticleakagemanagement(SLM)technology,startthestandbymodeorturnoffthedevice.Thesetwomodelsofakeydifferenceis:Instandbymode,thedeviceisstilloccupiedbytheinternalmemoryandlogic,andintheclosedmodeofthedevice,allthesystemstateisstoredinexternalmemory.TheuseofSLMtechnology,wake-uptimemuchfasterthanthespeedofcoldstartbecausetheprocedureshavebeenloadedintotheexternalmemory,theuserhavingtowaitfortheoperatingsystem(OS)completelyrestarted.InthecaseoftheuseofSLMtechnology,wemediaplayerasanexample,ifaftertensecondstoopenhasnotbeenprocessinginstructionoruserinput,itwillclosethedisplaydevicetoenterstandbyorshutdownmode.Forexample,TIusingARMCortex-A8coreOMAP35xdevicesonasinglechipprocessortosupportthedeviceshutdownmode,thedevicecanautomaticallywake-upcallthatthelowestpowermode.Inadditiontowake-updomain,allpowerdomainareclosed,powerconsumption,onlytowakeupthedomainwiththeI/Oleakagecurrent.Shutdownthesystemclock,inthecircumstances,thewake-upclockdomainbyaseparatesetof32kHz.Inaddition,OMAP35xcanautomaticallysendsignalstoexternalregulators,voltageregulatorscanshutdownthedepthofsleep.Processordoesnotsavetheinternalmemoryorlogic.Intheelectricmodeintothedevicebeforetheclosure,thesystemstateisstoredinexternalmemory.Afterthewake-upreset,themicroprocessorunit(MPU)willactivatetheuser-definedfunctions,SDRAMcontrollerconfigurationfromthehigh-speedtemporarymemory(SPM)torecover.TomeetavarietyofusesoftechnologyThroughacombinationoftheabove-mentionedpowermanagementtechnology,wecanbeawiderangeofoperatingconditionstoachievethebestpower.Ifthesystemwasbusydealingwithhigh-resolutionvideoplaybackforportableplayerssuchastasks,thensetupinover-voltageVDD1onOPP.Ifitisamoderate-powerwebbrowsing,canbesetforVDD1andVDD2ratedtheOPP.Iflow-powermusiccanbesetforVDD1andVDD2lowestOPP.Inallthesecircumstances,wecanstarttheAVStobalancethe"cold""hot"powerdifferentialdevices.Finally,ifusersopenthemediaplayerbutnotafewhoursorafewdaysuse,itsadoptionofSLMtechnologywillautomaticallyshutdownthedeviceintothemodel.Tobetterunderstandtheuseoftechnologybroughtaboutbytheabove-mentionedenergy-savingadvantages,thefollowingcasesneedtobetakenintoaccount.Inthefollowingcases,unlesstherearespecificdescription,orwealldonotuseTI'sAVS/SmartReflextechnology.Inthesedescriptions,IVAreferstoimages,videoandaudioacceleratorsubsystem.CaseI:device-downmode-0.590mW.ThisisaTIOMAPcanautomaticallywakeuptheminimumpowermode.Inthismode,theentiredeviceinadditiontowake-upoutsidethecloseddomain,andthewake-upfrequencydomainislessthan32kHz.Closetheregulatordoesnotuse(VDD1=VDD2=0),auto-refreshSDRAM,specialstartsequencewhenthewake-upcalltorestorethesystemstatecontrollerandtheSDRAM.CaseII:standbymode-7mW.Devicesinthestate,onlytowakeupthedomain,allothernon-powerdomainwake-upareinalow-powerstateofpreservation(VDD1=VDD2=0.9V).Alllogicandmemorywillberetained.AVSclosed.CaseIII:AudioDecoder-22mW(excludingDPLLpowerandIO).AlthoughtheARMinthe125MHzfrequency,butonlyfromtheDMAsetmultimediacardreaderinputdata,andthenenterhibernation.MP3decoderIVAframe(44.1kHz,128kbpsstereo),anddecodingthedatasenttoabufferinSDRAM.Chipmulti-channelbufferedserialporttosenddatatotheaudiocodecforplayback.Onthesystemconfigurationisconcerned,DSP'soperatingfrequencyis90MHz,intheprocessingcyclewithoutenteringthelowpowermodetoreducepowerconsumption.Atthistime,VDD10.9V,VDD2voltsto1.Casefour:audio/videoencoding-540mW(non-DPLLpowerandIO).Inthatcase,wecaptureandencodeaudio(AACe+,48kHz,32kbpsstereo),videocaptureandencoding(H.264VGAresolution,20framespersecond,2.4Mbsp),audioandvideoarepreserved,Atthesametimetodisplayvideo.Intheconfiguration,ARMoperatesat500MHz,DSPoperatingfrequencyis360MHz,VDD11.2V,VDD2to1.15volts.Inaddition,thesubsystem-chipcamerasensorcancapturevideofromanexternalinput,multi-channelbufferedserialportinputPCMaudiocapture,IVAimplementationofaudioandvideoencoding,encodingdatastoredinthemultimediacard,whichmakesvideodisplaysubsystemcycle,andvideosenttotheLCDandTVoutputinterface.ImplementationofpowermanagementInordertoachievethefullflexibilityofpowermanagement,DSPprocessorchippowerdeviceresetandclockmanagement(PRCM).OMAP3530processorfunctionmoduleisdividedinto18powerdomains,eachdomainhasitsownpowerswitch.PRCMcanswitchallthepowerdomain,butmanypowersuppliesmayalsobeuser-controlleddomain.Inaddition,eachpowerdomaincanbebasedonwhetherthelogicandmemorypower,andtheclockisinworkingconditionandenterthefourstates:theworkofstate,non-workingcondition,andmaintainonoroff.OntheARMandDSPdevices,theabove-mentionedstateregulatorsusuallyrequireauxiliary.Manyofthemarketregulatorstomeettheserequirementscan,ofcourse,needtomeettheprocessor'svoltage,current,powerconversionrateofdeclineinnormsaswellasincreasedpowersequencingrequirements.InordertoARMprocessorandDSPimplementationofDVFSandAVSoperation,therelevantregulatormustsupportI2Cprogrammability.Inthedeviceshutdownmode,thecircuitthroughtheautomaticsystemmustbeissued,ortoaspecificI2CcommandstoopenorclosetheGPIOsignalVDD1andVDD2regulators.IftheuseofGPIOsignals,I2Cdoesnotexistasaresultofthedelay,thenthewake-uptimewillbefaster.Designengineersinordertoreducetheburdenofalltheabove-mentionedcharacteristicsofthebestfeaturesintegratedinasingledevice,therebysignificantlyreducingthenumberofcomponents(Figure3).Figure3Highvoltageregulatorchipintegratesanumberofswitchingregulatorwithlowdropoutlinearregulator,whichcanmeettheneedsofOMAP35xprocessorsvoltagedomainrequirements.

中文翻譯：滿足多媒體處理器需求動態(tài)電源管理技術(shù)有源電源管理片上電源管理技術(shù)分為兩大類，管理工作系統(tǒng)功耗與管理待機(jī)功耗。有源電源管理分為三個(gè)領(lǐng)域：動態(tài)電壓與頻率縮放(DVFS)、自適應(yīng)電壓調(diào)整(AVS)與動態(tài)電源切換(DPS)。靜態(tài)功耗管理需要確保閑置的系統(tǒng)在需要更高處理能力之前處于省電狀態(tài)，也就是采用所謂的靜態(tài)漏電管理(SLM)技術(shù)，這種管理通常依賴于從待機(jī)到斷電的幾種低功耗模式。我們先來看看主動模式。利用DVFS技術(shù)，可根據(jù)應(yīng)用的性能需求通過軟件來降低時(shí)鐘速度和電壓。例如，我們不妨設(shè)想一款集成了高級RISC微處理器(ARM)與數(shù)字信號處理器(DSP)的應(yīng)用處理器。盡管ARM組件的運(yùn)行速度可高達(dá)600MHz，但系統(tǒng)并不總是需要如此高的計(jì)算能力。通常，我們可通過軟件來選擇預(yù)定義的處理器工作性能點(diǎn)(OPP)，這時(shí)的電壓可確保處理器工作在可滿足系統(tǒng)處理性能要求的最低頻率上。為了適應(yīng)不同應(yīng)用，進(jìn)一步提高優(yōu)化功率的靈活性，我們還可為處理器中的互連與外設(shè)預(yù)定義另外一組器件內(nèi)核OPP。軟件根據(jù)OPP需向外部穩(wěn)壓器發(fā)送控制信號才能設(shè)置最低電壓。例如，DVFS適用于兩個(gè)供電電壓VDD1(DSP與ARM處理器的供電電壓)與VDD2(子系統(tǒng)與外設(shè)互連的供電電壓)，這兩個(gè)電壓軌提供了大部分芯片功率(通常在75%到80%之間)。在執(zhí)行MP3解碼時(shí)，可將DSP處理器轉(zhuǎn)入低操作性能點(diǎn)，從而大幅減少功耗供處理其他任務(wù)之用，這時(shí)的ARM運(yùn)行頻率高達(dá)125MHz。為了在最佳功耗情況下實(shí)現(xiàn)必需的功能性，我們可將VDD1降至0.95伏特，而不使用最高1.35伏特的電壓，以確保600MHz的工作頻率。自適應(yīng)電壓縮放(AVS)作為第二種有源電源管理技術(shù)，是以芯片制造過程中以及器件運(yùn)行生命周期中產(chǎn)生的差異為基礎(chǔ)的。該技術(shù)與所有處理器都采用相同預(yù)編程OPP的DVFS不同?？梢韵胍姡痛蠖鄶?shù)已經(jīng)成熟的制造工藝而言，芯片的性能在既定頻率要求下要遵循一定的分布情況。部分器件(所謂的“熱”器件)相對于其他器件(所謂的“冷”器件)而言，能以較低的電壓實(shí)現(xiàn)給定的頻率，這就是AVS發(fā)揮作用的原理——處理器感應(yīng)到自身的性能級別，并相應(yīng)調(diào)整供電電壓。專用的片上AVS硬件可實(shí)施反饋環(huán)路，無需處理器干預(yù)即可動態(tài)優(yōu)化電壓電平，以滿足進(jìn)程、溫度以及硅芯片衰減等造成的差異要求(圖1)。圖1給定處理器的典型性能分布。此處的“冷”器件工作在125MHz的頻率時(shí)需要0.94伏特，而“熱”器件在該頻率下只需0.83伏特。自適應(yīng)電壓縮放(AVS)技術(shù)采用反饋環(huán)路相應(yīng)調(diào)節(jié)供電電壓，確保各器件運(yùn)行在特定處理任務(wù)所需的頻率上軟件可在工作中為每個(gè)OPP設(shè)置AVS硬件，而控制算法則通過I2C總線向外部穩(wěn)壓器發(fā)送指令，以逐步降低適當(dāng)穩(wěn)壓器的輸出，直至處理器剛好超過目標(biāo)頻率的要求為止。例如，開發(fā)人員可首先設(shè)計(jì)一個(gè)能滿足所有情況的電壓，在125MHz頻率下為0.95伏特(在圖1中的V1上方)。但是，如果系統(tǒng)中插入了采用AVS技術(shù)的“熱”器件，那么片上反饋機(jī)制就會自動將ARM的電壓降至0.85伏特或更低(圖1中的V2上方)。前兩種有源電源管理技術(shù)可以最小的工作電壓讓器件的某部分工作在理想的速度上。相比之下，第三種方法—?jiǎng)討B(tài)功率切換(DPS)先確定器件何時(shí)可完成當(dāng)前的計(jì)算任務(wù)，如果暫時(shí)不需要，則讓器件進(jìn)入低功耗待機(jī)狀態(tài)(圖2)。例如，處理器在等待DMA傳輸完成過程中會進(jìn)入低功耗狀態(tài)。處理器在喚醒后幾微秒內(nèi)就能返回正常工作狀態(tài)。圖2動態(tài)電源切換(DPS)在給定器件的某部分完成任務(wù)后使其進(jìn)入低功耗狀態(tài)無源電源管理雖然DPS可讓多媒體片上系統(tǒng)(SoC)的一部分進(jìn)入低功耗狀態(tài)，不過在有些情況下，我們可讓整個(gè)器件都進(jìn)入低功耗模式—在沒有應(yīng)用運(yùn)行時(shí)自動或通過用戶請求進(jìn)入低功耗模式。要實(shí)現(xiàn)這一目的，我們可應(yīng)用靜態(tài)漏電管理(SLM)技術(shù)，啟動待機(jī)或器件關(guān)閉模式。這兩種模式一個(gè)關(guān)鍵的不同之處在于：在待機(jī)模式下，器件仍然占用著內(nèi)部存儲器和邏輯，而在器件關(guān)閉模式下，所有系統(tǒng)狀態(tài)都保存于外部存儲器中。利用SLM技術(shù)，喚醒時(shí)間大大快于冷啟動速度，因?yàn)槌绦蛞呀?jīng)載入到了外部存儲器，用戶無需等待操作系統(tǒng)(OS)完全重新啟動。在采用SLM技術(shù)情況下，我們以媒體播放器為例，如果打開十秒鐘后還沒有得到處理指令或用戶輸入，就會關(guān)閉顯示屏進(jìn)入待機(jī)或器件關(guān)閉模式。例如，TI采用ARMCortex-A8內(nèi)核的OMAP35x單芯片處理器器件就支持器件關(guān)閉模式，即器件可自動喚醒的最低功耗模式。除了喚醒域之外，所有電源域均關(guān)閉，耗電的只有喚醒域與I/O漏電流。系統(tǒng)時(shí)鐘關(guān)閉，在此情況下，喚醒域的時(shí)鐘被單獨(dú)設(shè)為32kHz。此外，OMAP35x還可自動向外部穩(wěn)壓器發(fā)送信號，穩(wěn)壓器能夠在深度睡眠狀態(tài)下關(guān)閉。處理器內(nèi)部不保存存儲器或邏輯。在進(jìn)器件關(guān)閉電模式前，系統(tǒng)狀態(tài)存儲在外部存儲器中。經(jīng)后喚醒復(fù)位后，微處理器單元(MPU)會啟動用戶定義的功能，SDRAM控制器配置從高速暫存存儲器(SPM)中恢復(fù)?？蓾M足各種用途的技術(shù)通過結(jié)合采用上述電源管理技術(shù)，我們可實(shí)現(xiàn)多種操作條件下的最佳功耗。如果系統(tǒng)忙于處理播放高分辨率視頻等便攜式播放器任務(wù)，那么可在VDD1上設(shè)置過壓OPP。如果是功耗適中的web瀏覽，則可為VDD1與VDD2設(shè)置額定