20.3.4VHDL語言簡介 - VHDL語言簡介-2

程序中的語法解釋：

IF語句是VHDL中最常用的和最重要的順序條件語句，它是根據(jù)語句中所設(shè)置的一種或者多種條件，有選擇地執(zhí)行指定的順序語句。--IF的語法結(jié)構(gòu)(1)IF條件句THEN

順序語句

ENDIF;

格式（1）如果條件為真，于是（THEN）順序執(zhí)行條件句中所列出來的“順序語句”，直到ENDIF；如果條件為假，則直接跳過順序語句，結(jié)束IF語句的執(zhí)行。這是一種不完整的條件語句，用于產(chǎn)生時(shí)序電路。

格式（2）和格式（1）相比，當(dāng)判斷條件為假時(shí)，并不直接跳離IF語句，而是執(zhí)行ELSE下列出來的一系列的順序語句。所以格式（2）具有條件分支的功能，它可以通過條件來判斷應(yīng)該執(zhí)行哪段順序語句。這是一種完整性語句描述，因?yàn)樗o出了條件句所有可能的條件，因此通常用于產(chǎn)生組合電路。(2)IF條件句THEN

順序語句

ELSE

順序語句

ENDIF;

格式（3）是一種多重IF的嵌套式條件句，可以產(chǎn)生比較豐富的條件描述，既可以產(chǎn)生組合電路，也可以產(chǎn)生數(shù)字電路，或者是二者的混和。使用該語句時(shí)應(yīng)該注意，ENDIF的數(shù)量應(yīng)該與嵌套的條件句數(shù)量一致。(3)IF條件句THENIF條件句THEN......ENDIF;ENDIF;

(4)IF條件句THEN

順序語句

ELSEIF條件句THEN

順序語句

......ELSE

順序語句

ENDIF;ELSEIF來設(shè)定多個(gè)判斷條件，使判斷分支可以超過2個(gè)

顯然，程序的最后一項(xiàng)賦值語句“output<="111"”的執(zhí)行條件（相與條件）是：(din(7)='1')AND(din(6)='1')AND(din(5)='1')AND(din(4)='1')AND(din(3)='1')AND(din(2)='1')AND(din(1)='1')AND(din(0)=‘0')。

數(shù)碼轉(zhuǎn)換電路設(shè)計(jì)

4位二進(jìn)制到十進(jìn)制的真值表LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;--****************************************ENTITYycllIS PORT(A:INUNSIGNED(3DOWNTO0) ; BCD0,BCD1:OUTSTD_LOGIC_VECTOR(3DOWNTO0); SEVEN0,SEVEN1:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDycll;--****************************************--(1)STD_LOGIC_ARITH程序包：包括數(shù)據(jù)類型UNSIGNED的定義及相關(guān)的算術(shù)運(yùn)算符和轉(zhuǎn)換函數(shù)；--(2)STD_LOGIC_UNSIGNED程序包：包括可用于INTEGER和STD_LOGIC型混合運(yùn)算的運(yùn)算符，并定義了STD_LOGIC型到INTEGER型的轉(zhuǎn)換函數(shù)；--(3)UNSIGNED，具有數(shù)值和邏輯類型雙重身份，可以進(jìn)行數(shù)值和邏輯運(yùn)算。ARCHITECTUREbhvOFycllISSIGNALXC:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(A) BEGIN IFA<10THEN BCD1<="0000"; BCD0<=STD_LOGIC_VECTOR(A); SEVEN1<="0111111"; XC<=STD_LOGIC_VECTOR(A);--**************************************** ELSE BCD1<="0001"; BCD0<=STD_LOGIC_VECTOR(A)-10; SEVEN1<="0000110"; XC<=STD_LOGIC_VECTOR(A)-10;--**************************************** ENDIF;ENDPROCESS;

SEVEN_SEGMENT:BLOCK BEGIN SEVEN0<="0111111"WHENXC="0000"ELSE "0000110"WHENXC="0001"ELSE "1011011"WHENXC="0010"ELSE "1001111"WHENXC="0011"ELSE "1100110"WHENXC="0100"ELSE "1101101"WHENXC="0101"ELSE "1111101"WHENXC="0110"ELSE "0000111"WHENXC="0111"ELSE "1111111"WHENXC="1000"ELSE "1101111"WHENXC="1001"ELSE "0000000"; ENDBLOCKSEVEN_SEGMENT;ENDbhv;數(shù)碼轉(zhuǎn)換程序仿真結(jié)果--例18.有問題的4位加法器libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;

ENTITYadderIS PORT(data1,data2:INUNSIGNED(3downto0); Sum:OUTSTD_LOGIC_VECTOR(3downto0); );ENDadder;architectureARCHofadderisBEGIN Sum<=data1+data2;ENDarch;--例4.23

4位加法器的VHDL程序libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;--check4-BITadderfunctionentityADDER1isport(A:inUNSIGNED(3downto0); B:inUNSIGNED(3downto0); Cin:inSTD_LOGIC;BCDout:outSTD_LOGIC_VECTOR(3downto0); Cout:outSTD_LOGIC);endADDER1;ARCHITECTUREARCHofADDER1IS

SIGNALY,C:STD_LOGIC_VECTOR(3downto0);begin Y(0)<=A(0)XORB(0)XORCin; Y(1)<=A(1)XORB(1)XORC(0); Y(2)<=A(2)XORB(2)XORC(1); Y(3)<=A(3)XORB(3)XORC(2); C(0)<=(CinANDA(0))OR(CinANDB(0))OR(A(0)ANDB(0)); C(1)<=(C(0)ANDA(1))OR(C(0)ANDB(1))OR(A(1)ANDB(1)); C(2)<=(C(1)ANDA(2))OR(C(1)ANDB(2))OR(A(2)ANDB(2)); C(3)<=(C(2)ANDA(3))OR(C(2)ANDB(3))OR(A(3)ANDB(3)); BCDout<=Y(3)&Y(2)&Y(1)&Y(0); Cout<=C(3);endARCH;--例4.24全加器的簡化程序ARCHITECTUREARCHofADDER1isSIGNALY,C:STD_LOGIC_VECTOR(3downto0);Y(0)<=A(0)XORB(0)XORCin;C(0)<=(CinANDA(0))OR(CinANDB(0))OR(A(0)ANDB(0));GEN:FORIIN1TO3GENERATEY(I)<=A(I)XORB(I)XORC(I-1);C(I)<=(C(I-1)ANDA(I))OR(C(I-1)ANDB(I))OR(A(I)ANDB(I)); ENDGENERATE; BCDout<=Y(3)&Y(2)&Y(1)&Y(0); Cout<=C(3);endARCH;--例4.251位加法器的設(shè)計(jì)(全加器組件)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYFullAdderISPort( A :IN Std_Logic; B :IN Std_Logic; C :IN Std_Logic; Carry :INOUTStd_Logic; Sum :OUTStd_Logic );EndFullAdder;ARCHITECTUREaOFFullAdderISBeginSum<=AXORBXORC;Carry<=(AandB)or(AandC)or(BandC);enda;--例4.264位加法器的設(shè)計(jì)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYtstisPORT( A:INSTD_LOGIC_VECTOR(3Downto0);

B:INSTD_LOGIC_VECTOR(3Downto0); S:OUTSTD_LOGIC_VECTOR(3Downto0); C:INOUTSTD_LOGIC_VECTOR(4Downto0) );ENDtst;ARCHITECTUREaOFtstIS ComponentFullAdder--組件定義

Port( A :IN Std_Logic; B :IN Std_Logic; C :IN Std_Logic; Carry:INOUTStd_Logic; Sum :OUTStd_Logic ); EndComponent; BEGINC(0)<='0';--組件映像GEN:FORIIN0TO3GENERATEBEGINFullAdderPORTMAP(A(I),B(I),C(I),C(I+1),S(I)); ENDGENERATE;

ENDa;--例4.27

4位加法計(jì)數(shù)器ENTITYCNT4ISPORT(CLK:INBIT;Q:BUFFERINTEGERRANGE15DOWNTO0);END;ARCHITECTUREbhvOFCNT4ISBEGINPROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENQ<=Q+1;ENDIF;ENDPROCESS;ENDbhv;--例4.28

4位計(jì)數(shù)器

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT4ISPORT(CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));END;ARCHITECTUREbhvOFCNT4ISSIGNALQ1:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENQ1<=Q1+1;ENDIF;Q<=Q1;ENDPROCESS;ENDbhv;4位計(jì)數(shù)器的RTL電路--例4.29異步復(fù)位和時(shí)鐘使能的10進(jìn)制計(jì)數(shù)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK,RST,EN:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDCNT10;ARCHITECTUREbehavOFCNT10ISBEGIN

PROCESS(CLK,RST,EN)VARIABLECQI:STD_LOGIC_VECTOR(3DOWNTO0);-變量型BEGINIFRST='1'THENCQI:=(OTHERS=>'0');--計(jì)數(shù)器復(fù)位

ELSIFCLK'EVENTANDCLK='1'THEN--檢測時(shí)鐘上升沿

IFEN='1'THEN--檢測是否允許計(jì)數(shù)

IFCQI<"1001"THENCQI:=CQI+1;--允許計(jì)數(shù)

ELSECQI:=(OTHERS=>'0');--大于9，計(jì)數(shù)值清零

ENDIF;ENDIF;ENDIF;IFCQI="1001"THENCOUT<='1';ELSECOUT<='0';ENDIF;CQ<=CQI;--將計(jì)數(shù)值向端口輸出

ENDPROCESS;ENDbehav;--例4.32雙向移位寄存器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.AL