姜書艷數(shù)字邏輯設計及應用14

1、1,Chapter 6 Combinational Logic Design Practices(組合邏輯設計實踐),Documentation Standard and Circuit Timing (文檔標準和電路定時) Commonly Used MSI Combinational Logic Device (常用的中規(guī)模組合邏輯器件),Digital Logic Design and Application (數(shù)字邏輯設計及應用),2,期中考試,時間： 5月11日 (周六) 19:00-21:00 范圍： 第二章、第三章、第四章、第六章內(nèi)容及有關補充內(nèi)容 集中答疑時間： 5月11日（周

2、六） 8:30-11:30 14:30-17:30 地點：待定,3,實驗課答疑驗收通知,本周四（4月25日） 下午 2:30-5:30 地點：科A335,4,Decoder (譯碼器) Cascading Binary Decoders (譯碼器的級聯(lián)) Realize a Logic Circuit by Using Decoder (利用譯碼器實現(xiàn)邏輯電路),Review of Last Class (內(nèi)容回顧),Digital Logic Design and Application (數(shù)字邏輯設計及應用),5,BCD Decoder ( 二十進制譯碼器 ) Seven-Segment

3、Decoders(七段顯示譯碼器),Review of Last Class (內(nèi)容回顧),Digital Logic Design and Application (數(shù)字邏輯設計及應用),6,用譯碼器和邏輯門實現(xiàn)邏輯函數(shù),F = (X,Y,Z) (1,3,5,6),Digital Logic Design and Application (數(shù)字邏輯設計及應用),A Class Problem ( 每課一題 ),7,6.5 Encoder（編碼器）,1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1

4、 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1,2n Inputs,n Out- puts,Truth Table for a 8-to-3 Encoder,Digital Logic Design and Application (數(shù)字邏輯設計及應用),8,Encoder,N inputs with exactly one of them being set to 1, log2(n) outputs for encoding.,8,4

5、x2,4 x 2 encoder,9,Guarantee: The Inputs are asserted at most one at a time. (前提： 任何時刻只有一個輸入端有效。),6.5 Encoder（編碼器）,Truth Table for a 8-to-3 Encoder,Digital Logic Design and Application (數(shù)字邏輯設計及應用),10,A0 = I1 + I3 + I5 + I7,A1 = I2 + I3 + I6 + I7,A2 = I4 + I5 + I6 + I7,Trouble: When more than One Inp

6、uts are asserted? (問題：當某時刻出現(xiàn)多個輸入有效？),Priority（優(yōu)先級）,6.5 Encoder（編碼器）,Truth Table for a 8-to-3 Encoder,Digital Logic Design and Application (數(shù)字邏輯設計及應用),ABCD = A,11,Priority Encoder(優(yōu)先編碼器),Change I0I7 to H0H7, Make Sure the Inputs are asserted at most one at a time. ( 將 I0I7 轉(zhuǎn)換為 H0H7， 保證其中，任何時刻只有一個有效),

7、Highest-Priority ( 數(shù)大優(yōu)先 ),6.5 Encoder（編碼器）,Digital Logic Design and Application (數(shù)字邏輯設計及應用),12,Priority Encoder(優(yōu)先編碼器),H7 = I7 H6 = I6 I7 H5 = I5 I6 I7 H0 = I0 I1 I2 I6 I7 A2 = H4 + H5 + H6 + H7 A1 = H2 + H3 + H6 + H7 A0 = H1 + H3 + H5 + H7,Highest-Priority ( 數(shù)大優(yōu)先 ),6.5 Encoder（編碼器）,Digital Logic De

8、sign and Application (數(shù)字邏輯設計及應用),13,Priority Encoder(優(yōu)先編碼器),Change I0I7 to H0H7, Make Sure the Inputs are asserted at most one at a time. ( 將 I0I7 轉(zhuǎn)換為 H0H7， 保證其中，任何時刻只有一個有效),Highest-Priority ( 數(shù)大優(yōu)先 ),The IDLE Output is asserted if No Inputs are asserted. (如果沒有輸入有效，則 IDLE 為1 ) IDLE = I0 I1 I6 I7,6.5

9、Encoder（編碼器）,Digital Logic Design and Application (數(shù)字邏輯設計及應用),14,圖6-48 表6-27,The 74x148 Priority Encoder (優(yōu)先級編碼器74x148),Digital Logic Design and Application (數(shù)字邏輯設計及應用),15,2個74x148級聯(lián)為164優(yōu)先編碼器,Digital Logic Design and Application (數(shù)字邏輯設計及應用),16,輸入：由864，需8片74x148 每片優(yōu)先級不同（怎樣實現(xiàn)？） 保證高位無輸入時，次高位才工作 高位芯片的EO

10、端接次高位芯片的EI端,用8-3優(yōu)先編碼器74x148級聯(lián)為64-6優(yōu)先編碼器,片間優(yōu)先級的編碼 利用第9片74x148 每片的GS端接到第9片的輸入端 第9片的輸出作為高3位（RA5RA3）,片內(nèi)優(yōu)先級 片間優(yōu)先級,輸出：6位,8片輸出A2A0 通過或門作為 最終輸出的低3位 RA2RA0,Digital Logic Design and Application (數(shù)字邏輯設計及應用),17,分析判定優(yōu)先級電路：（利用74x148 ） 8個_電平有效輸入I0_LI7_L，_的優(yōu)先級最高 地址輸出A2A0，_電平有效 若輸出AVALID高電平有效，則表示_,A2 A1 A0,AVALID,低,

11、I0_L,至少有一個輸入有效,低,題6.53,Digital Logic Design and Application (數(shù)字邏輯設計及應用),18,設計判定優(yōu)先級電路：（利用74x148 ） 8個輸入I0I7高電平有效，I7優(yōu)先級最高 地址輸出A2A0，高電平有效 如果沒有輸入有效，為111且輸出IDLE有效,題6.52,Digital Logic Design and Application (數(shù)字邏輯設計及應用),19,6.6 Three-State Devices (三態(tài)器件),Three-State Buffer (Three-State Driver) 三態(tài)緩沖器（三態(tài)驅(qū)動器）,F

12、igure 6-51,Three States: Active High(1) ，Active Low (0), Hi-Z (三種狀態(tài)：高電平，低電平，高阻態(tài)）,Digital Logic Design and Application (數(shù)字邏輯設計及應用),20,6.6 Three-State Devices (三態(tài)器件),Three-State Device allow Multiple Sources to Share a Single “Party Line“ As long as Only One device “talk” on the Line at a time （三態(tài)器件允許

13、多個信號源共享單個“同線”， 條件是每次只有一個器件工作） (Figure 6-52),Digital Logic Design and Application (數(shù)字邏輯設計及應用),21,6.6 Three-State Devices (三態(tài)器件),Typical Three-State Devices are Designed So that they go into the Hi-Z state Faster than they come out of the Hi-Z state. （對典型的三態(tài)器件，進入高阻態(tài)比離開高阻態(tài) 的時間快）,Digital Logic Design an

14、d Application (數(shù)字邏輯設計及應用),22,6.6 Three-State Devices (三態(tài)器件),74x245：雙向傳輸數(shù)據(jù)，低電平使能 DIR 決定傳輸方向,74x541：兩個公共使能端，低電平使能， 施密特觸發(fā)輸入，輸出不反相 （圖6-54 6-55）,Standard SSI and MSI Three-State Buffer (標準SSI和MSI三態(tài)緩沖器),（圖6-56 6-57）,Digital Logic Design and Application (數(shù)字邏輯設計及應用),23,沖突（fighting）,利用使能端進行時序控制,三態(tài)器件允許信號共享單個“

15、同線”（party line）,典型的三態(tài)器件，進入高阻態(tài)比離開高阻態(tài)快,Digital Logic Design and Application (數(shù)字邏輯設計及應用),24,Digital Logic Design and Application (數(shù)字邏輯設計及應用),Figure 6-53,25,Notation of Data Bus （數(shù)據(jù)總線的表示法）,圖 655,Digital Logic Design and Application (數(shù)字邏輯設計及應用),26,Transfer Data in Either Directions By Using Three-State T

16、ransceiver (利用三態(tài)緩沖器實現(xiàn)數(shù)據(jù)雙向傳送),Bus Transceiver (總線收發(fā) 圖656),Digital Logic Design and Application (數(shù)字邏輯設計及應用),27,6.7 Multiplexer（多路復用器）,Digital Switch, Multi-Switch, Data Selector (又稱數(shù)據(jù)開關、多路開關、數(shù)據(jù)選擇器) （縮寫：MUX） Under Select Controlling Signals, Select One of the Multi-Inputs to the Output (在選擇控制信號的作用下， 從多

17、個輸入數(shù)據(jù)中選擇其中一個作為輸出。),Digital Logic Design and Application (數(shù)字邏輯設計及應用),28,28,Multiplexer (Mux),Mux: Another popular combinational building block Routes one of its N data inputs to its one output, based on binary value of select inputs,29,29,Multiplexer (Mux),4 input mux needs 2 select inputs to indicat

18、e which input to route through 8 input mux 3 select inputs N inputs log2(N) selects Like a rail yard switch,30,6.7 Multiplexer（多路復用器）,Enable 使能,Select 選擇,數(shù)據(jù)輸出（1位）,Digital Logic Design and Application (數(shù)字邏輯設計及應用),31,31,Mux Internal Design,2,1,i1,i0,s0,0,d,2,1,i1,i0,s0,d,0,i0 (1*i0=i0),i0 (0+i0=i0),2x

19、1 mux,0,32,32,Mux Internal Design,33,A B C,8-Input,1-bit Multiplexer,Digital Logic Design and Application (數(shù)字邏輯設計及應用),34,2-Input,4-bit Multiplexer,Digital Logic Design and Application (數(shù)字邏輯設計及應用),35,雙4選1,A B,Truth Table for a 74x153 4-Input, 2-bit Multiplexer,36,Expanding Multiplexers(擴展多路復用器),Expan

20、ding Bit (擴展位) How to Realize 8-Input, 16-bit Multiplexer? (如何實現(xiàn)8輸入，16位多路復用器？) From 8-Input, 1-bit to 8-Input, 16-bit (由8輸入1位8輸入16位) Need 16 74x151, Each Chip Process 1-bit (需要16片74x151， 每片處理輸入輸出中的1位),Digital Logic Design and Application (數(shù)字邏輯設計及應用),37,Expanding Multiplexers(擴展多路復用器),Expanding Bit (

21、擴展位) Select-Inputs Connect to C,B,A of Each Chip (選擇端連接到每片的C,B,A) Note: The Fanout Ability of Select field (注意：選擇端的扇出能力) （驅(qū)動16個負載）,Digital Logic Design and Application (數(shù)字邏輯設計及應用),38,Expanding Inputs (擴展數(shù)據(jù)輸入端的數(shù)目) How to realize 32-Input, 1-bit Multiplexer (如何實現(xiàn)32輸入，1位多路復用器？) Inputs from 8 to 32, Nee

22、d 4 chips ( 數(shù)據(jù)輸入由832，需4片) How to control Select Inputs - By High bit plus Low bit. ( 如何控制選擇輸入端？ 分為：高位低位),Expanding Multiplexers(擴展多路復用器),39,Expanding Inputs (擴展數(shù)據(jù)輸入端的數(shù)目) 如何實現(xiàn)32輸入，1位多路復用器？ High Bits plus Decoder as Select ( 高位譯碼器進行片選) Low Bits Connect to C,B,A of each Chip ( 低位接到每片的C,B,A) Output Usin

23、g OR Gate ( 4片輸出用或門得最終輸出),Expanding Multiplexers(擴展多路復用器),Figure 6-60,40,Dual 4-to-1 Multiplexer to 8-to-1 Multiplexer (用雙4選1數(shù)據(jù)選擇器構成8選1數(shù)據(jù)選擇器),41,41,Mux Example,City mayor can set four switches up or down, representing his/her vote on each of four proposals, numbered 0, 1, 2, 3 City manager can displ

24、ay any such vote on large green/red LED (light) by setting two switches to represent binary 0, 1, 2, or 3,42,Mux Example,Use 4x1 mux,43,43,Muxes Commonly Together N-bit Mux,Ex: Two 4-bit inputs A (a3 a2 a1 a0), and B (b3 b2 b1 b0) 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B,44,Muxes Commonly Together N-bit Mux,45,45,N-bit Mux Example,Four possible display items Temperature (T), Average miles-per-gallon (A) Instantaneous mpg (I), a