EDA_根據(jù)狀態(tài)圖寫VHDL狀態(tài)機(jī).doc

EDA技術(shù)實(shí)驗(yàn)報(bào)告實(shí)驗(yàn)名稱：例8-4 根據(jù)狀態(tài)圖寫VHDL狀態(tài)機(jī)姓名： 班級： 學(xué)號： 實(shí)驗(yàn)日期：指導(dǎo)教師：一、實(shí)驗(yàn)設(shè)計(jì)要求根據(jù)圖8-14(a)所示的狀態(tài)圖，分別按照圖8-4(b)和圖8-14(c)寫出對應(yīng)結(jié)構(gòu)的VHDL狀態(tài)機(jī)。 二、設(shè)計(jì)原理電路結(jié)構(gòu)圖或原理圖三、實(shí)驗(yàn)程序程序1： VHDL源程序代碼LIBRARY IEEE;-USE IEEE.STD_LOGIC_1164.ALL;ENTITY MOORE1 IS PORT (ina :IN STD_LOGIC_VECTOR(2 DOWNTO 0); CLK,RESET : IN STD_LOGIC; outa : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END MOORE1;ARCHITECTURE behav OF MOORE1 IS TYPE FSM_ST IS (s0,s1,s2,s3); SIGNAL C_ST : FSM_ST ; BEGIN PROCESS(CLK,RESET) BEGIN IF RESET =1 THEN C_ST = s0 ; outa IF ina =101 THEN C_ST = s1 ; outa= 0010 ;END IF; IF ina /=111 THEN C_ST = s1 ; outa IF ina /=000 THEN C_ST = s2 ;outa= 1001 ;END IF; IF ina =000 THEN C_ST = s1 ;outa IF ina /=100 THEN C_ST = s3 ; outa= 1111 ;END IF; if ina =100 THEN C_ST = s2 ; outa= 1111 ;END IF; if ina =011 THEN C_ST = s1 ; outa IF ina =101 THEN outa= 1101;C_ST = s0 ; END IF; if ina /=101THEN outa= 1110 ; C_ST C_ST = s0; OUTA 0); END CASE; END IF; END PROCESS;END behav;四、編譯及仿真結(jié)果選用器件型號cyclone 編譯后使用器件資源情況、引腳配置情況（硬件實(shí)驗(yàn)）：程序仿真波形圖時(shí)序分析結(jié)果仿真結(jié)果顯示：該設(shè)計(jì)是成功的。程序2：REG _COM MEALY型LIBRARY IEEE;- USE IEEE.STD_LOGIC_1164.ALL;ENTITY MEALY IS PORT (ina :IN STD_LOGIC_VECTOR(2 DOWNTO 0); CLK,RESET : IN STD_LOGIC; outa : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END MEALY;ARCHITECTURE behav OF MEALY IS TYPE FSM_ST IS (S0, S1, S2, S3); SIGNAL C_ST, N_ST: FSM_ST ; BEGIN REG : PROCESS (CLK, RESET)BEGINIF RESET = 1 THEN C_ST = S0;ELSIF CLKEVENT AND CLK = 1 THENC_ST IF ina =101 THEN outa= 0010 ; elsIF ina /=111 THEN outa= 1100 ;ELSE outa = 0000;END IF; N_ST IF ina =000 THEN N_ST = S1 ; elsIF ina /=000 THEN N_ST = S2 ;else N_ST = S1 ; END IF; outa if ina =100 THEN N_ST = S2 ; elsif ina =011 THEN N_ST = S1 ; elsIF ina /=100 THEN N_ST = S3 ; END IF; outa IF ina =101 THEN outa= 1101; elsif ina /=101THEN out