簡單計(jì)算機(jī)系統(tǒng)課程設(shè)計(jì)---計(jì)算機(jī)組成實(shí)驗(yàn)-C

1、計(jì)算機(jī)組成實(shí)驗(yàn)c»課程設(shè)計(jì)適用專業(yè)：電子信息類專業(yè)專業(yè)：*班級(jí)：*學(xué)號(hào):*姓名：*指導(dǎo)教師：*實(shí)驗(yàn)學(xué)期：2014-2015 第 1 學(xué)期西南交通大學(xué)信息科學(xué)與技術(shù)學(xué)院簡化計(jì)算機(jī)系統(tǒng)的設(shè)計(jì)一.實(shí)驗(yàn)?zāi)康模和ㄟ^學(xué)習(xí)簡單的指令系統(tǒng)及其各指令的操作流程，用 vhdl語 言實(shí)現(xiàn)簡單的處理器模塊，并通過調(diào)用存儲(chǔ)器模塊，將處理器模塊和存儲(chǔ)器模塊 連接形成簡化的計(jì)算機(jī)系統(tǒng)。2 .實(shí)驗(yàn)內(nèi)容1 .用vhdl語言實(shí)現(xiàn)簡單的處理器模塊。2 .調(diào)用存儲(chǔ)器模塊設(shè)計(jì) 256m6的存儲(chǔ)器模塊。3 .將簡單的處理器模塊和存儲(chǔ)器模塊連接形成簡單的計(jì)算機(jī)系統(tǒng)。4 .將指令序列存入存儲(chǔ)器，然后分析指令執(zhí)行流程。3 .預(yù)習(xí)要求

2、：1、學(xué)習(xí)簡單指令集。2、學(xué)習(xí)各指令的操作流程。4 .實(shí)驗(yàn)報(bào)告1. block 圖h-1i 、疝i.商pran50-r-i oiwnr 一 u. u-c. m-a.>>>>. e_-i .t井尸上而刷一.町1.刈njnjhn-dim 4fli x旃71wr印多由于m ,二>dcdcr f b f圖1 原理圖內(nèi)存文件:atidrh)*1* i+3t*5鈍*f0000000150024oddoqcif00340031ooeoj001 e00410qa1。第1m弘0051002s0c2d16007boddoooie0(000 woqdoa010ocbo240013oof

3、o0000000-0odoa0000000-00000盟0000good(iqodc3cco(joawn(xkh)。叩口*0000oooogoodoaooooqo即叩cob-o00004scoooooooooocoooommogoocooommm0000ooooooooqoqooooqaooooqo-o0000m0000oood(kotlocaocoooaaqodooo-aocdo72ooqqgood0000oqqqqfldo3g3cccocoooqbqooqooooooqoooaooaooq0000cqooqoqo圖2 內(nèi)存文件.mif2.程序設(shè)計(jì)library ieee;use ieee.

4、std_logic_1164.all;package mypack is constant idleconstant loadconstant moveconstant addx constant subp constant andp constant orp constant xorp constant shrp constant shlp constant swap constant jmp constant jz constant read: std_logic_vector(3 downto 0) :="0000": std_logic_vector(3 downt

5、o 0) :="0001": std_logic_vector(3 downto 0) :="0010": std_logic_vector(3 downto 0) :="0011": std_logic_vector(3 downto 0) :="0100": std_logic_vector(3 downto 0) :="0101": std_logic_vector(3 downto 0) :="0110": std_logic_vector(3 downto 0) :

6、="0111": std_logic_vector(3 downto 0) :="1000": std_logic_vector(3 downto 0) :="1001": std_logic_vector(3 downto 0) :="1010": std_logic_vector(3 downto 0) :="1011": std_logic_vector(3 downto 0) :="1100": std_logic_vector(3 downto 0) :="

7、;1101"constant write : std_logic_vector(3 downto 0) :="1110"constant stop : std_logic_vector(3 downto 0) :="1111"end mypack;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.mypack.all;cpu 實(shí)體聲明 entity cpu2 is-清零信號(hào)低有效-時(shí)鐘信號(hào)-讀寫信號(hào) ,'1'為寫-地

8、址線-數(shù)據(jù)輸入線-數(shù)據(jù)輸出線-溢出標(biāo)志port(reset : in std_logic;clock : in std_logic;write_read: out std_logic;m_address: out std_logic_vector(11 downto 0);m_data_in: in std_logic_vector(7 downto 0);m_data_out: out std_logic_vector(7 downto 0); overflow: out std_logic);end cpu2;cpurtl 級(jí)行為描述 architecture rtl of cpu2 is

9、signal ir: std_logic_vector(15 downto 0);-指令寄存器signal mdr: std_logic_vector(7 downto 0);-數(shù)據(jù)寄存器signal mar: std_logic_vector(11 downto 0);-地址寄存器signal status: integer range 0 to 6;-狀態(tài)寄存器beginstatus_change: process(reset, clock, status )beginif reset = '0' then status <= 0 ;elsif clock'e

10、vent and clock = '0' thencase status iswhen 0 =>status <= 1;when 1 =>if ir(15 downto 12) = stop then status <= 1;elsestatus <= 2;end if;when 2 =>case ir(15 downto 12) iswhen read|write|jmp|jz|swap => status <= 3;when others =>status <= 0;end case;when 3 =>if

11、ir(15 downto 12)= s status <= 0;elsestatus <= 4;end if;when 4 =>status <= 5;when 5 =>case ir(15 downto 12) iswhen read|write =>status <= 6;when others =>status <= 0;end case;when others =>status <= 0;end case;elsenull;end if;end process status_change;seq: process(res

12、et,clock)variable pc:std_logic_vector(11 downto 0);-程序計(jì)數(shù)器variable r0,r1,r2,r3: std_logic_vector(7 downto 0);-通用寄存器variable a: std_logic_vector(7 downto 0);- 臨時(shí)寄存器variable temp: std_logic_vector(8 downto 0);- 臨時(shí)變量beginif(reset='0') then- 清零ir <= (others=>'0');pc := (others=>&

13、#39;0');r0 := (others=>'0');r1 := (others=>'0');r2 := (others=>'0');r3 := (others=>'0');a := (others=>'0');mar <= (others=>'0');mdr <= (others=>'0');elsif(clock'event and clock='1') thenoverflow <=

14、'0'case status is-取指令-程序計(jì)數(shù)器加1-狀態(tài) 1when 0=>-狀態(tài) 0ir <= m_data_in & "00000000"pc := pc+1;when 1=>if (ir(15 downto 12) /= stop) thenmar <= pc;end if;case ir(15 downto 12) iswhen load =>r0:= "0000" & ir(11 downto 8);when shlp|shrp =>case ir(11 downto

15、10) is- rx to awhen "00"=> a:= r0;when "01"=> a:= r1;when "10"=> a:= r2;when others => a:= r3;end case;when move|addx|subp|andp|orp|xorp|swap=>case ir(9 downto 8) is- ry to awhen "00"=> a:=r0;when "01"=> a:=r1;when "10"

16、=> a:=r2;when others=> a:=r3;end case;when others => null;end case;when 2=>-狀態(tài) 2case ir(15 downto 12) iswhen addx =>- rx:= rx + a;case ir(11 downto 10) iswhen "00"=>temp := (r0(7) & r0(7 downto 0) + (a(7) & a(7 downto0);r0:=temp(7 downto 0);overflow <= temp(8)

17、xor temp(7);when "01"=>temp :=(r1(7) & r1(7 downto 0) + (a(7) & a(7 downto0);r1:=temp(7 downto 0);overflow <= temp(8) xor temp(7);when "10"=>temp :=(r2(7) & r2(7 downto 0) + (a(7) & a(7 downto0);r2:=temp(7 downto 0);overflow <= temp(8) xor temp(7);when

18、 others=>temp :=(r3(7) & r3(7 downto 0) + (a(7) & a(7 downto0);r3:=temp(7 downto 0);overflow <= temp(8) xor temp(7);end case;when subp =>- rx:= rx - a;case ir(11 downto 10) iswhen "00"=>temp :=(r0(7) & r0(7 downto 0) + not(a(7) & a(7downto 0) + 1;r0:=temp(7 down

19、to 0);overflow <= temp(8) xor temp(7);when "01"=>temp :=(r1(7) & r1(7 downto 0) + not(a(7) & a(7downto 0) + 1;r1:=temp(7 downto 0);overflow <= temp(8) xor temp(7);when "10"=>temp :=(r2(7) & r2(7 downto 0) + not(a(7) & a(7downto 0) + 1;r2:=temp(7 downto

20、 0);overflow <= temp(8) xor temp(7);when others=>temp :=(r3(7) & r3(7 downto 0) + not(a(7) & a(7downto 0) + 1;r3:=temp(7 downto 0);overflow <= temp(8) xor temp(7);end case;when move =>case ir(11 downto 10) iswhen "00"=> r0:= a;when "01"=> r1:= a;when &qu

21、ot;10"=> r2:= a;when others=> r3:= a;end case;when shrp =>case ir(11 downto 10) iswhen "00"=> r0:= '0' & a( 7 downto 1 );when "01"=> r1:= '0' & a( 7 downto 1 );when "10"=> r2:= '0' & a( 7 downto 1 );when others=

22、> r3:= '0' & a( 7 downto 1 );end case;when shlp =>case ir(11 downto 10) iswhen "00"=> r0:= a( 6 downto 0 ) & '0'when "01"=> r1:= a( 6 downto 0 ) & '0'when "10"=> r2:= a( 6 downto 0 ) & '0'when others=> r3

23、:= a( 6 downto 0 ) & '0'end case;when andp =>-rx:= rx and a;case ir(11 downto 10) iswhen "00"=> r0:=r0 and a;when "01"=> r1:=r1 and a;when "10"=> r2:=r2 and a;when others=> r3:=r3 and a;end case;when orp =>-rx:= rx or a;case ir(11 downto 10

24、) iswhen "00"=> r0:=r0 or a;when "01"=> r1:=r1 or a;when "10"=> r2:=r2 or a;when others=> r3:=r3 or a;end case;when xorp =>-rx:= rx xor a;case ir(11 downto 10) iswhen "00"=> r0:=r0 xor a;when "01"=> r1:=r1 xor a;when "10&quo

25、t;=> r2:=r2 xor a;when others=> r3:=r3 xor a;end case;when swap =>case ir(11 downto 8) is when "0100"=> r0:=r1;when "1000"=> r0:=r2;when "1100"=> r0:=r3;when "0001"=> r1:=r0;when "1001"=> r1:=r2;when "1101"=> r1:=

26、r3;when "0010"=> r2:=r0;when "0110"=> r2:=r1;when "1110"=> r2:=r3;when "0111"=> r3:=r1;when "1011"=> r3:=r2;when "0011"=> r3:=r0;when others=> null;end case;when others => null;end case;when 3=>case ir(15 downto 1

27、2) iswhen swap=>case ir(11 downto 10) iswhen "00"=> r0:=a;when "01"=> r1:=a;when "10"=> r2:=a;when others=> r3:=a;end case;when jmp|jz|read|write =>-swap: rx to ry;-狀態(tài)3- swap: a to rxir(7 downto 0)<= m_data_in;pc := pc+1;when others => null;end c

28、ase;when 4=>case ir(15 downto 12) iswhen jmp =>pc := ir(11 downto 0);mar <= ir(11 downto 0);- 取雙字節(jié)指令的后半部分-狀態(tài) 4- 無條件轉(zhuǎn)移指令when jz =>- 條件轉(zhuǎn)移指令if(r0="00000000") thenpc := ir(11 downto 0);mar <= ir(11 downto 0);elsemar <= pc;end if;when read =>mar <= ir(11 downto 0);when w

29、rite =>mar <= ir(11 downto 0);mdr <= r0;when others => null;end case;when 5 =>狀態(tài) 5mar <= pc;when 6 =>狀態(tài) 6case ir(15 downto 12) iswhen read => r0 := m_data_in;when others=> null;end case;end case;end if;end process seq;comb: process (reset, status)beginif (reset = '1

30、9; and status = 5 and ir(15 downto 12)= write ) thenwrite_read <= '1'elsewrite_read <= '0'end if;end process comb;m_address <= mar;m_data_out <= mdr;end rtl;3 .仿真波形圖dl julrlruinrmtlnjwmrnnrmtlnjwmjuuirlrumruumrnnnjmnruumjui:國 回 田 s 回 畫x 國 國 回 國 畫 田.le-er i" gq ii.等1_

31、1 le5t |'i 3sg 冏 le3t i eb-i lkfct： | m.q 11叩u叫 中即12 ,口it |li cpl2 lc st iw.tfh®* lq±c blluit lh.1l.hbl.il wtslicnr，tfl y e-ktl'、一he砧mmik 的 工霓1fuaa皿1 i ra-1： ： 1： ii ?u|-jl :：1. lilt 工 qs? ii： ci：i6 y m3l0：i tj 3011 j7 5 / (ml a： ik曲cl1111：*1&42 0,f ：im ?皿二'»cazi_ ?4至單

32、二加卷萼陜霓霓霓霓霓更寞賽寬話霓冕更奕要奏空運(yùn)更過 燙旭）©欽遼告txt電®t：£：引；jx j_j 二工1;”工冷:工q x 、 x 0 a q .。京 w復(fù)”工邛 工口 jiki is i ct x bo k 1：f k 9431 ：?xi r 年工第 鶴鐘月 工吼 m a 工si a >1000。¥ 必 丫 收:口西廠飛1.工&od力口也re-邛威iye卜mq,比 國置：iiut白g. fc epi£: ihli i'isqq. fid hd配七|訕”川 困 ep1 ihfei： 9 k2 國 t= i nat i

33、'iwi 13 q 叮母：iw5t id 圖生迂：lut ivmle 囪 'pi. iu t iflik 國 apkjjut iitate 困 ibi4f»hi +j i e &i eie ill 1.9njlptntlinrjlimlmmnmtlmjurirtlmrjmruurlrjinnrjlirlruuk鐘 kje工& 工加瓦e；：il»»工e工標(biāo)工通的 x詢 ：q>o工c60 t 第口 x岫口 m esq,era *值_l加工刊 mnim廣加x 心 a_打x u /.-l11 » x.-." ._ *k . se4.迎丫 = t i cum ： srnr ； tbjo tffxo 'i d：i x 990s x 1930 > ttdo y tolo j uto 工 i5x xtcox jjl ： me : oj