VHDL數(shù)字頻率計(jì)的設(shè)計(jì)

1、武漢理工大學(xué)硬件描述語言與數(shù)系統(tǒng)設(shè)計(jì)課程設(shè)計(jì)說明書I目錄1、設(shè)計(jì)原理11.1 FPGA的介紹11.2 VHDL的介紹11.3頻率的測量原理12、分模塊的設(shè)計(jì)12.1 計(jì)數(shù)器的設(shè)計(jì)12.2 頻率計(jì)算32.3 檔位選擇部分42.4 譯碼器模塊的設(shè)計(jì)53、下載測試64、總結(jié)與體會(huì)7參考文獻(xiàn)8附錄91所有的代碼9II摘要隨著時(shí)代的快速發(fā)展，頻率測量的需求在現(xiàn)實(shí)生活中越來越多，也對(duì)頻率測量精度的要求越來越高。傳統(tǒng)的基于電路板的頻率計(jì)在頻率較高時(shí)，由于電路的高頻效應(yīng)，其測量精度會(huì)大大下降。為了解決傳統(tǒng)測量方法在高頻的應(yīng)用問題，產(chǎn)生了基于FPGA的頻率計(jì)。本文主要介紹基于Cyclone V SoC 5CSE

2、MA5F31C6的用VHDL語言編寫的頻率測量系統(tǒng)。關(guān)鍵詞：FPGA，VHDL，頻率計(jì)。武漢理工大學(xué)硬件描述語言與數(shù)系統(tǒng)設(shè)計(jì)課程設(shè)計(jì)說明書1、設(shè)計(jì)原理1.1 FPGA的介紹1.2 VHDL的介紹1.3頻率的測量原理 頻率的即單位時(shí)間內(nèi)發(fā)生的次數(shù)，在電路中，頻率可以解釋為周期信號(hào)正脈沖的個(gè)數(shù)，電子計(jì)數(shù)器測頻有兩種方式：一是直接測頻法，即在單位時(shí)間內(nèi)測量被測信號(hào)的脈沖個(gè)數(shù)；二是間接測頻法，如周期測頻法3。直接測頻法適用于高頻信號(hào)的頻率測量，間接測頻法適用于低頻信號(hào)的頻率測量。本次設(shè)計(jì)采用的頻率測量方法為直接測頻法。 電路主要有兩部分組成，第一部分是頻率測量部分，用于測量出單位時(shí)間內(nèi)周期信號(hào)的正脈沖

3、數(shù)，第二部分是顯示部分，用于對(duì)電路測量的頻率進(jìn)行顯示；在本次設(shè)計(jì)中，用6個(gè)7段共陰數(shù)碼管進(jìn)行顯示。2、分模塊的設(shè)計(jì)2.1 計(jì)數(shù)器的設(shè)計(jì) 計(jì)數(shù)器模塊的主要功能是測量脈沖的數(shù)目，在設(shè)計(jì)中，測量周期信號(hào)的正脈沖的數(shù)目；計(jì)數(shù)器在工作時(shí)，其輸入端來一個(gè)上升沿，計(jì)數(shù)器的值加一，計(jì)數(shù)部分的代碼如下所示：PROCESS(CLK,CLEAR)BEGINIF CLK'EVENT AND CLK='1' THENIF COUNT1_1>8 THEN COUNT1_1<=0;COUNT1_2<=COUNT1_2+1; IF COUNT1_2>8 THEN COUNT1_

4、2<=0;COUNT1_3<=COUNT1_3+1;IF COUNT1_3>8 THEN COUNT1_3<=0;COUNT1_4<=COUNT1_4+1;IF COUNT1_4>8 THEN COUNT1_4<=0;COUNT1_5<=COUNT1_5+1;IF COUNT1_5>8 THEN COUNT1_5<=0;COUNT1_6<=COUNT1_6+1;END IF;END IF;END IF;END IF;ELSE COUNT1_1<=COUNT1_1+1;END IF；END IF;IF SUM>COUN

5、T THENOVERFLOW<='1'ELSE OVERFLOW<='0'END IF;IF CLEAR='0'THENCOUNT1_1<=0;COUNT1_2<=0;COUNT1_3<=0;COUNT1_4<=0;COUNT1_5<=0;COUNT1_6<=0;END IF;END PROCESS;在計(jì)數(shù)器中，共有6個(gè)計(jì)數(shù)變量，均為10進(jìn)制，低位計(jì)數(shù)變量計(jì)滿后向高位進(jìn)位，6個(gè)計(jì)數(shù)變量共同構(gòu)成一個(gè)6位計(jì)數(shù)器，最大計(jì)數(shù)上限為999999。2.2 頻率計(jì)算 頻率的計(jì)算，即指取出在一秒鐘時(shí)間間隔的計(jì)數(shù)器的

6、計(jì)數(shù)值，所得的值即為頻率。頻率計(jì)算部分的代碼如下所示：PROCESS(F_IN_50MHZ,OVERFLOW)VARIABLE SECOND : STD_LOGIC_VECTOR(30 DOWNTO 0);BEGIN IF F_IN_50MHZ'EVENT AND F_IN_50MHZ='1'THEN SECOND:=SECOND+1; IF OVERFLOW='1' THEN COUNT1_1_1<=15; COUNT1_2_1<=15; COUNT1_3_1<=15; COUNT1_4_1<=15; COUNT1_5_1<

7、;=15; COUNT1_6_1<=15; ELSE IF SECOND > 50000000 THEN SECOND:=(OTHERS=>'0'); COUNT1_1_1<=COUNT1_1; COUNT1_2_1<=COUNT1_2; COUNT1_3_1<=COUNT1_3; COUNT1_4_1<=COUNT1_4; COUNT1_5_1<=COUNT1_5; COUNT1_6_1<=COUNT1_6; CLEAR<='0' ELSE CLEAR<='1' END IF;

8、END IF; END IF;END PROCESS;當(dāng)計(jì)算的頻率值大于設(shè)定的量程之后，輸出的頻率值為16進(jìn)制的FFFFFF，即輸出單個(gè)計(jì)數(shù)器的值為15，以提示溢出測量范圍。2.3 檔位選擇部分 設(shè)計(jì)要求檔位分為三檔，分別為010K、0100K、01000K。故需要設(shè)計(jì)檔位選擇部分，檔位選擇部分代碼如下所示：PROCESS(F_SELECT)BEGINIF F_SELECT ="001" THENCOUNT<=10000;LIGHT1<='0'LIGHT2<='0'LIGHT3<='1'ELSIF F_

9、SELECT ="010"THENCOUNT<=100000;LIGHT1<='0'LIGHT2<='1'LIGHT3<='0'ELSIF F_SELECT ="100"THENCOUNT<=1000000;LIGHT1<='1'LIGHT2<='0'LIGHT3<='0'END IF;END PROCESS;當(dāng)選擇輸入為001時(shí)，選擇010K檔，當(dāng)選擇輸入為010時(shí)，選擇0100K檔，當(dāng)選擇輸入為100時(shí)，選擇

10、01000K檔，并亮相應(yīng)檔位的指示燈。2.4 譯碼器模塊的設(shè)計(jì) 由于要設(shè)計(jì)一個(gè)譯碼0F值得譯碼器，共需輸入16個(gè)值，所以要四位輸入端，輸出部分接數(shù)碼管，由于數(shù)碼管是7位的，所以輸出有7位，設(shè)計(jì)的譯碼器模塊代碼如下所示：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DCD_TO_SMG ISPORT(INPUT : IN STD_LOGIC_VECTOR(3 DOWNTO 0);OUTPUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ENTITY;ARCHITECTURE BHV OF DCD_TO_SMG I

11、SBEGINPROCESS(INPUT)BEGINCASE INPUT ISWHEN "0000" => OUTPUT <="0000001"WHEN "0001" => OUTPUT <="1001111"WHEN "0010" => OUTPUT <="0010010"WHEN "0011" => OUTPUT <="0000110"WHEN "0100" =>

12、; OUTPUT <="1001100"WHEN "0101" => OUTPUT <="0100100"WHEN "0110" => OUTPUT <="0100000"WHEN "0111" => OUTPUT <="0001111"WHEN "1000" => OUTPUT <="0000000"WHEN "1001" => OUT

13、PUT <="0000100"WHEN "1010" => OUTPUT <="0001000"WHEN "1011" => OUTPUT <="1100000"WHEN "1100" => OUTPUT <="0110001"WHEN "1101" => OUTPUT <="1000010"WHEN "1110" => OUTPUT &

14、lt;="0110000"WHEN "1111" => OUTPUT <="0111000"WHEN OTHERS => NULL;END CASE;END PROCESS;END ARCHITECTURE;3、下載測試 代碼寫好后用Quartus進(jìn)行編譯，編譯完后用Quartus自帶的下載工具下載到實(shí)驗(yàn)箱中4，然后連接好外接信號(hào)源與FPGA之間的電路，打開信號(hào)源，加載信號(hào)，信號(hào)波形為方波，幅值為3.3Vp-p，頻率從1Hz到1000KHz變化，觀察FPGA上數(shù)碼管的顯示的頻率與信號(hào)源顯示的信號(hào)的頻率是否相等。經(jīng)測試

15、當(dāng)信號(hào)頻率在500KHz以下時(shí)，數(shù)碼管顯示的頻率與信號(hào)源的頻率長時(shí)基本相同，瞬時(shí)相差±1Hz。500KHz以上時(shí) ，數(shù)碼管顯示的數(shù)在信號(hào)源頻率附近浮動(dòng)，為了確定是電路的信號(hào)傳輸問題還是寫的電路的功能的問題，寫了一個(gè)分頻模塊，用分頻模塊的輸出作為頻率計(jì)的輸入。經(jīng)測試，在使用分頻模塊時(shí)，電路在信號(hào)頻率較高時(shí)未出現(xiàn)問題，故電路的邏輯功能正確。分頻模塊的代碼5如下所示：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY fenping IS PORT(CLK_50MHZ : IN ST

16、D_LOGIC;CLK_OUT : BUFFER STD_LOGIC);END ENTITY;ARCHITECTURE BHV OF fenping ISBEGINPROCESS(CLK_50MHZ)VARIABLE Q : STD_LOGIC_VECTOR(25 DOWNTO 0);BEGINIF CLK_50MHZ'EVENT AND CLK_50MHZ='1'THENQ:=Q+1;IF Q>10000 THEN Q:=(OTHERS=>'0');CLK_OUT<=NOT CLK_OUT;END IF;END IF;END PROC

17、ESS;END ARCHITECTURE;4、總結(jié)與體會(huì) 通過這次EDA的課程設(shè)計(jì)，我更加熟練了quartusII14.0軟件的操作，更加熟悉了VHDL語言，增強(qiáng)了利用VHDL與Quartus軟件進(jìn)行設(shè)計(jì)的能力。讓我明白了FPGA是功能強(qiáng)大的電子設(shè)計(jì)自動(dòng)化設(shè)計(jì)平臺(tái)，F(xiàn)PGA可以通過簡單的設(shè)計(jì)實(shí)現(xiàn)很多復(fù)雜的功能，并且FPGA實(shí)現(xiàn)的功能更加穩(wěn)定，保密性好，在未來高速高精度的應(yīng)用場合中必將大有作為。同時(shí)，VHDL語言作為一門超高速集成電路描述語言，其語法嚴(yán)謹(jǐn)，實(shí)用性強(qiáng)，是一門很好的語言工具。在具體設(shè)計(jì)過程中，應(yīng)當(dāng)跟具數(shù)字電路的結(jié)構(gòu)特征寫個(gè)模塊，然后再連接起來，這樣使代碼更加簡明，便于維護(hù)于修改，也便

18、于在大規(guī)模電路中進(jìn)行調(diào)用，使大規(guī)模電路的設(shè)計(jì)更加高效、簡單。參考文獻(xiàn)1 潘松，黃繼業(yè). EDA技術(shù)與VHDL. 北京：清華大學(xué)出版社，2009.09.2 朱娜，張金保，王志強(qiáng). EDA技術(shù)實(shí)用教程.北京：人民郵電出版社，2012.07.3 朱小祥,游家發(fā).EDA技術(shù)與應(yīng)用.北京：清華大學(xué)出版社，2012.07.4 佩里.VHDL編程實(shí)例.北京：電子工業(yè)出版社，2009.06.5 Kenneth L. Short.VHDL大學(xué)實(shí)用教程.北京：電子工業(yè)出版社，2011.09.附錄1 所有的代碼LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD

19、_LOGIC_UNSIGNED.ALL;USE IEEE.numeric_std.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY FREQ ISPORT(F_SELECT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);F_IN : IN STD_LOGIC;F_IN_50MHZ : IN STD_LOGIC;SMG5 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);SMG4 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);SMG3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0

20、);SMG2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);SMG1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);SMG0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);LIGHT1 : OUT STD_LOGIC;LIGHT2 : OUT STD_LOGIC;LIGHT3 : OUT STD_LOGIC;OVERFLOW : BUFFER STD_LOGIC);END ENTITY;ARCHITECTURE BHV OF FREQ ISSIGNAL COUNT : INTEGER RANGE 1000000 DOWNT

21、O 0;SIGNAL SUM : INTEGER RANGE 1000000 DOWNTO 0;SIGNAL COUNT1_1 : INTEGER RANGE 10 DOWNTO 0;SIGNAL COUNT1_2 : INTEGER RANGE 10 DOWNTO 0;SIGNAL COUNT1_3 : INTEGER RANGE 10 DOWNTO 0;SIGNAL COUNT1_4 : INTEGER RANGE 10 DOWNTO 0;SIGNAL COUNT1_5 : INTEGER RANGE 10 DOWNTO 0;SIGNAL COUNT1_6: INTEGER RANGE 1

22、0 DOWNTO 0;SIGNAL COUNT1_1_1 : INTEGER RANGE 15 DOWNTO 0;SIGNAL COUNT1_2_1 : INTEGER RANGE 15 DOWNTO 0;SIGNAL COUNT1_3_1: INTEGER RANGE 15 DOWNTO 0;SIGNAL COUNT1_4_1 : INTEGER RANGE 15 DOWNTO 0;SIGNAL COUNT1_5_1: INTEGER RANGE 15 DOWNTO 0;SIGNAL COUNT1_6_1: INTEGER RANGE 15 DOWNTO 0;SIGNAL CLEAR : S

23、TD_LOGIC;SIGNAL SMG0_BUFF : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SMG1_BUFF : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SMG2_BUFF : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SMG3_BUFF : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SMG4_BUFF : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SMG5_BUFF : STD_LOGIC_VECTOR(3 DOWNTO 0);COM

24、PONENT DCD_TO_SMG ISPORT(INPUT : IN STD_LOGIC_VECTOR(3 DOWNTO 0);OUTPUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END COMPONENT;BEGINPROCESS(F_SELECT)BEGINIF F_SELECT ="001" THENCOUNT<=10000;LIGHT1<='0'LIGHT2<='0'LIGHT3<='1'ELSIF F_SELECT ="010"THENCO

25、UNT<=100000;LIGHT1<='0'LIGHT2<='1'LIGHT3<='0'ELSIF F_SELECT ="100"THENCOUNT<=1000000;LIGHT1<='1'LIGHT2<='0'LIGHT3<='0'END IF;END PROCESS;PROCESS(CLK,CLEAR)BEGINIF CLK'EVENT AND CLK='1' THENIF COUNT1_1>8

26、THEN COUNT1_1<=0;COUNT1_2<=COUNT1_2+1; IF COUNT1_2>8 THEN COUNT1_2<=0;COUNT1_3<=COUNT1_3+1;IF COUNT1_3>8 THEN COUNT1_3<=0;COUNT1_4<=COUNT1_4+1;IF COUNT1_4>8 THEN COUNT1_4<=0;COUNT1_5<=COUNT1_5+1;IF COUNT1_5>8 THEN COUNT1_5<=0;COUNT1_6<=COUNT1_6+1;END IF;END

27、IF;END IF;END IF;ELSE COUNT1_1<=COUNT1_1+1;END IF;END IF;IF SUM>COUNT THENOVERFLOW<='1'ELSE OVERFLOW<='0'END IF;IF CLEAR='0'THENCOUNT1_1<=0;COUNT1_2<=0;COUNT1_3<=0;COUNT1_4<=0;COUNT1_5<=0;COUNT1_6<=0;END IF;END PROCESS;PROCESS(F_IN_50MHZ,OVERFLOW

28、)VARIABLE SECOND : STD_LOGIC_VECTOR(30 DOWNTO 0);BEGIN IF F_IN_50MHZ'EVENT AND F_IN_50MHZ='1'THEN SECOND:=SECOND+1; IF OVERFLOW='1' THEN COUNT1_1_1<=15; COUNT1_2_1<=15; COUNT1_3_1<=15; COUNT1_4_1<=15; COUNT1_5_1<=15; COUNT1_6_1<=15; ELSE IF SECOND > 50000000

29、THEN SECOND:=(OTHERS=>'0'); COUNT1_1_1<=COUNT1_1; COUNT1_2_1<=COUNT1_2; COUNT1_3_1<=COUNT1_3; COUNT1_4_1<=COUNT1_4; COUNT1_5_1<=COUNT1_5; COUNT1_6_1<=COUNT1_6; CLEAR<='0' ELSE CLEAR<='1' END IF; END IF; END IF;END PROCESS;SMG0_BUFF<=CONV_STD_LOGI

30、C_VECTOR(COUNT1_1_1,4);SMG1_BUFF<=CONV_STD_LOGIC_VECTOR(COUNT1_2_1,4);SMG2_BUFF<=CONV_STD_LOGIC_VECTOR(COUNT1_3_1,4);SMG3_BUFF<=CONV_STD_LOGIC_VECTOR(COUNT1_4_1,4);SMG4_BUFF<=CONV_STD_LOGIC_VECTOR(COUNT1_5_1,4);SMG5_BUFF<=CONV_STD_LOGIC_VECTOR(COUNT1_6_1,4);SUM<=COUNT1_1 + COUNT1_2

31、 * 10 +COUNT1_3 * 100 +COUNT1_4 * 1000 +COUNT1_5 * 10000 + COUNT1_6 * 100000;U0 : DCD_TO_SMG PORT MAP(INPUT => SMG0_BUFF,OUTPUT=>SMG0);U1 : DCD_TO_SMG PORT MAP(INPUT => SMG1_BUFF,OUTPUT=>SMG1);U2 : DCD_TO_SMG PORT MAP(INPUT => SMG2_BUFF,OUTPUT=>SMG2);U3 : DCD_TO_SMG PORT MAP(INPUT

32、=> SMG3_BUFF,OUTPUT=>SMG3);U4 : DCD_TO_SMG PORT MAP(INPUT => SMG4_BUFF,OUTPUT=>SMG4);U5 : DCD_TO_SMG PORT MAP(INPUT => SMG5_BUFF,OUTPUT=>SMG5);END ARCHITECTURE;/*/LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DCD_TO_SMG ISPORT(INPUT : IN STD_LOGIC_VECTOR(3 DOWNTO 0);OUTPUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ENTITY;ARCHIT