EDA程序設(shè)計試題及答案講解

1、1 .請畫出下段程序的真值表，并說明該電路的功能。LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY aaa ISPORT( oe,dir :IN STD_LOGIC ;a,b : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0 );END aaa ;ARCHITECTURE ar OF aaa ISBEGINPROCESS(oe , dir )輸入輸出BEGINa1a0x3x2x1x0IF oe='0' THEN a<= "zzzzzzzz"1,”b<= zzzzzzzz ;000

2、001ELSIF oe=T THEN010010IF dir= 0 THEN b<=a;100100ELSIF dir= 1 THEN a<=b;111000ENDIF;END IF ;END PROCESS ;END ar ;功能為：24譯碼器.4分2 .請說明下段程序的功能，寫出真值表，并畫出輸入輸出波形。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY aaa ISPORT( reset,clk: IN STD

3、_LOGIC;q: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);END aaa;ARCHITECTURE bd OF aaa ISBEGINPROCESS(clk,reset)BEGINIF (reset='0') THEN q<="000"ELSIF (clk'event AND clk='1') THENIF (q=5) THEN q<="000"ELSE q<=q+1;END IF;END IF;END PROCESS;END bd;功能為：帶進位借位的4位加/減

4、法器。 .3分輸入輸出波形圖如下： 7分a3.0:一：=. b3.0c3.0一，一 ;:d1. 試用VHDL語言編程實現(xiàn)74LS273芯片的功能。LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY ls273 IS2,1'PORT( clr, clk d q );END ls273;IN std_logic;IN std_logic_vector(7 DOWNTO 0 );OUT std_logic_vector(7 DOWNTO 0 );4'ARCHITECTURElock8 OF ls273 ISBEGINPROCESS ( cl

5、k )BEGINIF (CLR= '0') THENq<= "00000000” ；ELSEIF (clk 'event AND clk= '1') THEN q<=d;ELSEIF ( clk= '0') THEN q<=q;1'1'2, 3'1'END IF;END PROCESS;END lock8;3 .請用VHDL語言編程實現(xiàn)一個狀態(tài)向量發(fā)生器。LIBRARYieee;2,1'USE ieee.std_logic_1164.ALL;ENTITYstasISPOR

6、T(cp, rst:IN std_logic;2'p:BUFFER std_logic_vector(7 DOWNTO 0 ););END stas;ARCHITECTUREBEGINarstasOF stasIS1'PROCESS (cp )1BEGINIF(rst="0")THEN p<= "00000000”；1ELSEIF (cp 'event AND cp= '1')1'WITH p SELECTp<= "10101010”WHEN00000000”；”01010101”WHEN101

7、01010”；”00001111”WHEN01010101” ；”11110000”WHEN00001111” ；”11111111”WHEN11110000” ；”00000000”WHEN11111111” ；”00000000”WHENOTHERS;6'END IFEND PROCESS;END arstas;1.閱讀下段程序，畫出該電路的真值表，并詳細說明該電路的功能LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ab_8 ISPORT( a, b : IN STD_

8、LOGIC_VECTOR(7 DOWNTO 0);ahb, alb, aeb: OUT STD_LOGIC);END ab_8;ARCHITECTURE bd OF ab_8 ISBEGINPROCESS(a,b)alb<='0' aeb<='0' alb<= T; aeb<='0' aeb<='1'BEGINIF a>b THEN ahb<=T;ELSIF a<b THENahb<='0'ELSE ahb<='0' alb<=

9、9;0'END IF;END PROCESS;END bd;1. (1)真值表如下：(5')輸 入輸 出a、bahbalbaeba>b100a<b010a=b001（2）該電路是一個8位兩輸入比較器，（2'）a、b是兩個8位輸入端；（1 '）1”，其余端輸出為“ 0"。（2'）ahb、alb和aeb為比較結(jié)果輸出端，某種比較結(jié)果為真時，相應(yīng)的輸出端為1 .試用VHDL語言編程實現(xiàn)一個2-4譯碼器，其真表如下:輸入端輸出端enselecty0XX1111”1001110”1011101”1101011”1110111”2-4譯碼器碼

10、參考程序如下:(答案不唯一，用 case語句、withselect語句都可以。) LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;(1 ')ENTITY ym24 ISPORT( en : IN STD_LOGIC;select : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)(3');END ym24;ARCHITECTURE bd OF ym24 ISBEGINPROCESS(en)(1')IF (en='1 ') THEN

11、y<=“1110”WHENselect= "00"ELSE“1101”WHENselect ="01"ELSE“1011”WHENselect ="10"ELSE“0111”WHENselect ="11”ELSE(4')A A A 1111 ;ELSE y<="1111”;END PROCESS;END bd;A、B、C、D、E、F都是8位輸入總2 .試用VHDL語言設(shè)計一個六路8位總線復(fù)用器，其中線，Q為8位輸出總線，S為3位選擇端，其功能如下：輸入端輸出端S2S1S0Q7-Q0000Q=A

12、001Q=B010Q=C011Q=D100Q=E101Q=F其它B= "00000000”六路8位總線復(fù)用器 參考程序:（答案不唯一）LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mux6 ISPORT(S : INA,B,C,D,E,F: IN(1')std_logic_vector(2 DOWNTO 0);std_logic_vector(7 DOWNTO 0);Q: OUT std_logic_vector(7 DOWNTO 0);(3')END mux6;ARCHITECTURE bd OF mux6 ISBE

13、GIN(1')PROCESS(S)BEGINCASE S ISWHEN "000"=>Q<=A;WHEN "001"=>Q<=B;WHEN "010"=>Q<=C;WHEN "011"=>Q<=D;WHEN "100"=>Q<=E;WHEN "101"=>Q<=F;WHEN OTHERS=>Q<="00000000"(4')END CASE;END PROC

14、ESS;END bd;(10 分)2、已知三選一電路如圖，判斷下列程序是否有錯誤，如有則指出錯誤所在，并給出完整程序。library ieee;use ieee.std_logic_1164.all;ENTITY MAX isport(a1,a2,a3,s0,s1:in bit;outy:out bit);end max;(2)architecture one of max iscomponent mux21aport(a,b,s:in std_logic;y:out std_logic);end component; (2')signal temp std_logic;_ (2

15、9;)beginu1:mux21a port map(a2,a3,s0,temp);(2)u2:mux21a port map(a1,temp,s1,outy);( 2')end one;1 .已知電路原理圖如下，請用 VHDL語言編寫其程序 冷is:答：library ieee;use ieee.std_logic_1164.all;entity mux21 is port(a,b,s:in bit;y:out bit);end mux21;(4')architecture one of mux21 issingle d,e:bit;begind<=a and (not

16、)s;e<=b and s; y<=d or e;end one;2 .設(shè)計一個帶有異步清零功能的十進制計數(shù)器。計數(shù)器時鐘clk上升沿有效、清零端CLRN、進位輸出co。GLK DQUT £3. S心LRHCO答：library ieee;use ieee.std_logic_1164.all;entity counter10 isport(clk,CLRN:in std_logic;dout:out integer range 0 to 9);end counter10;(5)architecture behav of counter10 IS begin proces

17、s(clk) variable cnt:integer range 0 to 9;(3')begin IF CLRN='0' THEN CNT:=0; ELSIF clk='1'and clk'event thenif cnt=9 thencnt:=0;elsecnt:=cnt+1;end if;end if;dout<=cnt;end process;end behav;(7')3 . 1)用VHDL語言編寫半加器和或門器件的程序，如圖所示：H-RDDEROR2A答：半加器程序：library ieee;use ieee.std_

18、logic_1164.all;entity h_adder isport(a,b:in std_logic;co,so:out std_logic);end h_adder;architecture one of h_adder isbeginso<=not(a xor(not b);co<=a and b;end one;或門程序：library ieee;use ieee.std_logic_1164.all;entity or2a isport(a,b:in std_logic;c:out std_logic);end or2a;architecture one of or2

19、a isbeginc<=a or b;end one;2)在上道題目的基礎(chǔ)上用元件例化語句設(shè)計1位全加器。(2')(3')(2')bin匚堂前匕將Bl I I "I I I B 1 Bl 19 I 1h_ adderhaddera"o3im主程序：library ieee;use ieee.std_logic_1164.all;entity f_adder isport(ain,bin,cin:in std_logic;cout,sum:out std_logic);end entity f_adder;architecture fd1 of

20、f_adder iscomponent h_adderport(a,b:in std_logic;co,so:out std_logic);end component;(5)component or2aport(a,b:in std_logic;c:out std_logic);end component;signal d,e,f:std_logic;beginu1 : h_adder port map(a=>ain,b=>bin,co=>d,so=>e);u2 : h_adder port map(a=>e,b=>cin,co=>f,so=>s

21、um);u3 : or2a port map(d,f,cout);end fd1;(5)1.試用VHDL語言編程實現(xiàn)一個總線開關(guān)，其真值表如下:輸入輸出enselectA0A6B0B6Y0Y60，x，Zzzzzzz”10，A11，B1.總線開關(guān)的參考程序如下：LIBRARY ieee;USE ieee.std_logic_1164.all;(1')ENTITY aaa ISPORT( en, select : IN STD_LOGIC ; A, B : IN STD_LOGIC_VECTOR(6 DOWNTO 0 ); Y : OUT STD_LOGIC_VECTOR(6 DOWNTO

22、 0) END aaa ;(4')ARCHITECTURE ar OF aaa IS BEGIN PROCESS(en, select ) BEGIN IF en= '0' THEN 丫<= "ZZZZZZZ ”； ELSIF en='1' THEN IF select='0' THEN Y<=A; ELSIF select= '1' THEN Y<=B; END IF; END IF ; END PROCESS ; END ar ;(5')2,試用VHDL語言編程實現(xiàn)一個M10計數(shù)器，

23、要求該計數(shù)器有一個時鐘輸入端clk, 一個復(fù)位端rst (低電平復(fù)位)，一個使能端en (高電平時允許計數(shù))，一個“計數(shù)到”輸出端cout, 一個4位二進制 當前計數(shù)值輸出口 q； cout端僅當計數(shù)滿的一個時鐘周期輸出高電平，其余時刻全保持低電平。 2. M10計數(shù)器參考程序：LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;(1')ENTITY aaa IS PORT(clk, rst, en : IN STD_LOGIC; co

24、ut: OUT STD_LOGIC; q: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ); END aaa;(4')ARCHITECTURE bd OF aaa IS BEGIN PROCESS(clk,reset,en) BEGIN IF (rst='0') THEN q<="0000" ELSIF (clk'event AND clk='1') THEN IF en='1' THEN IF (q=9) THEN q<="0000" ELSE q&

25、lt;=q+1; END IF; END IF; END IF; END PROCESS;END bd;(10')3.請用VHDL語言編程，用一個狀態(tài)機模型實現(xiàn)一個七段碼 LED字符發(fā)生器。該電路有一個復(fù)位輸入 端RST, 一個時鐘輸入端CP, 一組七段碼輸出端ag。在LED上七個段的排列位置如圖所示。該電路 的功能為，當復(fù)位輸入端 RST為低電平時，輸出端口輸出全零，無顯示；當 RST為高電平時，在時鐘信號CP的每個上升沿，輸出端依次輪流輸出5個字符“HAPPY”的七段碼（共陰極接法），周而復(fù)始3.用VHDL語言編程實現(xiàn)一個 LED字符發(fā)生器參考程序:LIBRARY ieee;USE

26、 ieee.std_logic_1164.ALL;ENTITY gencIS(1')PORT( rst, cp:IN STD_LOGIC;a,b,c,d,e,f,g: OUT STD_LOGIC );(1')END genc;ARCHITECTURE aa OF genc ISTYPE state IS(s0,s1, s2, s3, s4, s5 );SIGNAL pstate: state;SIGNAL dout: STD_LOGIC_VECTOR(6 DOWNTO 0 );(2')BEGINpr1: PROCESS(cp, rst,) BEGINIF rst=

27、9;0' THEN pstate <=s0;ELSIF (cp'event AND cp='0' ) THEN CASE pstate ISWHEN s0=> pstate <=s1;WHEN s1=> pstate <=s2;WHEN s2=> pstate <=s3;WHEN s3=> pstate <=s4;WHEN s4=> pstate <=s5;WHEN s5=> pstate <=s1;WHEN OTHERS=> pstate <=s0;END CASE;EN

28、D IF;END PROCESS;(5') pr2: PROCESS(pstate)BEGINCASE state ISWHEN s0 => dout<="0000000"-無顯示W(wǎng)HEN s1 =>dout<="0110111"-H”WHEN s2 =>dout<="1110111"-A ”WHEN s3 =>dout<="1100111"-P”WHEN s4 =>dout<="1100111"-P”WHEN s5 =>

29、dout<="0111011"-Y”WHEN OTHERS=> dout<="0000000"- 無顯示(5')END CASE;END PROCESS;a<=dout(6); b<=dout(5); c<=dout(4); d<=dout(3); e<=dout(2); f<=dout;g<=dout(0);END aa;(1')2 .試用VHDL語言和進程語句，編程實現(xiàn)一個3-8譯碼器。該譯碼器的功能為，當使能信號EN為低電平時，輸出端Y7Y0全為高電平(沒有輸出端被選中)

30、當EN為高電平時，每一種ABC的輸入狀態(tài)組合能惟一地選中一路輸出(被選中的端輸出低電平)。真值表如下:輸 入輸出ABCENY7Y6Y5Y4Y3Y2Y1Y00001口111111r o00111111110101011111101101r 1 i111 111011r 1100111101111101111011111110 111011111口1111101111口xxx011111111LIBRARY ieee;OF ls273 IS1'1'std_logic_vector(7 DOWNTO 0 );1'1'WHEN 0001 ”；USE ieee.std_l

31、ogic_1164.ALL;ENTITY ym38 IS PORT( a, b, c, en :INy:OUT);END ym38;ARCHITECTURE arc38 BEGIN PROCESS(en) SIGNAL din : BEGIN din<=a&b&c&en; WITH din SELECT y<= "11111110'2,1'std_logic;std_logic_vector(7 DOWNTO 0 );3'”11111101”WHEN0011”；”11111011”WHEN0101"；”111101

32、11”WHEN0111"；”11101111”WHEN1001"；”11011111”WHEN1011"；”10111111”WHEN1101"；”01111111”WHEN1111"；”11111111"WHEN OTHERS;END PROCESS;END arc38;5'1.試用VHDL語言編程實現(xiàn)一個多路開關(guān)。輸 入輸出S1SoENAoBoA1B1A2B2A3B3XY1 001xxXXXXXXAoBo 1011xXXXXXXXA1B1101XXXXXXXXA2B21 111XXXXXXXXA3B3 Ixx0XXXXXX

33、XXZZ該電路的功能為，當選擇端So和Si為不同狀態(tài)組合時，如果使能信號EN為電平，輸出端X和Y分別與不同的輸入通道A0B0、A1B1、A2B2和A3B3接通并保持，當 EN為低電平時，X、丫輸出為高阻態(tài)。真值表如下：1.多路開關(guān)的參考程序如下:LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mulkey ISPORT(s0,s1,en, a0,b0,a1,b1,a2,b2,a3,b3: IN std_logic;x, y : OUT std_logic_vector(7 DOWNTO 0 ); );END mulkey;ARCHITECTURE

34、 armk OF mulkey ISSIGNAL sel : std_logic_vecter (1 DOWNTO 0 ) BEGIN sel<=s1&s0;PROCESS (en ) BEGIN3'2'ENDIF (en='0')THEN x<='Z，；y<= 'Z'ELSEIF (sel="00") THENx<=a0 ;y<=b0;ELSEIF (sel="01") THENx<=a1 ;y<=b1;ELSEIF (sel="10&q

35、uot;) THENx<=a2;y<=b2;ELSEIF (sel="11")THENx<=a3 ;y<=b3;END IF;END PROCESS;armk;六、寫VHDL1序：（10分）1 .設(shè)計10進制加法計數(shù)器，要求含異步清 0和同步時鐘使能。注意：時鐘信號命名為 CLK,使能信號為EN,清零信號為RST,計數(shù)輸出為CQ。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT (CLK,RST,EN : IN ST

36、D_LOGIC;CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT10;ARCHITECTURE behav OF CNT10 ISBEGINPROCESS(CLK, RST, EN)VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);計數(shù)器異步復(fù)位檢測時鐘上升沿檢測是否允許計數(shù)（同步使能）允許計數(shù)，檢測是否小于9 大于9,計數(shù)值清零計數(shù)大于9,輸出進位信號BEGINIF RST = '1' THEN CQI := (OTHERS =>'0&#

37、39;);-ELSIF CLK'EVENT AND CLK='1' THEN -IF EN = '1' THEN-IF CQI < 9 THEN CQI := CQI + 1;-ELSE CQI := (OTHERS =>'0');-END IF;END IF;END IF;IF CQI = 9 THEN COUT <= '1'-ELSE COUT <= '0'END IF;CQ <= CQI;-將計數(shù)值向端口輸出END PROCESS;END behav;2 .試描述一個帶進

38、位輸入、輸出的 8位全加器端口： A、B為加數(shù)，CIN為進位輸入，S為加和，COUT為進位輸出LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER8 ISPORT (A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);CIN : IN STD_LOGIC;COUT : OUT STD_LOGIC;S : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END ADDER8;ARCHITECTURE ONE OF ADDER8 ISSIGNAL TS : STD_LOGIC_VECTOR (8

39、DOWNTO 0);BEGINTS <= (0' & A) + ('0' & B) + CIN;S <= TS(7 DOWNTO 0);COUT <= TS(8);END ONE;七、VHDLS序設(shè)計：(20分)設(shè)計一數(shù)據(jù)選擇器MUX,其系統(tǒng)模塊圖和功能表如下圖所示。試采用下面三種方式中的兩種來描述該數(shù)據(jù)選擇器MUX的結(jié)構(gòu)體。SEL(1:O)SEL00011011OTHERS(a)用if語句。(b)用case語句。(c)用when else語句。Library ieee;Use ieee.std_logic_1164.all;Entit

40、y mymux isPort ( sel : in std_logic_vector(1 downto 0);Ain, Bin : in std_logic_vector(1 downto 0);Cout : out std_logic_vector(1 downto 0);End mymux;Architecture one of mymux isBeginProcess (sel, ain, bin)BeginIf sel =00" then cout <= ain and bin;Elsif sel =01 " then cout <= ain xor b

41、in;Elsif sel ='10 " then cout <= not ain;Else cout <= not bin;End if;End process;End one;Architecture two of mymux is BeginProcess (sel, ain, bin)BeginCase sel iswhen00"=>cout <=ain and bin;when01 "=>cout <=ain xor bin;when'10"=>cout <=not ain;when

42、 others => cout <= not bin;End case;End process;End two;Architecture three of mymux isBeginCout <= ain and bin when sel = Ain xor bin when sel = Not ain when sel =00 " else01 " else "10" else not bin;End three;設(shè)計一個7段數(shù)碼顯示譯碼器，并逐行進行解釋LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.AL

43、L ;COUTAIN AND BINAIM XOR BINNOT AINNOT BINy選擇信號輸入 數(shù)據(jù)輸入ENTITY DECL7S ISPORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ;ARCHITECTURE one OF DECL7S ISBEGINPROCESS( A )BEGINCASE A ISWHEN "0000" => LED7S <= "0111111"WHEN "0001"

44、 => LED7S <= "0000110"WHEN "0010" => LED7S <= "1011011"WHEN "0011" => LED7S <= "1001111"WHEN "0100" => LED7S <= "1100110"WHEN "0101" => LED7S <= "1101101"WHEN "0110" =>

45、; LED7S <= "1111101"WHEN "0111" => LED7S <= "0000111"WHEN "1000" => LED7S <= "1111111"WHEN "1001" => LED7S <= "1101111"WHEN "1010" => LED7S <= "1110111"WHEN "1011" => LED

46、7S <= "1111100"WHEN "1100" => LED7S <= "0111001"WHEN "1101" => LED7S <= "1011110"WHEN "1110" => LED7S <= "1111001"WHEN "1111" => LED7S <= "1110001"WHEN OTHERS => NULL ;END CASE ;EN

47、D PROCESS ;END ;關(guān)于數(shù)據(jù)選擇器餓設(shè)計1、4選1多路選擇器的IF語句描述 library ieee;use ieee.std_logic_1164.all;entity multiplexers_1 isport (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end multiplexers；architecture archi of multiplexers_1 isbeginprocess (a, b, c, d, s)beginif (s = "

48、00") then o <= a;elsif (s = "01") then o <= b;elsif (s = "10") then o <= c;else o <= d;end if;end process;end archi;2、4選1多路選擇器的CASE語句描述library ieee;use ieee.std_logic_1164.all;entity multiplexers_2 isport (a, b, c, d : in std_logic;s : in std_logic_vector (1 down

49、to 0);o : out std_logic);end multiplexers_2;architecture archi of multiplexers_2 isbeginprocess (a, b, c, d, s)begincase s iswhen "00" => o <= a;when "01" => o <= b;when "10" => o <= c;when others => o <= d;end case;end process;end archi;3、用選擇用條件

50、信號賦值語句描述四選一電路entity mux4 isport(i0, i1, i2, i3 : in std_logic;sel: in std_logic_vector(1 downto 0);q : out std_logic);end mux4;Architecture rtl of mux4 isbeginq<=i0 when sel =“00 ”elsei1 when sel =“01 ”elsei2 when sel =“10”elsei3 when sel =“11”;end rtl;4、信號賦值語句描述四選一電路entity mux4 isport(i0, i1, i2

51、, i3 : in std_logic;sel: in std_logic_vector(1 downto 0);q : out std_logic);end mux4;architecture rtl of mux4 issignal sel : std_logic_vector (1 downto 0); beginwith sel selectq<=i0 when sel =00i1 whensel ="01",i2 whensel ="10",i3 whensel ="11",'X' when other

52、s end rtl;關(guān)于編碼器和譯碼器的設(shè)計1、順序描述語句中if語句之8-3線編碼器library ieee;use ieee.std_logic_1164.all;entity priority_encoder isport ( sel : in std_logic_vector (7 downto 0);code :out std_logic_vector (2 downto 0);end priority_encoder;architecture archi of priority_encoder isBeginProcess (sel)BeginIf sel(0)='1

53、9; then code<="000"Elsif sel(1)='1' then code<="001"Elsif sel(2)='1' then code<="010"Elsif sel(3)='1' then code<="011"Elsif sel(4)='1' then code<="100"Elsif sel(5)='1' then code<="101&quo

54、t;Elsif sel(6)='1' then code<="110"Else code<="111"End if;End process;End archi;2、并發(fā)描述語句之8-3線編碼器library ieee;use ieee.std_logic_1164.all;entity priority_encoder_1 isport ( sel : in std_logic_vector (7 downto 0);code :out std_logic_vector (2 downto 0);end priority_en

55、coder_1;architecture archi of priority_encoder_1 is begincode <= "000" when sel(0) = '1' else"001" when sel(1) = '1' else"010" when sel(2) = '1' else"011" when sel(3) = '1' else"100" when sel(4) = '1' else&q

56、uot;101" when sel(5) = '1' else"110" when sel(6) = '1' else"111" when sel(7) = '1' else"ZZZ"； 1end archi;3、順序描述語句中case語句之3-8譯碼器 library ieee;use ieee.std_logic_1164.all;entity encoder_38 isport ( sel : in std_logic_vector (2 downto 0);en : i

57、n std_logiccode :out std_logic_vector (7 downto 0);end encoder_38;architecture rtl of encoder_38 isbeginprocess (sel,en)beginif (en= ' 1 ' ) thencase sel iswhen "000" =>code <= " 00000001 "when "001" =>code <= " 00000010 "when "010&quo

58、t; =>code <= " 00000100 "when "011" =>code <= " 00001000 "when"100" =>code <=" 00010000"when"101" =>code <=" 00100000"when"110" =>code <=" 01000000"when"111" =>code &l

59、t;=" 10000000"when others =>code <= " 00000000 "end case;else code <= " zzzzzzzz "end if;end process;end rtl;并發(fā)描述語句之3-8譯碼器library ieee;use ieee.std_logic_1164.all;entity encoder_38 isport ( sel : in std_logic_vector (2 downto 0);code :out std_logic_vector (7 do

60、wnto 0);end encoder_38;architecture archi of encoder_38 isSignal sel: std_logic_vector (2 downto 0);BeginWith sel selectcode <= " 00000001" when sel="000", "00000010" when sel="001","00000100 " when sel= "010","00001000 " when sel="011","00010000 " when sel="100","00100000 " when sel="101",