FPGA硬件電子琴

1、 課程設(shè)計(jì)報(bào)告（電子設(shè)計(jì)自動(dòng)化）題 目硬件電子琴學(xué) 院信息科學(xué)與工程學(xué)院專 業(yè)電子科學(xué)與技術(shù)班 級(jí)08級(jí)2班姓 名閆志偉 洪丁達(dá)指導(dǎo)教師吳麗麗2010年6月25日電子琴的設(shè)計(jì) 摘 要：用可編程邏輯器件（PLD）來完成該設(shè)計(jì)。核心是一數(shù)控分頻器，對(duì)輸入的脈沖進(jìn)行分頻，得到每個(gè)音階對(duì)應(yīng)的頻率，由此實(shí)現(xiàn)簡(jiǎn)易電子琴的發(fā)音功能。電子琴可演奏由鍵盤輸入的音階，同時(shí)在數(shù)碼管上顯示對(duì)應(yīng)音節(jié)的頻率。本設(shè)計(jì)基于超高速硬件描述語言VHDL在Altera公司的Cyclone系列的EP2C5T144C8芯片上編程實(shí)現(xiàn)；經(jīng)仿真，硬件測(cè)試和調(diào)試基本能夠達(dá)到技術(shù)指標(biāo)，實(shí)驗(yàn)結(jié)果和仿真結(jié)果基本一致。關(guān)鍵詞：PLD，VHDL，數(shù)控

2、分頻，電子琴 The Design of Electrical Organ Abstract：The design is accomplished with Programmable-Logic-Device (PLD). The core of it is a numerical control frequency divider, which can divide the input pulse into the corresponding frequency to the musical scale, so that it can achieve the sounding functio

3、n of simple electronic organ. The organ can play the musical scale put in with a keyboard . The design is programmed with VHDL and realized in the chip of EP2C5T144C8 Cyclone series. It can basically reach the technique index after simulating, hardware debugging. The experiment result is consonant w

4、ith the simulating result. Keywords：PLD, VHDL, numerical control frequency divider, electrical organ一 系統(tǒng)設(shè)計(jì)1、 設(shè)計(jì)要求 8個(gè)音階，外部時(shí)鐘信號(hào)12 MHz；能同步顯示音階頻率。2 設(shè)計(jì)思路 通過可編程邏輯器件（PLD）和VHDL硬件描述語言來實(shí)現(xiàn)電子琴的基本要求。 設(shè)計(jì)的主體是數(shù)控分頻器，對(duì)輸入的頻率按照與每個(gè)音階對(duì)應(yīng)的分頻系數(shù)進(jìn)行分頻，得到各個(gè)音階對(duì)應(yīng)的頻率分別在蜂鳴器和數(shù)碼管上以聲音和頻率數(shù)值的形式作為輸出。 3、系統(tǒng)組成及工作原理圖1-2-3-1為系統(tǒng)的工作原理框圖。根據(jù)設(shè)計(jì)要求，

5、提供的外部時(shí)鐘信號(hào)為12MHz，所以在本設(shè)計(jì)中需要將其進(jìn)行分頻，以得到所需要的脈沖 。鍵盤編碼器的作用是對(duì)鍵盤按鍵輸入的信號(hào)進(jìn)行檢測(cè)，并且產(chǎn)生相應(yīng)的分頻系數(shù)。 音調(diào)發(fā)生器的主要部分是一個(gè)數(shù)控分頻器，它由一個(gè)初值可預(yù)置的加法計(jì)數(shù)器構(gòu)成，詳細(xì)工作原理將在后文做介紹，當(dāng)它接收到一個(gè)分頻信號(hào)時(shí)，便對(duì)端口的12MHz的輸入時(shí)鐘信號(hào)進(jìn)行分頻，之后由揚(yáng)聲器輸出對(duì)應(yīng)的聲調(diào)。頻率計(jì)的作用是將各個(gè)音階對(duì)應(yīng)的分頻之后的頻率通過數(shù)碼管顯示出來。 分頻置 數(shù)按鍵分頻器12MHZ蜂 鳴 器4位測(cè)頻器數(shù)碼管顯示圖1-2-3-1 工作原理框圖二 單元電路設(shè)計(jì) 1、 頂層模塊的設(shè)計(jì) VHDL采用的是自頂向下的設(shè)計(jì)方式，頂層模塊

6、由音調(diào)發(fā)生器（tonetaba）、數(shù)控分頻器（speaker）和頻率計(jì)（top）三個(gè)模塊組成。圖2-1-1即是頂層設(shè)計(jì)原理圖。由鍵盤輸入的信號(hào)，進(jìn)行編碼，輸出的都是八位二進(jìn)制數(shù)，對(duì)應(yīng)音調(diào)發(fā)生器的輸入。 圖2-1-1 頂層設(shè)計(jì)原理圖 2、 音調(diào)發(fā)生器模塊(tonetaba)的設(shè)計(jì)音調(diào)發(fā)生器的作用是產(chǎn)生獲得音階的分頻預(yù)置值。當(dāng)8位發(fā)聲控制輸入index中的某一位為高電平時(shí)，則對(duì)應(yīng)某一音階的數(shù)值將以端口tone輸出，作為獲得該音階的分頻預(yù)置值，該值作為數(shù)控分頻器的輸入，來對(duì)12MHz的脈沖進(jìn)行分頻，由此得到每個(gè)音階相應(yīng)的頻率，例如輸入index="00000010"，即對(duì)應(yīng)的按鍵

7、是2，產(chǎn)生的分頻系數(shù)便是1702；同時(shí)由high1輸出對(duì)應(yīng)該音階低音顯示。各音階所對(duì)應(yīng)的頻率：低音1低音2低音3低音4低音5低音6低音7261.63Hz293.67Hz329.63Hz349.23Hz391.99Hz440Hz493.88Hz高音1高音2高音3高音4高音5高音6高音71046.5Hz1174.66Hz1318.51Hz1396.92Hz1567.98Hz1760Hz1975.52HZ分頻系數(shù)的計(jì)算：低音1的頻率為261.6Hz，則分頻系數(shù)=1911，同理可求其他頻率的分頻系數(shù)。創(chuàng)新點(diǎn)：利用按鍵8來區(qū)別高低音，當(dāng)按鍵8為高電平時(shí)，按鍵1到7分別表示高音的1到7。當(dāng)按鍵8為低時(shí)，按

8、鍵1到7為低音的1到7 high1<='0'-1911 high1<='0'-1702 high1<='0'-1517 high1<='0'-1432 high1<='0'-1275; high1<='0'-1136 when "01000000" => tone<="01111110100" high1<='0'-1012 when "10000001" => t

9、one<="00111011110" high1<='1'-478 when "10000010" => tone<="00110101001" high1<='1'-426 when "10000100" => tone<="00101111011" high1<='1'-379 when "10001000" => tone<="00101100101&q

10、uot; high1<='1'-358 when "10010000" => tone<="00100111110" high1<='1'-319 when "10100000" => tone<="00100011100" high1<='1'-284 when "11000000" => tone<="00011111101" high1<='1'-

11、253 when others =>null;3 、 數(shù)控分頻模塊（speaker）的設(shè)計(jì)數(shù)控分頻模塊的目的是對(duì)基準(zhǔn)脈沖分頻，得到1,2,3,4,5,6,7七個(gè)音符對(duì)應(yīng)頻率。該模塊的VHDL描述中包含了三個(gè)進(jìn)程。首先對(duì)12MHz的基準(zhǔn)脈沖進(jìn)行12分頻得到1MHz的脈沖，然后按照tone輸入的分頻系數(shù)對(duì)1MHz的脈沖再次分頻，得到的便是所需要的頻率。而第三個(gè)進(jìn)程的作用是在音調(diào)輸出時(shí)再進(jìn)行二分頻，將脈沖展寬，以使揚(yáng)聲器有足夠功率發(fā)音。十二分頻：divideclk : process(clk) variable count4 :std_logic_vector( 3 downto 0); be

12、gin preclk<='0' if count4>11 then preclk<='1' count4:="0000" elsif clk'event and clk='1' then count4:=count4 + 1; end if; end process;按分頻系數(shù)進(jìn)行分頻：genspks: process(preclk,tone) variable count11 :std_logic_vector (10 downto 0); begin if preclk'event and

13、 preclk='1' then count11:=count11+1;fullspks<='0' if count11=tone then fullspks<='1' count11:="00000000000" end if; end if; end process;二分頻使輸出有足夠大的功率發(fā)聲：delayspks: process(fullspks) variable count2 :std_logic; begin if fullspks'event and fullspks ='1

14、9;then count2:=not count2; if count2='1' then spks<='1' else spks<='0' end if; end if; end process;4 、測(cè)頻計(jì)模塊（top）的設(shè)計(jì) 頻率計(jì)的作用是將各個(gè)音階對(duì)應(yīng)的分頻之后的頻率通過數(shù)碼管顯示出來。其外加測(cè)頻控制信號(hào)（clk）為1Hz的標(biāo)準(zhǔn)時(shí)鐘脈沖，基本構(gòu)成為4個(gè)十進(jìn)制加計(jì)數(shù)器和鎖存器。測(cè)頻結(jié)果即為各個(gè)音階對(duì)應(yīng)的頻率，由數(shù)碼管同步顯示。 三 波形仿真1.音調(diào)發(fā)生模塊tonetaba的波形仿真圖： 仿真圖形如上，按鍵由1依次按到7，按鍵8為

15、0，tone依次 輸 出低音1到7的分頻系數(shù)，high1輸出為0，表示此時(shí)輸出為低音。波形仿真圖符合設(shè)計(jì)，說明設(shè)計(jì)正確。2.數(shù)控分頻仿真波形：由于spks的頻率相較于時(shí)鐘頻率12MHz差別較大，因而未能在圖上看到spks的波形變化。四 系統(tǒng)測(cè)試1、測(cè)試使用的儀器 Altera公司的Cyclone系列的EP2C5T144C8芯片康芯教學(xué)實(shí)驗(yàn)箱2、測(cè)試方法 選擇模式5，數(shù)控分頻的基準(zhǔn)頻率用clk0的12MHz輸入，4位測(cè)頻器的輸入頻率用clk2的1Hz輸入。分配好引腳后，將程序燒到板上，依次按下按鍵，蜂鳴器發(fā)出相應(yīng)聲音，同時(shí)數(shù)碼管顯示該音階對(duì)應(yīng)的頻率。3、指標(biāo)測(cè)試和測(cè)試結(jié)果 每個(gè)音階對(duì)應(yīng)著不同的頻

16、率。頻率的大小直接影響著音調(diào)的高低以及失真度。 表4-3-1 頻率測(cè)試音階12 34567頻率(Hz)高 1048117513221397156217651980低263294331352392443495 測(cè)試結(jié)果可以看出，得到的頻率和分頻結(jié)果基本一致，發(fā)音情況良好，音調(diào)準(zhǔn)確。五 結(jié)束語本設(shè)計(jì)利用超高速硬件描述語言VHDL實(shí)現(xiàn)了電子琴 鍵盤輸入發(fā)音的簡(jiǎn)易功能的設(shè)計(jì)，經(jīng)過編程，綜合，仿真，下載，芯片燒制，最終做出成品，測(cè)試情況良好，能夠準(zhǔn)確實(shí)現(xiàn)音階的發(fā)音功能 。 六 參考文獻(xiàn)1 潘松.黃繼業(yè).EDA技術(shù)與VHDL(第2版).北京：清華大學(xué)出版社2009.2 網(wǎng)上相關(guān)資料.七 附錄程序清單1.

17、8音階硬件電子琴頂層文件：library ieee;use ieee.std_logic_1164.all;entity music isport( fclk1,fclk12: in std_logic; o_high:out std_logic;o_dout: buffer std_logic;fdin: in std_logic_vector(7 downto 0);fout: out std_logic_vector( 15 downto 0);end;architecture one of music is component speakerport( clk: in std_logi

18、c;tone: in std_logic_vector(10 downto 0);spks: out std_logic ); end component; component tonetaba port (index :in std_logic_vector (7 downto 0); high1: out std_logic;-gaoyin tone: out std_logic_vector (10 downto 0); end component; component cnt10 port ( clk1,rst,en: in std_logic; cq: out std_logic_v

19、ector(3 downto 0); cout :out std_logic); end component; component testctl PORT ( CLK : IN STD_LOGIC; - 1Hz CNT_EN,RST_CNT,LOAD : OUT STD_LOGIC); END component; component reg16 port ( load : in std_logic; din: in std_logic_vector(15 downto 0); dout: out std_logic_vector(15 downto 0) ); end component;

20、 signal tone1: std_logic_vector( 10 downto 0); signal en1,rst1,ld,d1,d2,d3: std_logic; signal fd: std_logic_vector(15 downto 0); begin u1: tonetaba port map ( index=>fdin, tone=>tone1, high1=>o_high); u2: speaker port map ( clk=>fclk12, tone=>tone1, spks=>o_dout); u3: testctl port

21、map ( clk=>fclk1, cnt_en=>en1, rst_cnt=>rst1, load=>ld); u4: cnt10 port map ( clk1=>o_dout, en=>en1, rst=>rst1, cq=>fd( 3 downto 0), cout=>d1); u5: cnt10 port map ( clk1=>d1, en=>en1, rst=>rst1, cq=>fd( 7 downto 4), cout=>d2); u6: cnt10 port map (clk1=>d2

22、, en=>en1, rst =>rst1, cq=>fd(11 downto 8), cout=>d3); u7: cnt10 port map (clk1=>d3, en=>en1, rst=>rst1, cq=>fd(15 downto 12); u8: reg16 port map (load=>ld, din=>fd, dout=>fout); end; 2.音調(diào)發(fā)生模塊程序：library ieee;use ieee.std_logic_1164.all;entity tonetaba is port (index

23、:in std_logic_vector (7 downto 0); high1: out std_logic;-gaoyin tone: out std_logic_vector (10 downto 0); end; architecture one of tonetaba is begin search: process(index) begin case index is when "01000000" => tone<="01111110100" high1<='0'-1012 when "10000

24、001" => tone<="00111011110" high1<='1'-478 when "10000010" => tone<="00110101001" high1<='1'-426 when "10000100" => tone<="00101111011" high1<='1'-379 when "10001000" => tone<=&q

25、uot;00101100101" high1<='1'-358 when "10010000" => tone<="00100111110" high1<='1'-319 when "10100000" => tone<="00100011100" high1<='1'-284 when "11000000" => tone<="00011111101" high1

26、<='1'-253 when others =>null; end case; end process; end; 3.分頻模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity speaker is port( clk: in std_logic; tone: in std_logic_vector(10 downto 0); spks: out std_logic ); end; architecture one of speaker is signal

27、 fullspks: std_logic; signal preclk : std_logic; begin divideclk : process(clk) variable count4 :std_logic_vector( 3 downto 0); begin preclk<='0' if count4>11 then preclk<='1' count4:="0000" elsif clk'event and clk='1' then count4:=count4 + 1; end if; e

28、nd process; genspks: process(preclk,tone) variable count11 :std_logic_vector (10 downto 0); begin if preclk'event and preclk='1' then count11:=count11+1;fullspks<='0' if count11=tone then fullspks<='1' count11:="00000000000" end if; end if; end process; de

29、layspks: process(fullspks) variable count2 :std_logic; begin if fullspks'event and fullspks ='1'then count2:=not count2; if count2='1' then spks<='1' else spks<='0' end if; end if; end process; end; 3. 4位測(cè)頻器：（1）十進(jìn)制加法器：library ieee;use ieee.std_logic_1164.all

30、;use ieee.std_logic_unsigned.all;entity cnt10 is port ( clk1,rst,en: in std_logic; cq: out std_logic_vector(3 downto 0); cout :out std_logic); end cnt10; architecture behav of cnt10 is begin process(clk1,rst,en) variable cqi:std_logic_vector(3 downto 0); begin if rst ='1' then cqi :=(others =>'0'); elsif clk1'event and clk1='1' then if en='1' then if cqi<10 then cqi :=cqi+1; if cqi=10 then cout<='1'cqi:=(others=>'0