基于Verilog的數(shù)字密碼鎖設(shè)計(jì)

1、word課程設(shè)計(jì)報(bào)告課程設(shè)計(jì)題目：基于Verilog的數(shù)字密碼鎖設(shè)計(jì) 學(xué) 號(hào)：202220070209學(xué)生姓名：尹景興專 業(yè)：通信工程班 級(jí)：1521301指導(dǎo)教師：鐘凱 2022年 1月 12 日目 錄一、課程設(shè)計(jì)內(nèi)容- 1 -二、實(shí)現(xiàn)思路- 1 -1.解鎖過(guò)程- 1 -2.報(bào)警過(guò)程- 1 -3.重置密碼過(guò)程- 1 -三、實(shí)現(xiàn)程序- 2 -四、仿真驗(yàn)證- 5 -1.解鎖過(guò)程- 5 -2.報(bào)警過(guò)程- 6 -3.重置密碼過(guò)程- 8 -五、設(shè)計(jì)心得- 11 -.word一、 課程設(shè)計(jì)內(nèi)容設(shè)計(jì)一個(gè)4位串行數(shù)字密碼鎖，要求如下：1. 開鎖密碼為4位二進(jìn)制，當(dāng)輸入密碼與鎖內(nèi)給定的密碼一致時(shí)，方可開鎖。否

2、那么進(jìn)入“錯(cuò)誤狀態(tài)，發(fā)出報(bào)警信號(hào)。2. 鎖內(nèi)的密碼可調(diào)。3. 串行數(shù)字密碼鎖的報(bào)警，直到按下復(fù)位開關(guān)，才停下。此時(shí)，數(shù)字密碼鎖又自動(dòng)等待下一個(gè)開鎖狀態(tài)。二、 實(shí)現(xiàn)思路1. 解鎖過(guò)程密碼鎖出廠之前預(yù)設(shè)一個(gè)初始密碼，在本課程設(shè)計(jì)中將其預(yù)設(shè)為0101。在密碼鎖上鎖狀態(tài)下,輸入正確密碼，密碼鎖翻開。2. 報(bào)警過(guò)程當(dāng)輸入的密碼與鎖內(nèi)密碼不一致時(shí)，蜂鳴器響起，直到按下取消按鍵，蜂鳴器才停止鳴叫。3. 重置密碼過(guò)程重置密碼時(shí)，需先驗(yàn)證原密碼是否正確。當(dāng)輸入原密碼正確，才可以輸入新密碼，設(shè)置新密碼為鎖內(nèi)密碼。三、 實(shí)現(xiàn)程序module coded_lock(clk,in,set,pause,value1,va

3、lue2,store,bee,status,temp_set,ook); input clk,in,set,pause; output reg bee = 0; output reg status = 0; output reg temp_set = 0; output reg ook = 0; output reg3:0 value1; output reg3:0 value2; output reg3:0 store; reg en = 1; reg2:0 i = 0; reg2:0 j = 0; reg2:0 k = 0; reg2:0 count1 = 0; reg2:0 count2

4、 = 0; reg2:0 count3 = 0; reg3:0 keynum = 4b0101; always (posedge clk) begin if(set = 1) fork temp_set = 1; value1 = 4bxxxx; value2 = 4bxxxx; store = 4bxxxx; i = 0; j = 0; k = 0; ook = 0; count1 = 0; count2 = 0; count3 = 0; join end always (posedge clk) begin if(temp_set = 0) begin case(en,in) 2b11:

5、begin value1i = 1b1; i = i + 1; count1 = count1 + 1;end 2b10: begin value1i = 1b0; i = i + 1; count1 = count1 + 1;end endcase end end always (posedge clk) begin if(count1 = 4) begin if(value1 = keynum) status = 1; else bee = 1; i = 0; count1 = 0; value1 = 4bxxxx; end end always (posedge clk) begin i

6、f(pause = 1) bee = 0; end always (posedge clk) begin if(temp_set = 1 & ook = 0) begin case(en,in) 2b11: begin value2j = 1b1; j = j + 1; count2 = count2 + 1;end 2b10: begin value2j = 1b0; j = j + 1; count2 = count2 + 1;end endcase end end always (posedge clk) begin if(count2 = 4) begin if(value2 = ke

7、ynum) ook = 1; j = 0; count2 = 0; value2 = 4bxxxx; end end always (posedge clk) begin if(ook = 1) begin case(en,in) 2b11: begin storek = 1b1; k = k + 1; count3 = count3 + 1;end 2b10: begin storek = 1b0; k = k + 1; count3 = count3 + 1;end endcase end end always (posedge clk) begin if(count3 = 4) begi

8、n keynum = store; temp_set = 0; ook = 0; k = 0; count3 = 0; end end endmodule 四、 仿真驗(yàn)證1. 解鎖過(guò)程測(cè)試平臺(tái)代碼：timescale 1ns/1nsmodule text; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.o

9、ok(ook),.status(status),.value1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1bx; set = 0; pause = 0; join initial begin #123 in = 1b1; #23 in = 1bx; #45 in = 1b0; #23 in = 1bx; #45 in = 1b1; #23 in = 1bx; #45 in = 1b0; #23 in = 1bx; end

10、 endmodule 如圖，當(dāng)輸入預(yù)設(shè)密碼0101時(shí)，圖中status由0變?yōu)?，表示密碼鎖翻開。2. 報(bào)警過(guò)程測(cè)試平臺(tái)代碼：timescale 1ns/1nsmodule text3; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp3(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.status(status),.value1(va

11、lue1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1bx; set = 0; pause = 0; join initial begin #123 in = 1b1; #23 in = 1bx; #45 in = 1b1; #23 in = 1bx; #45 in = 1b0; #23 in = 1bx; #45 in = 1b0; #23 in = 1bx; #123 pause = 1; #23 pause = 0; end en

12、dmodule如下列圖，當(dāng)輸入密碼0011時(shí)，與鎖內(nèi)密碼不一致，bee由0變?yōu)?，表示蜂鳴器響起。當(dāng)按下pause按鈕時(shí)，bee由1變?yōu)?，表示蜂鳴器停止鳴叫。3. 重置密碼過(guò)程測(cè)試平臺(tái)代碼：timescale 1ns/1nsmodule text2; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp2(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.oo

13、k(ook),.status(status),.value1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1bx; set = 0; pause = 0; join initial begin #123 set = 1; #21 set = 0; #123 in = 1b1; #21 in = 1bx; #45 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx; #45 i

14、n = 1b0; #21 in = 1bx; #125 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx; #45 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx; #125 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx; #45 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx;end endmodule 如下列圖，當(dāng)正確輸入預(yù)設(shè)密碼0101時(shí)，ook由0變?yōu)?，表示可以更改密碼，

15、更改密碼為1010。接著，輸入新密碼1010，status由0變?yōu)?，表示密碼鎖被新密碼翻開，如下列圖。五、 設(shè)計(jì)心得通過(guò)這次課程設(shè)計(jì)，我更深入熟悉了Verilog編程的各個(gè)過(guò)程和原理，并且，成功地做出了一個(gè)產(chǎn)品的簡(jiǎn)化模型極大地挺高了我的學(xué)習(xí)興趣。當(dāng)然，設(shè)計(jì)過(guò)程中也遇到了各種問題和困難，我竭力克服，過(guò)后感覺受益匪淺。我會(huì)再接再厲的。Bingo!.word東華理工大學(xué)課程設(shè)計(jì)評(píng)分表學(xué)生姓名：尹景興 班級(jí)：1521301 學(xué)號(hào)：202220070209課程設(shè)計(jì)題目：基于Verilog的數(shù)字密碼鎖設(shè)計(jì) 工程內(nèi)容總分值實(shí) 評(píng)選題能結(jié)合所學(xué)課程知識(shí)、有一定的能力訓(xùn)練。符合選題要求5人一題10工作量適中，難易度合理10能力水平能熟練應(yīng)用所學(xué)知識(shí)，有一定查閱文獻(xiàn)及運(yùn)用文獻(xiàn)資料能力10理論依據(jù)充分，數(shù)據(jù)準(zhǔn)確，公