多功能數(shù)字鐘課程設(shè)計(jì)VHDL代碼書上程序改

1、library ieee;use ieee.std_logic_1164.all;entity clock isport(clk1hz:in std_logic;-1hz脈沖-clk100:in std_logic;-100hz脈沖-weekclk:in std_logic;-星期調(diào)整脈沖-start_stop:in std_logic;-秒表啟動(dòng)/停止控制-reset:in std_logic;-秒表復(fù)位-adclk:in std_logic;-校時(shí)脈沖-setselect:in std_logic;-調(diào)整位選擇脈沖-mode:in std_logic;-功能選擇脈沖-showdate:in

2、 std_logic;-日期顯示-dis:out std_logic_vector(23 downto 0;-顯示輸出- glisten:out std_logic_vector(5 downto 0;-閃爍指示- weekout:out std_logic_vector(3 downto 0;-星期輸出- qh:out std_logic-整點(diǎn)報(bào)時(shí)-;end clock;architecture arch of clock iscomponent adjustport (adclk: in std_logic;data_in: out std_logic_vector(7 downto 0;

3、end component;component controlport (setclk: in std_logic;setlap: out std_logic_vector (1 downto 0;mode: in std_logic;module: out std_logic_vector (2 downto 0;end component;component weekcounterport (clk: in std_logic;clk2: in std_logic;q: out std_logic_vector(3 downto 0;end component;component stop

4、watchport (clk: in std_logic;reset: in std_logic;start_stop: in std_logic;centsec: out std_logic_vector(7 downto 0;sec: out std_logic_vector(7 downto 0;min: out std_logic_vector(7 downto 0;end component;component h_m_s_countport (clk: in std_logic;set: in std_logic;setlap: in std_logic_vector (1 dow

5、nto 0;d:in std_logic_vector(7 downto 0;sec:out std_logic_vector(7 downto 0;min:out std_logic_vector(7 downto 0;hour:out std_logic_vector(7 downto 0;qh:out std_logic;qc: out std_logic;end component;component y_m_d_countport (clk: in std_logic;set: in std_logic;setlap: in std_logic_vector(1 downto 0;d

6、ata_in: in std_logic_vector(7 downto 0;day: out std_logic_vector (7 downto 0;month: out std_logic_vector (7 downto 0;year: out std_logic_vector (7 downto 0;end component;component displayport (module: in std_logic_vector (2 downto 0;showdate:in std_logic;clk:in std_logic;setlap:in std_logic_vector(1

7、 downto 0;watch: in std_logic_vector (23 downto 0;time:in std_logic_vector(23 downto 0;date:in std_logic_vector(23 downto 0;dis: out std_logic_vector (23 downto 0;glisten:out std_logic_vector(5 downto 0 ;end component;signal data_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:std_logic_vec

8、tor(7 downto 0;signal setlap:std_logic_vector(1 downto 0;signal module:std_logic_vector(2 downto 0;signal qc:std_logic;signal watch,time,date:std_logic_vector(23 downto 0;beginu1:adjust port map(adclk,data_in;u2:control port map(setselect,setlap,mode,module;u3:stopwatch port map(clk100,reset,start_s

9、top,mcentsec,msec,mmin;u4:h_m_s_count port map(clk1hz,module(1,setlap,data_in,ssec,smin,shour,qh,qc;u5:y_m_d_count port map(qc,module(2,setlap,data_in,sdate,smonth,syear;u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten;u7:weekcounter port map(qc,weekclk,weekout;watch<

10、=mmin&msec&mcentsec;time<=shour&smin&ssec;date<=syear&smonth&sdate;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adjust isport (adclk: in std_logic;data_in: out std_logic_vector(7 downto 0;end adjus

11、t;architecture arch of adjust issignal temp2,temp1:std_logic_vector(3 downto 0;beginprocess(adclkbeginif rising_edge(adclkthenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="1001" and temp1="1001"

12、thentemp1<="0000"temp2<="0000"end if;end if;data_in<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control isport (setclk: in std_logic;-調(diào)整脈沖-setlap: out std_logic_vector (1 downto 0;-調(diào)整位選擇脈沖- mode: i

13、n std_logic;-功能選擇脈沖-module: out std_logic_vector (2 downto 0-功能輸出-;end control;architecture arch of control issignal ssetlap:std_logic_vector(1 downto 0;signal s:std_logic_vector(3 downto 0;beginprocess(mode,setclkbeginif mode='1'thenssetlap<="00"elsif rising_edge(setclk thenif

14、ssetlap="10"thenssetlap<="00"elsessetlap<=ssetlap+'1'end if;end if;end process;setlap<=ssetlap;process(modebeginif rising_edge(mode thencase s iswhen"0001"=>s<="0010"when"0010"=>s<="0100"when"0100"=>

15、;s<="1000"when"1000"=>s<="0001"when others=>s<="0010"end case;end if;end process;module<=s(3 downto 1;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter60 isport (clk:

16、 in std_logic;-計(jì)數(shù)脈沖-clr: in std_logic;-復(fù)位-q: out std_logic_vector(7 downto 0;-計(jì)數(shù)值- qc:out std_logic-進(jìn)位輸出-;end counter60;architecture arch of counter60 issignal temp1,temp2:std_logic_vector(3 downto 0; beginprocess(clr,clkbeginif clr='1'thentemp1<="0000"temp2<="0000"

17、elsif rising_edge(clkthenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="0101" and temp1="1001" thentemp1<="0000"temp2<="0000"qc<='1'elseqc<='0'end i

18、f;end if;q<=temp2&temp1;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter99 isport (clk: in std_logic;-100vhz計(jì)數(shù)脈沖-en: in std_logic;-計(jì)數(shù)使能-clr: in std_logic;-復(fù)位-q: out std_logic_vector(7 downto 0;-計(jì)數(shù)值-qc: ou

19、t std_logic-進(jìn)位-;end counter99 ;architecture arch of counter99 issignal temp1,temp2:std_logic_vector(3 downto 0; beginprocess(clr,clkbeginif clr='1'thentemp1<="0000"temp2<="0000"elsif rising_edge(clkthenif en='1' thenif temp1="1001" thentemp2<=te

20、mp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="1001" and temp1="1001" thentemp1<="0000"temp2<="0000"qc<='1'elseqc<='0'end if;end if;end if;q<=temp2&temp1;end process;end arch;library

21、ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity daycounter isport (clk: in std_logic;-計(jì)數(shù)脈沖-set: in std_logic;-調(diào)整信號(hào)-day_in: in std_logic_vector(7 downto 0;-調(diào)整輸入- day_out: out std_logic_vector(7 downto 0;-天輸出- qc: out std_logic;-進(jìn)位-day28: in std_log

22、ic;-該位為1表示該月為28天-day29: in std_logic;-該位為1表示該月為29天-day30: in std_logic; -該位為1表示該月為30天- day31: in std_logic-該位為1表示該月為31天-;end daycounter;architecture arch of daycounter issignal temp1,temp2:std_logic_vector(3 downto 0; signal days:std_logic_vector(7 downto 0;begindays<="00101000" when da

23、y28='1'else"00101001"when day29='1'else"00110000"when day30='1'else "00110001"when day31='1'else"00000000"process(clk,set,day_in,daysbeginif set='1' thentemp2<=day_in(7 downto 4;temp1<=day_in(3 downto 0;elsif risin

24、g_edge(clkthenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2&temp1=days thentemp2<="0000"temp1<="0001"qc<='1'elseqc<='0'end if;end if;end process;day_out<=temp2&a

25、mp;temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity days_control isport (month: in std_logic_vector(7 downto 0;-月份-year2: in std_logic;-年份高位數(shù)字bcd碼最低位-year1: in std_logic_vector(1 downto 0;-年份低位數(shù)字bcd碼末兩位-day28: out std_logic; -該位為1表示該月為28天-day29: out std_logic; -該位為1表示該月為29天-day30: out

26、std_logic; -該位為1表示該月為30天-day31: out std_logic-該位為1表示該月為31天-;end days_control;architecture arch of days_control isbeginprocess(month,year2,year1begincase month iswhen "00000001"=>day28<='0'day29<='0'day30<='0'day31<='1'when "00000010"

27、=>if (year2='0'and year1="00"or (year2='1'and year1="10" then day28<='0'day29<='1'day30<='0'day31<='0'elseday28<='1'day29<='0'day30<='0'day31<='0'end if;when "00000011&

28、quot;=>day28<='0'day29<='0'day30<='0'day31<='1'when "00000100"=>day28<='0'day29<='0'day30<='1'day31<='0'when "00000101"=>day28<='0'day29<='0'day30<='0'

29、;day31<='1'when "00000110"=>day28<='0'day29<='0'day30<='1'day31<='0'when "00000111"=>day28<='0'day29<='0'day30<='0'day31<='1'when "00001000"=>day28<='0'

30、;day29<='0'day30<='0'day31<='1'when "00001001"=>day28<='0'day29<='0'day30<='1'day31<='0'when "00010000"=>day28<='0'day29<='0'day30<='0'day31<='1'when &qu

31、ot;00010001"=>day28<='0'day29<='0'day30<='1'day31<='0'when "00010010"=>day28<='0'day29<='0'day30<='0'day31<='1'when others=>day28<='0'day29<='0'day30<='0'd

32、ay31<='1'end case;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity display isport (module: in std_logic_vector (2 downto 0;-功能選擇-showdate:in std_logic;-顯示日期-clk:in std_logic;-閃爍脈沖-setlap:in std_logic_vector(1 downto 0;-閃爍位選擇- watch: in std_logic_vector (23 downto 0;-秒表

33、計(jì)數(shù)值輸入- time:in std_logic_vector(23 downto 0;-時(shí)分秒計(jì)數(shù)值輸入- date:in std_logic_vector(23 downto 0;-年月日計(jì)數(shù)值輸入- dis: out std_logic_vector (23 downto 0;-顯示輸出-glisten:out std_logic_vector(5 downto 0-閃爍輸出-;end display;architecture arch of display isbeginprocess(module,showdate,watch,time,datebeginif showdate=&#

34、39;1'thendis<=date;elsecase module iswhen"001"=>dis<=watch;when"010"=>dis<=time;when"100"=>dis<=date;when others=>dis<=time;end case;end if;end process;process(clk,module,setlapbeginif module="010"or module="100"thencas

35、e setlap iswhen"00"=>glisten(1 downto 0<=clk&clk;glisten(5 downto 2<="0000"when"01"=>glisten(3 downto 2<=clk&clk;glisten(5 downto 4<="00"glisten(1 downto 0<="00"when"10"=>glisten(5 downto 4<=clk&clk;gl

36、isten(3 downto 0<="0000"when others=>glisten<="000000"end case;else glisten<="000000"end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity dmux isport (set:in std_logic;-調(diào)整信號(hào)-setlap: in std_logic_vector (1 downto 0;-調(diào)整位選擇- d: in std_log

37、ic_vector(7 downto 0;-調(diào)整輸入-set1:out std_logic;set2:out std_logic;set3:out std_logic;q1: out std_logic_vector(7 downto 0;q2: out std_logic_vector(7 downto 0;q3: out std_logic_vector(7 downto 0;end dmux;architecture arch of dmux isbeginprocess(set,setlap,dbeginif set='1' thencase setlap iswhen

38、"00"=>set1<='1'set2<='0'set3<='0'q1<=d;when"01"=>set1<='0'set2<='1'set3<='0'q2<=d;when"10"=>set1<='0'set2<='0'set3<='1'q3<=d;when others=>set1<=

39、9;0'set2<='0'set3<='0'end case;elseset1<='0'set2<='0'set3<='0'end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;entity h_m_s_count isport (clk: in std_logic;-1hz脈沖-set: in std_logic;-調(diào)整信號(hào)-setlap: in std_logic_vector (1 dow

40、nto 0;-調(diào)整位選擇- d:in std_logic_vector(7 downto 0;-調(diào)整輸入-sec:out std_logic_vector(7 downto 0;-秒輸出-min:out std_logic_vector(7 downto 0;-分輸出-hour:out std_logic_vector(7 downto 0;-小時(shí)輸出- qh:out std_logic;-整點(diǎn)報(bào)時(shí)-qc: out std_logic-進(jìn)位-;end h_m_s_count;architecture arch of h_m_s_count iscomponent sec_mincounterp

41、ort (clk: in std_logic;set:in std_logic;d:in std_logic_vector(7 downto 0;q:out std_logic_vector(7 downto 0;qc:out std_logic;end component;component hourcounterport (clk: in std_logic;set:in std_logic;d:in std_logic_vector(7 downto 0;q: out std_logic_vector(7 downto 0;qc:out std_logic;end component;c

42、omponent dmuxport (set:in std_logic;setlap: in std_logic_vector (1 downto 0;d: in std_logic_vector(7 downto 0;set1:out std_logic;set2:out std_logic;set3:out std_logic;q1: out std_logic_vector(7 downto 0;q2: out std_logic_vector(7 downto 0;q3: out std_logic_vector(7 downto 0;end component;signal secs

43、et,minset,hourset: std_logic;signal secin,minin,hourin:std_logic_vector(7 downto 0;signal qcsec,qcmin,qchour: std_logic;beginu1:dmux port map(set,setlap,d,secset,minset,hourset,secin,minin,hourin; u2:sec_mincounter port map(clk,secset,secin,sec,qcsec;u3:sec_mincounter port map(qcsec,minset,minin,min

44、,qcmin;u4:hourcounter port map(qcmin,hourset,hourin,hour,qchour;qh<=qcmin;qc<=qchour;end arch;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity hourcounter isport (clk: in std_logic;-計(jì)數(shù)脈沖-set:in std_logic;-調(diào)整信號(hào)-d:in std_logic_vector(7 downto 0;-調(diào)整時(shí)

45、間-q: out std_logic_vector(7 downto 0;-小時(shí)輸出- qc:out std_logic-進(jìn)位-;end hourcounter;architecture arch of hourcounter issignal temp1,temp2:std_logic_vector(3 downto 0; beginprocess(clk,setbeginif set='1'thentemp2<=d(7 downto 4;temp1<=d(3 downto 0;elsif rising_edge(clk thenif temp1="10

46、01" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="0010" and temp1="0100" thentemp1<="0000"temp2<="0000"qc<='1'elseqc<='0'end if;end if;end process;q<=temp2&temp1

47、;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity monthcounter isclk: in std_logic;-計(jì)數(shù)脈沖-set: in std_logic;-調(diào)整信號(hào)-month_in: in std_logic_vector(7 downto 0;-調(diào)整輸入- month_out: out std_logic_vector(7 downto 0;-月輸出- qc: out std_logic-進(jìn)位-

48、;end monthcounter;architecture arch of monthcounter issignal temp1,temp2:std_logic_vector(3 downto 0;beginprocess(clk,set,month_inbeginif set='1' thentemp2<=month_in(7 downto 4;temp1<=month_in(3 downto 0;elsif rising_edge(clk thenif temp1="1001" thentemp2<=temp2+'1'

49、;temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="0001"and temp1="0010" thentemp2<="0000"temp1<="0001"qc<='1'elseqc<='0'end if;end if;end process;month_out<=temp2&temp1;end arch;library ieee;use ieee.

50、std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sec_mincounter isport (clk: in std_logic;-計(jì)數(shù)脈沖-set:in std_logic;-調(diào)整信號(hào)-d:in std_logic_vector(7 downto 0;-調(diào)整時(shí)間輸入-q:out std_logic_vector(7 downto 0;-分和秒輸出-qc:out std_logic-進(jìn)位-;end sec_mincounter;architecture arch of

51、sec_mincounter issignal temp1,temp2:std_logic_vector(3 downto 0;beginprocess(clk,setbeginif set='1'thentemp2<=d(7 downto 4;temp1<=d(3 downto 0;elsif rising_edge(clk thenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end

52、 if;if temp2="0101" and temp1="1001" thentemp1<="0000"temp2<="0000"qc<='1'elseqc<='0'end if;end if;end process ;q<=temp2&temp1;end arch;library ieee;use ieee.std_logic_1164.all;entity stopwatch isport (clk: in std_logic;-100h

53、z脈沖-reset: in std_logic;-復(fù)位-start_stop: in std_logic;-啟動(dòng)/停止-centsec: out std_logic_vector(7 downto 0;-百分秒輸出,當(dāng)超過60分轉(zhuǎn)為秒- sec: out std_logic_vector(7 downto 0;-秒輸出,當(dāng)超過60分轉(zhuǎn)為分-min: out std_logic_vector(7 downto 0-分輸出,當(dāng)超過60分轉(zhuǎn)為小時(shí)-;end stopwatch;architecture arch of stopwatch iscomponent counter99port (clk:

54、 in std_logic;en: in std_logic;clr: in std_logic;q: out std_logic_vector(7 downto 0;qc: out std_logic;end component;component counter60port (clk: in std_logic;clr: in std_logic;q: out std_logic_vector(7 downto 0;qc: out std_logic;end component;signal qc1,qc2,qc3,qc4,flag:std_logic;signal tcentsec,ts

55、ec,tmin,thour:std_logic_vector(7 downto 0; beginu1:counter99 port map(clk,start_stop,reset,tcentsec,qc1;u2:counter60 port map(qc1,reset,tsec,qc2;u3:counter60 port map(qc2,reset,tmin,qc3;u4:counter60 port map(qc3,reset,thour,qc4;process(qc3beginif rising_edge(qc3thenflag<='1'end if;if flag

56、='1' thencentsec<=tsec;sec<=tmin;min<=thour;elsecentsec<=tcentsec;sec<=tsec;min<=tmin;end if;end process;end arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity weekcounter isport (clk: in std_logic;-天脈沖-clk2: in

57、 std_logic;-外部星期調(diào)整脈沖-q: out std_logic_vector(3 downto 0-星期輸出-; end weekcounter; architecture arch of weekcounter is signal temp:std_logic_vector(3 downto 0; signal cp:std_logic; begin cp<=clk or clk2; process begin wait until rising_edge(cp; if temp="0111" then temp<="0001"

58、 else temp<=temp+'1' end if; q<=temp; end process; end arch; library ieee; use ieee.std_logic_1164.all; entity y_m_d_count is port ( clk: in std_logic;-計(jì)數(shù)脈沖-set: in std_logic;-調(diào)整信號(hào)-setlap: in std_logic_vector(1 downto 0;-調(diào)整位選擇-data_in: in std_logic_vector(7 downto 0;-調(diào)整輸入-day: out std_

59、logic_vector (7 downto 0;-日輸出-month: out std_logic_vector (7 downto 0;-月輸出-year: out std_logic_vector (7 downto 0-年輸出-; end y_m_d_count; architecture arch of y_m_d_count is component daycounter port ( clk: in std_logic; set: in std_logic; day_in: in std_logic_vector(7 downto 0; day_out: out std_logi

60、c_vector(7 downto 0; qc: out std_logic; day28: in std_logic; day29: in std_logic; day30: in std_logic; day31: in std_logic ; end component; component monthcounter port ( clk: in std_logic; set: in std_logic; month_in: in std_logic_vector(7 downto 0; month_out: out std_logic_vector(7 downto 0; qc: out std_logic ; end component; component yearcounter port ( clk: in std_logic; set: in std_logic; year_in: in std_logic_vector(7 downto 0; year_out: out std_logic_vector(7 downto