EDA第五講優(yōu)化和時(shí)序分析

1、EDA 技術(shù)實(shí)用教程技術(shù)實(shí)用教程第第 五五 講講 優(yōu)化和時(shí)序分析優(yōu)化和時(shí)序分析 11.1 資源優(yōu)化資源優(yōu)化 11.1.1 資源共享資源共享 【例【例11-1】LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;USE ieee.std_logic_arith.all;ENTITY multmux IS PORT (A0, A1，B : IN std_logic_vector(3 downto 0); sel : IN std_logic; Result : OUT std_logic_vector(7

2、 downto 0);END multmux;ARCHITECTURE rtl OF multmux ISBEGIN process(A0,A1,B,sel) begin if(sel = 0) then Result = A0 * B; else Result = A1 * B; end if; end process;END rtl; 11.1 資源優(yōu)化資源優(yōu)化 11.1.1 資源共享資源共享 乘法器0乘法器1選擇器01ResultSelA0BA1B圖圖11-1 先乘后選擇的設(shè)計(jì)方法先乘后選擇的設(shè)計(jì)方法RTL結(jié)構(gòu)結(jié)構(gòu) 11.1 資源優(yōu)化資源優(yōu)化 11.1.1 資源共享資源共享 圖圖11-2

3、 先選擇后乘設(shè)計(jì)方法先選擇后乘設(shè)計(jì)方法RTL結(jié)構(gòu)結(jié)構(gòu) 選擇器01乘法器A0SelA1Result11.1 資源優(yōu)化資源優(yōu)化 11.1.1 資源共享資源共享 【例【例11-2】ARCHITECTURE rtl OF muxmult IS signal temp : std_logic_vector(3 downto 0);BEGIN process(A0,A1,B,sel) begin if(sel = 0) then temp = A0; else temp = A1; end if; result = temp * B; end process;END rtl; 11.1 資源優(yōu)化資源優(yōu)化

4、11.1.1 資源共享資源共享 圖圖11-3 資源共享反例資源共享反例 選擇器01ABSR選擇器01ABSR選擇器01ABSR11.1 資源優(yōu)化資源優(yōu)化 11.1.2 邏輯優(yōu)化邏輯優(yōu)化 【例【例11-3】LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;ENTITY mult1 IS PORT(clk : in std_logic; ma : In std_logic_vector(11 downto 0); mc : out std_log

5、ic_vector(23 downto 0);END mult1;ARCHITECTURE rtl OF mult1 IS signal ta，tb : std_logic_vector(11 downto 0);BEGINprocess(clk) begin if(clkevent and clk = 1) then ta = ma; tb = 1; mc = ta * tb; end if;end process;END rtl; 11.1 資源優(yōu)化資源優(yōu)化 11.1.2 邏輯優(yōu)化邏輯優(yōu)化 【例【例11-4】LIBRARY ieee;USE ieee.std_logic_1164.all;

6、use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;ENTITY mult2 IS PORT(clk : in std_logic; ma : In std_logic_vector(11 downto 0); mc : out std_logic_vector(23 downto 0);END mult2;ARCHITECTURE rtl OF mult2 IS signal ta : std_logic_vector(11 downto 0); constant tb : std_logic_vector(11 down

7、to 0) := 1;BEGINprocess(clk) begin if(clkevent and clk = 1) then ta=ma; mc=ta * tb; end if;end process;END rtl; 11.1 資源優(yōu)化資源優(yōu)化 11.1.3 串行化串行化 【例【例11-5】LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;ENTITY pmultadd IS PORT(clk : in std_logic; a0,a1

8、,a2,a3 : in std_logic_vector(7 downto 0); b0,b1,b2,b3 : in std_logic_vector(7 downto 0); yout : out std_logic_vector(15 downto 0);END pmultadd;ARCHITECTURE p_arch OF pmultadd ISBEGINprocess(clk) begin if(clkevent and clk = 1) then yout = (a0*b0)+(a1*b1)+(a2*b2)+(a3*b3); end if;end process; END p_arc

9、h; yout= a0 b0 + a1 b1 + a2 b2 + a3 b3 11.1 資源優(yōu)化資源優(yōu)化 X康芯科技康芯科技11.1.3 串行化串行化 15:0Q15:01:16D15:0+15:015:01:1615:015:0*7:015:07:0*7:015:07:0*7:015:07:0*7:015:07:0yout15:015:0b37:07:0b27:07:0b17:07:0b07:07:0a37:07:0a27:07:0a17:07:0a07:07:0clk圖圖11-4 并行并行乘法并行并行乘法RTL結(jié)構(gòu)（結(jié)構(gòu)（Synplify綜合）綜合） X康芯科技康芯科技【例【例11-6】L

10、IBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;ENTITY smultadd IS PORT(clk， start : in std_logic; a0,a1,a2,a3 : In std_logic_vector(7 downto 0); b0,b1,b2,b3 : In std_logic_vector(7 downto 0); yout : out std_logic_vector(15 downto 0);END smultadd;

11、ARCHITECTURE s_arch OF smultadd IS signal cnt : std_logic_vector(2 downto 0); signal tmpa，tmpb : std_logic_vector(7 downto 0); signal tmp， ytmp : std_logic_vector(15 downto 0); BEGINtmpa = a0 when cnt = 0 else a1 when cnt = 1 else a2 when cnt = 2 else a3 when cnt = 3 else a0;tmpb = b0 when cnt = 0 e

12、lse b1 when cnt = 1 else b2 when cnt = 2 else b3 when cnt = 3 else b0;tmp = tmpa * tmpb;process(clk) begin if(clkevent and clk = 1) then if(start = 1) then cnt = 000; ytmp 0); elsif (cnt4) then cnt = cnt + 1; ytmp = ytmp + tmp; elsif (cnt = 4) then yout = ytmp; end if; end if;end process;END s_arch;

13、 11.2 速度優(yōu)化速度優(yōu)化 11.2.1 流水線設(shè)計(jì)流水線設(shè)計(jì) 圖圖11-5 未使用流水線未使用流水線 11.2 速度優(yōu)化速度優(yōu)化 11.2.1 流水線設(shè)計(jì)流水線設(shè)計(jì) 圖圖11-6 使用流水線使用流水線 11.2 速度優(yōu)化速度優(yōu)化 11.2.1 流水線設(shè)計(jì)流水線設(shè)計(jì) 圖圖11-7 流水線工作圖示流水線工作圖示 X康芯科技康芯科技【例【例11-7】LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;ENTITY adder4 IS PORT(c

14、lk : in std_logic; a0,a1,a2,a3 : in std_logic_vector(7 downto 0); yout : out std_logic_vector(9 downto 0);END adder4;ARCHITECTURE normal_arch OF adder4 IS signal t0,t1,t2,t3 : std_logic_vector(7 downto 0); signal addtmp0,addtmp1 : std_logic_vector(8 downto 0);BEGINprocess(clk) begin if(clkevent and

15、clk=1) then t0 = a0; t1 = a1; t2 = a2; t3 = a3; end if;end process;addtmp0 = 0&t0 + t1;addtmp1 = 0&t2 + t3;process(clk) begin if(clkevent and clk = 1) then yout = 0&addtmp0 + addtmp1; end if;end process; END normal_arch;X康芯科技康芯科技【例【例11-8】LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.

16、std_logic_unsigned.all;use ieee.std_logic_arith.all;ENTITY pipeadd IS PORT(clk : in std_logic; a0,a1,a2,a3 : in std_logic_vector(7 downto 0); yout : out std_logic_vector(9 downto 0);END pipeadd;ARCHITECTURE pipelining_arch OF pipeadd IS signal t0,t1,t2,t3 : std_logic_vector(7 downto 0); signal addtm

17、p0,addtmp1 : std_logic_vector(8 downto 0);BEGINprocess(clk) begin if(clkevent and clk=1) then t0 = a0; t1 = a1; t2 = a2; t3 = a3; end if;end process;process(clk) begin if(clkevent and clk = 1) then addtmp0 = 0&t0 + t1; addtmp1 = 0&t2 + t3;yout T2 T2 Q Q Q Q Q Q 11.2 速度優(yōu)化速度優(yōu)化 11.2.2 寄存器配平寄存器配

18、平 圖圖11-9 寄存器配平的結(jié)構(gòu)寄存器配平的結(jié)構(gòu) 延時(shí)塊（組合邏輯1）QQSETCLRD觸發(fā)器QQSETCLRD觸發(fā)器clkQQSETCLRD觸發(fā)器延時(shí)塊（組合邏輯2）t1t2t1t2 t1 t1t2 t2 Q Q Q Q Q Q 11.2 速度優(yōu)化速度優(yōu)化 11.2.3 關(guān)鍵路徑法關(guān)鍵路徑法 延時(shí)塊Td2延時(shí)最長Td1延時(shí)塊Td3輸入輸出關(guān)鍵路徑 延時(shí)最長 Td1 延時(shí)塊 Td2 延時(shí)塊 Td3 圖圖11-10 關(guān)鍵路徑示意關(guān)鍵路徑示意 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.1 Settings設(shè)置設(shè)置 11.3.2 HDL版本設(shè)置及版本設(shè)置及Analysis &

19、; Synthesis功能功能 11.3.3 Analysis & Synthesis的優(yōu)化設(shè)置的優(yōu)化設(shè)置 11.3.4 適配器適配器Fitter設(shè)置設(shè)置 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 圖圖9-11 布線倍布線倍增器優(yōu)化程度增器優(yōu)化程度指數(shù)選擇指數(shù)選擇 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.5 增量布局布線控制設(shè)置增量布局布線控制設(shè)置 圖圖11-12 反標(biāo)反標(biāo)設(shè)置設(shè)置 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.6 使用使用Design Assistant檢查設(shè)計(jì)可靠性檢查設(shè)計(jì)可靠性 圖圖11-13 Design Assistant設(shè)

20、置設(shè)置 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.7 時(shí)序設(shè)置與分析時(shí)序設(shè)置與分析 圖圖11-14 全編譯前時(shí)序條件設(shè)置（設(shè)置時(shí)鐘信號(hào)全編譯前時(shí)序條件設(shè)置（設(shè)置時(shí)鐘信號(hào)CLK不低于不低于130MHz） 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.7 時(shí)序設(shè)置與分析時(shí)序設(shè)置與分析 圖圖11-15 由由Timing Wizard窗口設(shè)置時(shí)序條件窗口設(shè)置時(shí)序條件 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.8 查看時(shí)序分析結(jié)果查看時(shí)序分析結(jié)果 圖圖11-16 時(shí)序分析報(bào)告窗時(shí)序分析報(bào)告窗 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.8 查看時(shí)

21、序分析結(jié)果查看時(shí)序分析結(jié)果 圖圖11-17 Timing Analyzer Tool 項(xiàng)進(jìn)入的時(shí)序分析報(bào)告窗項(xiàng)進(jìn)入的時(shí)序分析報(bào)告窗 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.9 適配優(yōu)化設(shè)置示例適配優(yōu)化設(shè)置示例 圖圖11-18 未用乘積項(xiàng)前的編譯報(bào)告未用乘積項(xiàng)前的編譯報(bào)告 【例【例11-9】 用用CASE語句設(shè)計(jì)的正弦信號(hào)發(fā)生器語句設(shè)計(jì)的正弦信號(hào)發(fā)生器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SINGT IS PORT ( CLK : IN STD_LOGIC;

22、 DOUT : OUT INTEGER RANGE 255 DOWNTO 0 );END;ARCHITECTURE DACC OF SINGT IS SIGNAL Q : INTEGER RANGE 63 DOWNTO 0 ; SIGNAL D : INTEGER RANGE 255 DOWNTO 0 ;BEGINPROCESS(CLK) BEGIN IF CLKEVENT AND CLK = 1 THENIF Q 63 THEN Q = Q + 1; ELSE Q D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D

23、D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D NULL ;END CASE; END PROCESS; DOUT = D ; END; 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.9 適配優(yōu)化設(shè)置示例適配優(yōu)化設(shè)置示例 圖圖11-19 針對(duì)工程選擇針對(duì)工程選擇Locate in Assignment Editor 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.9 適配優(yōu)化設(shè)置示例適配優(yōu)化設(shè)置示例 圖圖11-20 選用乘積項(xiàng)邏輯優(yōu)化選用乘積項(xiàng)邏輯優(yōu)化 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)

24、序分析 11.3.9 適配優(yōu)化設(shè)置示例適配優(yōu)化設(shè)置示例 圖圖11-21在在floorplan中可以看到使用了中可以看到使用了32個(gè)個(gè)ESB 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.9 適配優(yōu)化設(shè)置示例適配優(yōu)化設(shè)置示例 圖圖11-22使用了乘積項(xiàng)的編譯報(bào)告使用了乘積項(xiàng)的編譯報(bào)告 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.10 Slow Slew Rate設(shè)置設(shè)置 圖圖11-23 Slow Slew Rate選擇選擇 11.3 優(yōu)化設(shè)置與時(shí)序分析優(yōu)化設(shè)置與時(shí)序分析 11.3.11 LogicLock優(yōu)化技術(shù)優(yōu)化技術(shù) 大規(guī)模系統(tǒng)開發(fā)中，應(yīng)用邏輯鎖定技術(shù)可以優(yōu)化大規(guī)模系統(tǒng)開發(fā)中，應(yīng)用邏輯鎖定技術(shù)可以優(yōu)化設(shè)計(jì)