verilog 設(shè)計可綜合的狀態(tài)機的指導(dǎo)原則

1、圖圖1 . 時鐘同步的狀態(tài)機結(jié)構(gòu)時鐘同步的狀態(tài)機結(jié)構(gòu) (Mealy 狀態(tài)機狀態(tài)機)下一狀態(tài)下一狀態(tài)的邏輯的邏輯 F F輸出邏輯輸出邏輯 G G狀態(tài)狀態(tài)寄存器寄存器 clk 輸入Moor Moor 狀態(tài)機狀態(tài)機下一個狀態(tài)下一個狀態(tài) = F(= F(當(dāng)前狀態(tài)，輸入信號當(dāng)前狀態(tài)，輸入信號) )輸出信號輸出信號 = G(= G(當(dāng)前狀態(tài)當(dāng)前狀態(tài)) )；下一狀下一狀態(tài)的邏態(tài)的邏輯輯 F F輸出邏輯輸出邏輯 G G狀態(tài)狀態(tài)寄存器寄存器圖2. 時鐘同步的狀態(tài)機結(jié)構(gòu) (Moor狀態(tài)機)有限狀態(tài)機的圖形表示有限狀態(tài)機的圖形表示 圖形表示：狀態(tài)、轉(zhuǎn)移、條件和邏輯開關(guān)圖形表示：狀態(tài)、轉(zhuǎn)移、條件和邏輯開關(guān)圖圖3.4

2、3.4 狀態(tài)轉(zhuǎn)移圖狀態(tài)轉(zhuǎn)移圖Idle Start Stop Clear A/K1=0 !A A/K2=1 !Reset /K2=0 K1=0!Reset /K2=0 K1=0 （!Reset |!A ）/ K2=0 K1=1!Reset /K2=0 K1=01.定義模塊名和輸入輸出端口；定義模塊名和輸入輸出端口；2.定義輸入、輸出變量或寄存器；定義輸入、輸出變量或寄存器；3.定義時鐘和復(fù)位信號；定義時鐘和復(fù)位信號；4.定義狀態(tài)變量和狀態(tài)寄存器；定義狀態(tài)變量和狀態(tài)寄存器；5.用時鐘沿觸發(fā)的用時鐘沿觸發(fā)的always塊表示狀態(tài)轉(zhuǎn)移過程；塊表示狀態(tài)轉(zhuǎn)移過程；6.在復(fù)位信號有效時給狀態(tài)寄存器賦初始值；

3、在復(fù)位信號有效時給狀態(tài)寄存器賦初始值；7.描述狀態(tài)的轉(zhuǎn)換過程：符合條件，從一個狀態(tài)到描述狀態(tài)的轉(zhuǎn)換過程：符合條件，從一個狀態(tài)到另外一個狀態(tài)，否則留在原狀態(tài)；另外一個狀態(tài)，否則留在原狀態(tài)；8.驗證狀態(tài)轉(zhuǎn)移的正確性，必須完整和全面。驗證狀態(tài)轉(zhuǎn)移的正確性，必須完整和全面。ClockResetAK2K1input Clock, Reset A;output K2, K1;信號說明，引腳信號說明，引腳變量和常量變量和常量圖圖1 . 時鐘同步的狀態(tài)機結(jié)構(gòu)時鐘同步的狀態(tài)機結(jié)構(gòu) (Mealy 狀態(tài)機狀態(tài)機)下一狀態(tài)下一狀態(tài)的邏輯的邏輯 F F輸出邏輯輸出邏輯 G G狀態(tài)狀態(tài)寄存器寄存器 clk 輸入信號變量、

4、常量聲明 每一個時鐘沿產(chǎn)生一次可能的狀態(tài)變化 state 產(chǎn)生下一狀態(tài)的組合邏輯 nextstate 產(chǎn)生輸出K1的組合邏輯ResetAclkStopClear010010always20always30K10K20ClockResetAK2K1statemodule mux2(clk,ina,out);input clk,ina;output out;reg out;reg 1:0 state;parameter s0 = 2b00,s1 =2b01,s2 =2b10,s3=2b11;always (posedge clk)beginstate=s0;out =0;case(state)s0

5、:begin state=(ina=1)?s1:s0; out=0; ends1: begin state=(ina=1)?s2:s0; out=0; ends2: begin state=(ina=1)?s3:s0; out=0; ends3: begin state=(ina=1)?s3:s0; out=1; end endcaseendendmodule just_launchedis_landedabort_missionall_systems_goclklaunch_shuttleland_shuttlestart_countdownstart_trip_metercntjust_l

6、aunchedis_landedabort_mission/launch_shuttle=1/land_shuttle=1/start_trip_meter=1HOLDSEQUENCELANDLAUNCHON_MISSIONcnt=0/start_countdown=1all_systems_gomodule statemachine ( launch_shuttle, land_shuttle, start_countdown, start_trip_meter, clk, all_systems_go, just_launched, is_landed, cnt, abort_missio

7、n); output launch_shuttle, land_shuttle, start_countdown； output start_trip_meter; input clk, just_launched, is_landed, abort_mission, all_systems_go; input 3:0 cnt; reg launch_shuttle, land_shuttle, start_countdown, start_trip_meter;/設(shè)置獨熱碼狀態(tài)的參數(shù) parameter HOLD=5b00001, SEQUENCE=5b00010, LAUNCH=5b001

8、00, ON_MISSION=5b01000， LAND=5b10000; reg 4:0 state;always (negedge clk or posedge abort_mission) begin /檢查異步reset的值,即abort_mission的值 if(abort_mission) launch_shuttle, land_shuttle, start_trip_meter, start_countdown= 4b0000; state=LAND; else begin /* 主狀態(tài)機，狀態(tài)變量state */ case ( state ) HOLD: if (all_sy

9、stems_go) begin state = SEQUENCE; start_countdown = 1; end else state = HOLD; SEQUENCE: if (cnt = = 0 ) state = LAUNCH; else state = SEQUENCE; LAUNCH: begin state = ON_MISSION; launch_shuttle = 1; end ON_MISSION: /取消使命前，一直留在使命狀態(tài) if (just_launched) start_trip_meter = 1; else state = ON_MISSION; LAND:

10、 if (is_landed) state = HOLD; else begin land_shuttle = 1; state = LAND; end default: state = 5bxxxxx; endcaseend end/end of alwaysendmoduleModule clk_3(clkin,reset,clkout);input clkin,reset;reg 1:0 state;reg clk1;always (posedge clkin or negedge reset)if (!reset)state =2b00;else case(state)2b00:sta

11、te=2b01;2b01:state=2b11;2b11:state=2b00;default:state=2b00; endcasealways (negedge clk or negedge reset)if (!reset)clk1=1b0;elseclk1 y ) begin tmp = x; x = y; y = tmp; end endtaskendmodulemodule compare(equal,a,b);parameter size=1;output equal;input size-1:0 a, b;assign equal =（a=b）? 1 : 0;endmodule

12、module decoder(out,in);output 7:0 out;input 2:0 in;assign out = 1b1in;/* 把最低位的把最低位的1左移左移 in（根據(jù)從（根據(jù)從in口輸入的值）口輸入的值）位，并賦予位，并賦予out */endmodulemodule encoder1(none_on,out,in); output none_on; output 2:0 out; input 7:0 in; reg 2:0 out; reg none_on; always (in) begin: local /此處此處begin - end塊必須有一模塊名塊必須有一模塊名

13、 integer i; out = 0; none_on = 1; /*returns the value of the highest bit number turned on*/ for( i=0; i8; i=i+1 ) if( ini ) begin out = i; none_on = 0; end endendmodulemodule encoder2 ( none_on, out2, out1, out0, h, g, f, e, d, c, b, a); input h, g, f, e, d, c, b, a; output none_on, out2, out1, out0

14、; wire 3:0 outvec; assign outvec= h? 4b0111 : g? 4b0110 : f? 4b0101: e? 4b0100 : d? 4b0011 :c? 4b0010 : b? 4b0001: a? 4b0000 : 4b1000; assign none_on = outvec3; assign out2 = outvec2; assign out1 = outvec1; assign out0 = outvec0;endmodulemodule encoder3 (none_on, out2, out1, out0, h, g,f, e, d, c, b

15、, a);input h, g, f, e, d, c, b, a;output out2, out1, out0，none_on;reg 3:0 outvec;assign none_on,out2,out1,out0 = outvec;always ( a or b or c or d or e or f or g or h) if(h)outvec = 4b0111; else if(g)outvec = 4b0110; else if(f)outvec = 4b0101; else if(e)outvec = 4b0100; else if(d)outvec = 4b0011; els

16、e if(c)outvec = 4b0010; else if(b)outvec = 4b0001; else if(a)outvec = 4b0000; elseoutvec = 4b1000;endmodulemodul emux1(out, a, b, sel);output out;input a, b, sel;assign out = sel? a : b;endmodule使用連續(xù)賦值、使用連續(xù)賦值、casecase語句或語句或if-elseif-else語句可以生成多路語句可以生成多路器電路，如果條件語句（器電路，如果條件語句（casecase或或if-elseif-else）

17、中分支條件）中分支條件是互斥的話，綜合器能自動地生成并行的多路器。是互斥的話，綜合器能自動地生成并行的多路器。module mux2( out, a, b, sel); output out; input a, b, sel; reg out; /用電平觸發(fā)的用電平觸發(fā)的always塊來設(shè)計多路器的組合邏輯塊來設(shè)計多路器的組合邏輯 always ( a or b or sel ) case( sel ) 1b1: out = a; 1b0: out = b; default: out = bx; endcaseendmodulemodule mux3( out, a, b, sel);outp

18、ut out;input a, b, sel;reg out;always ( a or b or sel )begin if( sel ) out = a; else out = b;endendmodulemodule parity( even_numbits,odd_numbits,input_bus);output even_numbits, odd_numbits;input 7:0 input_bus;assign odd_numbits = input_bus;assign even_numbits = odd_numbits;endmodule module trist1( o

19、ut, in, enable);output out;input in, enable;assign out = enable? in: bz;endmodule module trist2( out, in, enable );output out;input in, enable;/bufif1是是 一個一個 Verilog門級原語（門級原語（primitive）bufif1 mybuf1(out, in, enable);endmodulemodule bidir(tri_inout, out, in, en, b);inout tri_inout;output out;input in

20、, en, b;assign tri_inout = en? In : bz;assign out = tri_inout b;endmodulemodule dff( q, data, clk);output q;input data, clk;reg q;always ( posedge clk )begin q = data;endendmodulemodule latch1( q, data, clk);output q;input data, clk;assign q = clk? data : q;endmodulemodule latch2( q, data, clk, set,

21、 reset);output q;input data, clk, set, reset;assign q= reset? 0 : ( set? 1:(clk? data : q ) );endmodulemodule latch3( q, data, clk);output q;input data, clk;reg q;always (clk or data) if(clk) q=data; endmodulemodule shifter( din, clk, clr, dout);input din, clk, clr;output 7:0 dout;reg 7:0 dout;alway

22、s (posedge clk) if(clr)/清零清零 dout = 8b0; else begin dout = dout1; /左移一位左移一位 dout0 = din; /把輸入信號放入寄存器的最低位把輸入信號放入寄存器的最低位 endendmodulemodule counter1( out, cout, data, load, cin, clk);output 7:0 out;output cout;input 7:0 data;input load, cin, clk;reg 7:0 out;always (posedge clk)if( load ) out = data;else out = out + cin;assign cout=( & out) & cin;/只有當(dāng)只有當(dāng)out7:0的所有各位都為的所有各位都為1/并且進位并且進位cin也為