數(shù)字集成電路(中文)第六章

1、EE141 Digital Integrated Circuits2ndCombinational Circuits1Nov 9, 2011EE141 Digital Integrated Circuits2ndCombinational Circuits2組合邏輯時序邏輯Output = f(In)Output = f(In, Previous In)Combina t i o n alLogicCircuitOutInCombina t i o n alLogicCircuitOutInStateEE141 Digital Integrated Circuits2ndCombination

2、al Circuits3q每一時刻每一時刻 (除了切換期間的瞬態(tài)效應(yīng)）每個門除了切換期間的瞬態(tài)效應(yīng)）每個門 的輸出通過一個低阻路徑連接到的輸出通過一個低阻路徑連接到q在任何時候該門的輸出即為該電路實現(xiàn)的布在任何時候該門的輸出即為該電路實現(xiàn)的布爾函數(shù)值爾函數(shù)值(再一次忽略切換期間的瞬態(tài)效應(yīng)再一次忽略切換期間的瞬態(tài)效應(yīng)) q不同于動態(tài)電路，后者依賴把信號值暫時存不同于動態(tài)電路，后者依賴把信號值暫時存放在高阻抗電路節(jié)點的電容上放在高阻抗電路節(jié)點的電容上VDD or Vss EE141 Digital Integrated Circuits2ndCombinational Circuits4VDDF(

3、In1,In2,InN)In1In2InNIn1In2InNPUNPDNPMOS onlyNMOS onlyPUN(上拉網(wǎng)絡(luò)) 和 PDN(下拉網(wǎng)絡(luò)) 是雙通道邏輯網(wǎng)絡(luò)EE141 Digital Integrated Circuits2ndCombinational Circuits5q一個晶體管可以看成是一個由其柵信號控制的開關(guān)qPDN由NMOS器件構(gòu)成，PUN由PMOS器件構(gòu)成q可以推導(dǎo)出一組規(guī)則來實現(xiàn)邏輯功能q互補CMOS結(jié)構(gòu)的上拉和下拉網(wǎng)絡(luò)互為對偶網(wǎng)絡(luò)q互補門本質(zhì)上是反相的，只能實現(xiàn)與非、或非和異或門q實現(xiàn)一個具有N個輸入的邏輯門需晶體管數(shù)目2N個EE141 Digital Integ

4、rated Circuits2ndCombinational Circuits6Transistors can be thought as a switch controlled by its gate signalNMOS switch closes when switch control input is highNMOS邏輯規(guī)則-串聯(lián)AND操作、并聯(lián)OR操作EE141 Digital Integrated Circuits2ndCombinational Circuits7PMOS邏輯規(guī)則-串聯(lián)NOR 操作、并聯(lián)NAND操作EE141 Digital Integrated Circuit

5、s2ndCombinational Circuits8VDDVDD 0PDN0 VDDCLCLPUNVDD0 VDD - VTnCLVDDVDDVDD |VTp|CLSDSDVGSSSDDVGSEE141 Digital Integrated Circuits2ndCombinational Circuits9PUN和PDN是互補網(wǎng)絡(luò) 符合DeMorgan定律 單級互補CMOS邏輯門是反相輸出的 同相：需加額外反相EE141 Digital Integrated Circuits2ndCombinational Circuits10EE141 Digital Integrated Circui

6、ts2ndCombinational Circuits11EE141 Digital Integrated Circuits2ndCombinational Circuits12C(a) pul l - d o wn netwo rkSN1SN4SN2SN3DFFADBCDFABCsub-net sDAABCVDDVDDB(c) com p l e t e g ateEE141 Digital Integrated Circuits2ndCombinational Circuits13OUT = D + A (B + C)DABCDABCEE141 Digital Integrated Cir

7、cuits2ndCombinational Circuits14EE141單元設(shè)計標(biāo)準單元通用邏輯可綜合等高，寬度可變數(shù)據(jù)通路單元規(guī)則、結(jié)構(gòu)化邏輯（算術(shù)運算）單元中包含互連線固定高度和寬度數(shù)字集成電路14組合邏輯電路EE141 Digital Integrated Circuits2ndCombinational Circuits15不包含維數(shù)信息表示了晶體管間的相對位置EE141 Digital Integrated Circuits2ndCombinational Circuits16EE141 Digital Integrated Circuits2ndCombinational Cir

8、cuits17不包含維數(shù)信息表示了晶體管間的相對位置InOutVDDGNDInverterAOutVDDGNDBNAND2EE141 Digital Integrated Circuits2ndCombinational Circuits18CABX = C (A + B)BACijABCEE141 Digital Integrated Circuits2ndCombinational Circuits19XCABABCXVDDGNDVDDGNDEE141 Digital Integrated Circuits2ndCombinational Circuits20CABX = C (A + B

9、)BACijjVDDXXiGNDABCPUNPDNABC邏輯圖EE141 Digital Integrated Circuits2ndCombinational Circuits21CABX = (A+B)(C+D)BADVDDXXGNDABCPUNPDNCDDABCDEE141 Digital Integrated Circuits2ndCombinational Circuits22GNDxabcdVDDxGNDxabcdVDDx(a) Logic graphs for (ab+cd)(b) Euler Paths a b c dacdxVDDGND(c) stick diagram fo

10、r ordering a b c dbEE141 Digital Integrated Circuits2ndCombinational Circuits23n 靜態(tài)特性靜態(tài)特性高噪聲容限高噪聲容限(NM ) VOH=VDD, VOL=VSS (GND)無靜態(tài)功耗無靜態(tài)功耗 穩(wěn)態(tài)時，穩(wěn)態(tài)時，VDD和和VSS(GND)間無直流通路間無直流通路n 動態(tài)特性動態(tài)特性上升、下降時延接近上升、下降時延接近 上下網(wǎng)絡(luò)有適當(dāng)?shù)某叽绫壤舷戮W(wǎng)絡(luò)有適當(dāng)?shù)某叽绫壤鼸E141 Digital Integrated Circuits2ndCombinational Circuits24q滿電源幅度開關(guān); 高噪聲容限q

11、電平幅度與器件尺寸無關(guān); ratiolessq穩(wěn)態(tài)時總有到VDD或GND之間的通路; 低輸出阻抗q高輸入阻抗; 輸入穩(wěn)態(tài)電流幾乎為零q電源與地之間無直接通路; 無靜態(tài)功耗q傳輸延時是負載電容和晶體管電阻的函數(shù)EE141 Digital Integrated Circuits2ndCombinational Circuits25AReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintNAND2INVNOR2EE141 Digital Integrated Circuits2ndCombinational Circuits26q延時與輸入波形有關(guān)q輸

12、出高到低的轉(zhuǎn)換 A=B=0-1 延時： 0.69(2Rn)CL A=1，B=0-1- 延時： 0.69 (2Rn )CL A=0-1，B=1 延時： 0.69 (2Rn )CL 實際上單A跳變比單 B跳變快CLARnARpBRpBRnCintEE141 Digital Integrated Circuits2ndCombinational Circuits27q延時與輸入波形有關(guān)q輸出低到高的轉(zhuǎn)換 A=B=1-0 延時： 0.69 Rp/2 CL A=1，B=1-0- 延時： 0.69 Rp CL A=1-0，B=1 延時： 0.69 Rp CL 實際上單A跳變比單B跳變快CLARnARpBR

13、pBRnCintEE141 Digital Integrated Circuits2ndCombinational Circuits28A=B=10B=1, A=10B=1 0, A=1time psVoltage VInput DataPatternDelay(psec)A=B=0169A=1, B=0162A= 01, B=150A=B=1035A=1, B=1076A= 10, B=157NMOS = 0.5m/0.25 mPMOS = 0.75m/0.25 mCL = 100 fFEE141 Digital Integrated Circuits2ndCombinational Cir

14、cuits29DCBADCBACLC3C2C1 分布RC模型 (Elmore延時)tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)傳輸延時隨扇入迅速惡化 - 最壞情況成平方關(guān)系 - 電阻電容同時起作用EE141 Digital Integrated Circuits2ndCombinational Circuits30tpLHtp (psec)fan-in避免扇入大于4的門tpHL平方線性tptpLHEE141 Digital Integrated Circuits2ndCombinational Circuits31tpNOR2tp (psec)eff. fan-out所有的

15、門具有相同驅(qū)動電流tpNAND2tpINV斜率是驅(qū)動力的函數(shù)EE141 Digital Integrated Circuits2ndCombinational Circuits32q扇入: 平方源于電容和電阻的增加q扇出: 每個額外扇出增加負載 CLEE141 Digital Integrated Circuits2ndCombinational Circuits33q晶體管尺寸規(guī)則 只要扇出電容為主q漸進尺寸規(guī)則InNCLC3C2C1In1In2In3M1M2M3MN分布RC線M1 M2 M3 MN (最接近輸出最小)使R1R2R3RNEE141 Digital Integrated Cir

16、cuits2ndCombinational Circuits34q晶體管排序C2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical pathcritical path放電101放電放電1延時由CL, C1 and C2的放電時間決定延時由CL的放電時間決定1101放電放電結(jié)束放電結(jié)束EE141 Digital Integrated Circuits2ndCombinational Circuits35q不同的邏輯結(jié)構(gòu)F = ABCDEFGHEE141 Digital Integrated Circuits2ndCombinational Circu

17、its36q插入緩沖器將扇入和扇出隔離開CLCLEE141 Digital Integrated Circuits2ndCombinational Circuits37EE141晶體管尺寸規(guī)則假定典型p/n管比例為2/1并聯(lián)保持(考慮單個跳變；同時跳變時電阻，并聯(lián)速度更快)串聯(lián)加倍(考慮同時跳變時，電阻串聯(lián)折半，減小單個電阻)2 ARpBRp24 BRp單個信號輸入電容為INV的5/3單個信號 Rn輸入電容 2 B為INV的4/3CL4ARpCint2RnACint1RnARnB1CL數(shù)字集成電路28組合邏輯電路EE141 Digital Integrated Circuits2ndCombi

18、national Circuits38 CLBRnARpBRpARnCintBRpARpARnBRnCLCint22221144EE141 Digital Integrated Circuits2ndCombinational Circuits39OUT = D + A (B + C)DABCDABC12224488EE141 Digital Integrated Circuits2ndCombinational Circuits40OUT = D + A (B + C)DABCDABC12224488EE141 Digital Integrated Circuits2ndCombinatio

19、nal Circuits41EE141 Digital Integrated Circuits2ndCombinational Circuits42目標(biāo): 相對于靜態(tài)互補CMOS, 減少晶體管個數(shù)VDDVSSPDNIn1In2In3FRLLoadVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNResistiveDepletionLoadPMOSLoad(a) 電阻負載(b) 耗盡 NMOS負載(c) 偽NMOS負載VT 有比邏輯EE141 Digital Integrated Circuits2ndCombinational Circuits45VDDVSSP

20、DNIn1In2In3FRL電阻負載電阻負載NMOS+ 電阻負載電阻負載 VOH = VDD VOL = RPNRPN + RL 不對稱響應(yīng)不對稱響應(yīng) 存在靜態(tài)功耗存在靜態(tài)功耗 tpL= 0.69 RLCLVDDEE141 Digital Integrated Circuits2ndCombinational Circuits46耗盡負載 NMOS偽-NMOSVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDN耗盡負載耗盡負載PMOS負載負載VT 寄生小=速度快l理想開關(guān) - 低導(dǎo)通電阻和低寄生電容EE141 Digital Integrated Circuits

21、2ndCombinational Circuits56BBAF =AB0EE141 Digital Integrated Circuits2ndCombinational Circuits57VDDInOutx0.5m/0.25m0.5m/0.25m1.5m/0.25m00.511.520.01.02.03.0Time nsVoltage VxOutInEE141 Digital Integrated Circuits2ndCombinational Circuits58A = 2.5 VBC = 2.5 VCLA = 2.5 VC = 2.5 VBM2M1Mn缺陷 -閾值損失 -后繼反相器有

22、短路 功耗EE141 Digital Integrated Circuits2ndCombinational Circuits59M2M1MnMrOutABVDDVDDLevel RestorerX 電平恢復(fù)器 -使Vx迅速拉到高電平 問題：尺寸規(guī)劃 -A=0，B=0-1時 -有比邏輯EE141 Digital Integrated Circuits2ndCombinational Circuits60EE141 Digital Integrated Circuits2ndCombinational Circuits61lCPL門的特點互補數(shù)據(jù)輸入用較少管子實現(xiàn)加法器和異或功能差分信號極性免去

23、了多余反相器屬于靜態(tài)邏輯，有較好抑噪能力模塊化結(jié)構(gòu)EE141 Digital Integrated Circuits2ndCombinational Circuits62ABCCABCCBCLC = 0 VA = 2.5 VC = 2.5 VBCLC = 0 VA = 0 VC = 2.5 VEE141 Digital Integrated Circuits2ndCombinational Circuits63Vout0 V2.5 V2.5 VRnRp0.01.02.00 10 20 30 Vout, VResistance, ohmsRnRpRn | RpEE141 Digital Inte

24、grated Circuits2ndCombinational Circuits64AM2M1BSSSFVDDABFBABBM1M2M3/M4EE141 Digital Integrated Circuits2ndCombinational Circuits65V1Vi-1C2.52.500ViVi+1CC2.50Vn-1VnCC2.50InV1ViVi+1CVn-1VnCCInReqReqReqReqCC(a)(b)CReqReqCCReqCCReqReqCCReqCInm(c)EE141 Digital Integrated Circuits2ndCombinational Circuit

25、s66EE141 Digital Integrated Circuits2ndCombinational Circuits67EE141 Digital Integrated Circuits2ndCombinational Circuits68q靜態(tài)電路在任何時候通過低阻通路，輸出連在VDD或VSS. 除非在開關(guān)的瞬間 扇入n需要2n個晶體管（一半為p管）q動態(tài)電路依賴高阻節(jié)點（電容）暫存信號電荷 結(jié)構(gòu)簡單，寄生小，速度快 易受噪聲影響 扇入n需要n+2晶體管（一個是p管）EE141 Digital Integrated Circuits2ndCombinational Circuits69

26、In1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMe兩相位工作 預(yù)充電 (CLK = 0) 求值 (CLK = 1)EE141 Digital Integrated Circuits2ndCombinational Circuits70q動態(tài)門的輸出一旦放電后，要等到下一次預(yù)充電才能充電q在求值時，輸出最多完成一次1-0轉(zhuǎn)化 要么保持為1 要么放電到0，放電后不可能回到1，直到再次充電 級聯(lián)問題.q在求值期間或是求值之后，輸出可以是高組態(tài)，狀態(tài)存儲在CL上，PDN網(wǎng)絡(luò)截至EE141 Digital Integrated Circuits2ndCombinati

27、onal Circuits71q邏輯函數(shù)僅由 PDN完成 晶體管數(shù)目為N+2 （靜態(tài)互補CMOS：2N）q全幅輸出 (VOL = GND and VOH = VDD)q器件尺寸不影響邏輯電平 與比例無關(guān)q開關(guān)速度更快 寄生電容?。–in，Cout）q無短路功耗 只有漏電和電容功耗EE141 Digital Integrated Circuits2ndCombinational Circuits72q總功耗通常高于靜態(tài)互補CMOS VDD 和GND之間無靜態(tài)電流和短路電流 無毛刺 較高的轉(zhuǎn)化概率 Clk額外負載q需要一個預(yù)充電或求值時鐘CLKEE141 Digital Integrated Ci

28、rcuits2ndCombinational Circuits73CLClkClkOutAMpMe漏電來源CLKVOut預(yù)充電求值主要是亞閾值漏電流EE141 Digital Integrated Circuits2ndCombinational Circuits74CLClkClkMeMpABOutMkp類似于傳輸晶體管中的電平恢復(fù)管維持管EE141 Digital Integrated Circuits2ndCombinational Circuits75CL 存儲的電荷在CL 和 CA 之間再分配（共享） ，降低了可靠性CLClkClkCACBB=0AOutMpMeEE141 Digit

29、al Integrated Circuits2ndCombinational Circuits76CL=50fFClkClkAABBB!BCCOutCa=15fFCc=15fFCb=15fFCd=10fFEE141 Digital Integrated Circuits2ndCombinational Circuits77MpMeVDDOutAB = 0CLCaCbMaMbXCLVDDCLVoutt CaVDDVTnVX+=or VoutVoutt VDDCaCL- - VDDVTnVX= VoutVDDCaCaCL+- - -=case 1) if Vout VTnB =0ClkXCLCaC

30、bAOutMpMaVDDMbClkMeEE141 Digital Integrated Circuits2ndCombinational Circuits78ClkClkMeMpABOutMkpClk對內(nèi)部節(jié)點進行預(yù)充電，采用時鐘驅(qū)動晶體管代價是增加面積和功耗EE141 Digital Integrated Circuits2ndCombinational Circuits79CL1ClkClkB=0A=0Out1MpMeOut2CL2In動態(tài) NAND靜態(tài) NAND=1=0EE141 Digital Integrated Circuits2ndCombinational Circuits80

31、VoltageTime, nsClkInOut1Out2EE141 Digital Integrated Circuits2ndCombinational Circuits81CLClkClkBAOutMpMe在輸出OUT和輸入時鐘CLK之間（預(yù)充電管），由于柵漏電容導(dǎo)致輸出電壓超出VDD。時鐘的快速上升沿（下降呀）耦合到輸出OUTEE141 Digital Integrated Circuits2ndCombinational Circuits82ClkClkIn1In2In3In4OutIn &ClkOutTime, nsVoltage時鐘饋通時鐘饋通EE141 Digital Integrated Circuits2ndCombinational Circuits83ClkClkOut1InMpMeMpMeClkClkOut2VtClkInOut1Out2VVTn輸入不允許10的轉(zhuǎn)化，只允許0 1 的轉(zhuǎn)化!EE141 Digital Integrated Circuits2ndCombinational Circuits84In1In2