數(shù)字邏輯設(shè)計(jì)第6章 Combinational logic Design Practices2

1、組合邏輯部分小結(jié)第4章 組合邏輯設(shè)計(jì)原理第6章 組合邏輯設(shè)計(jì)實(shí)踐1第4章 基本原理 開關(guān)代數(shù)基礎(chǔ)組合邏輯的基本分析、綜合方法冒險(xiǎn) 開關(guān)代數(shù)的公理、定理 對(duì)偶、反演規(guī)則 邏輯函數(shù)的表示法 分析步驟，利用公式進(jìn)行化簡(jiǎn) 設(shè)計(jì)方法、步驟 利用卡諾圖化簡(jiǎn)，電路處理 無關(guān)項(xiàng)的化簡(jiǎn)、多輸出函數(shù)的化簡(jiǎn) 冒險(xiǎn)的檢查和消除2Switching algebraex1：prove 例2：寫出下列函數(shù)的反函數(shù)和對(duì)偶函數(shù)：3Truth table、canonical sum、 canonical product、Karnaugh mapLogic functiontruth tableStandard Represent

2、ation of logic function4.7(c)4.7(d)4.7(h)4.8(c)4Truth table、canonical sum、 canonical product、Karnaugh mapStandard Representation of logic functionTruth table canonical sum、 canonical productcanonical sum、 canonical product4.9(b)4.9(c)5Logic equation canonical sum、 canonical productMinterm and maxter

3、m 例：四個(gè)變量可以構(gòu)成( )個(gè)最小項(xiàng)，它們之和是( )。最小項(xiàng)m5和m10相與的結(jié)果為（ ）。Standard Representation of logic function4.9(f)4.9(e)6卡諾圖化簡(jiǎn)：最小積之和：圈1最小和之積：圈0；F取非后圈1再取非。4.15 (b)邏輯函數(shù)的化簡(jiǎn)4.15 (f)4.15 (d)4.15 (e)7卡諾圖化簡(jiǎn)：最小積之和：圈1最小和之積：圈0；F取非后圈1再取非。4.18(b)邏輯函數(shù)的化簡(jiǎn)4.58(b)4.59(a)8Complement sum：對(duì)于一個(gè)邏輯函數(shù)，下列哪個(gè)說法是不正確的（ )。 a) 最小和邏輯表達(dá)式肯定唯一 b) 標(biāo)準(zhǔn)和邏

4、輯表達(dá)式肯定唯一 c) 標(biāo)準(zhǔn)積邏輯表達(dá)式肯定唯一 d) 完全和邏輯表達(dá)式肯定唯一 The sum of all the prime implicants of a logic function. 4.179組合電路的分析分析的目的：確定給定電路的邏輯功能分析步驟：由輸入到輸出逐級(jí)寫出邏輯函數(shù)表達(dá)式對(duì)輸出邏輯函數(shù)表達(dá)式進(jìn)行化簡(jiǎn)判斷邏輯功能（列真值表或畫波形圖）10例：下圖為一可控函數(shù)發(fā)生器，其中C1、C2為控制端，A、B為輸入變量，F(xiàn)為輸出變量。C1、C2的取值如表所示，完成此表。C1C2F=f(A,B)0001101111例：分析下面電路。寫出F1、F2的表達(dá)式：12分析圖示邏輯電路的功能B3

5、B2B1B0G3G2G1G0解：1、寫表達(dá)式2、列真值表3、分析功能0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1B3 B2 B1 B0G3 G2 G1 G00 0 0 00 0 0 10 0 1 1G3 = B3G2 = B3B2G1 = B2B1G0 = B1B0二進(jìn)制碼至GRAY碼的轉(zhuǎn)換電路0 0 1 00 1 1 00 1 1 10 1 0 10 1 0 01 1 0 01 1 0 11 1 1 11 1 1

6、01 0 1 01 0 1 11 0 0 11 0 0 013組合電路的綜合問題描述邏輯抽象選定器件類型函數(shù)化簡(jiǎn)電路處理將函數(shù)式變換電路實(shí)現(xiàn)真值表或函數(shù)式用門電路用MSI組合電路或PLD14例：設(shè)計(jì)用3個(gè)開關(guān)控制一個(gè)電燈的邏輯電路，要求改變?nèi)魏我粋€(gè)開關(guān)的狀態(tài)都能控制電燈由亮變滅或者由滅變亮。輸入：A、B、C，輸出：F =1 燈亮；F =0 燈滅。0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 ABCF011010011、填寫真值表2、選擇器件 用基本門電路實(shí)現(xiàn) 利用卡諾圖化簡(jiǎn) 用譯碼器實(shí)現(xiàn) 轉(zhuǎn)換為最小項(xiàng)之和 用數(shù)據(jù)選擇器實(shí)現(xiàn)150 00 00 0

7、0 00 10 10 10 11 01 01 01 01 11 11 11 10 00 11 01 10 00 11 01 10 00 11 01 10 00 11 01 1X1 X0Y1 Y00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 10 0 1 00 0 1 10 0 0 00 0 1 00 1 0 00 1 1 00 0 0 00 0 1 10 1 1 01 0 0 1P3 P2 P1 P0設(shè)計(jì)2位數(shù)乘法器1、列真值表 輸入：X、Y（2位） 輸出：乘積P（4位） P3 = X1X0Y1Y0Y1Y0X1X000 01 11 1000011110P21

8、112、用門電路實(shí)現(xiàn) 利用卡諾圖化簡(jiǎn) 注意：多輸出函數(shù)3、電路處理16Y1Y0X1X000 01 11 1000011110P1111111Y1Y0X1X000 01 11 1000011110P01111P3 = X1X0Y1Y0P2 = X1Y1P3P1 = X1Y0P3+X0Y1P3P0 = X0Y0Y1Y0X1X000 01 11 1000011110P21111117比較：按多輸出化簡(jiǎn)（紫色）按單個(gè)卡諾圖化簡(jiǎn)（黑色）P3 = X1 X0 Y1 Y0P2 = X1X0Y1 + X1Y1Y0P1 = X1Y1Y0 + X1X0Y0 + X0Y1Y0 + X1X0Y1P0 = X0 Y0P

9、3 = X1X0Y1Y0P2 = X1Y1P3P1 = X1Y0P3+X0Y1P3P0 = X0Y0考慮：用譯碼器實(shí)現(xiàn) 直接表示為標(biāo)準(zhǔn)和形式考慮：用4位加法器74X283和少許門實(shí)現(xiàn)184.35 An XOR gate4.55 a 3-bit comparator 4.38 realize a inverter?4.54OR-XOR circuitNOR-XOR circuitP2P1P0 Q2Q1Q0194.61 complete the timing diagram204.19 find all the static hazards and design a hazard-free cir

10、cuit.(g)Static-0 hazards or static-1 hazards？OR-AND circuit or AND-OR circuit？211) the logic equation?2）all of the static hazards.22第6章 設(shè)計(jì)實(shí)踐常用的中規(guī)模集成電路（MSI）編碼器、譯碼器、多路復(fù)用器、奇偶校驗(yàn)電路、 比較器、加法器、三態(tài)器件掌握基本功能，級(jí)聯(lián)的方法綜合應(yīng)用：利用基本MSI器件作為基本單元設(shè)計(jì)更復(fù)雜的組合邏輯電路文檔標(biāo)準(zhǔn)和電路定時(shí)（了解）23 a.Write the truth table of F and G。 b.Write the can

11、onical sum and product of F.Example246.43 show how to build all four of the following functions using one SSI package (four 2-input gates) and one 74x138. SSI package：P.361 Fig.6-18Example256.20 (c) Example(e) (f) 26例：利用74x138和與非門設(shè)計(jì)一位全減器；寫出各輸出函數(shù)的最小項(xiàng)之和表達(dá)式，畫出電路連接圖。 111011101001110010100110000011011110

12、0000BODBINYX 全減器真值表 Example27例設(shè)X、Z均為三位二進(jìn)制數(shù)，X為輸入，Z為輸出。要求二者之間有以下關(guān)系： 當(dāng)3X 6時(shí)，Z=X+1; 當(dāng)X 6時(shí)，Z=3。用一片38譯碼器74138和少量門實(shí)現(xiàn)該電路。Example286.41 design a customized decoder利用MSI和SSI部件，設(shè)計(jì)專用譯碼器，其功能表如下表所示，在你的設(shè)計(jì)中要使IC組件的數(shù)目最少。 輸入：A2、A1、A0，使能信號(hào)CS_L輸出：8位Example2930 31input：8421BCD codeoutput：1-out-of-10 codeY0Y9I0I1I2I3多余的6個(gè)

13、狀態(tài)如何處理？輸出均無效：拒絕“翻譯”作為任意項(xiàng)處理 電路內(nèi)部結(jié)構(gòu)簡(jiǎn)單節(jié)省多少個(gè)與門輸入端？6.38 Suppose that you are asked to design a new component, a decimal decoder that is optimized for applications in which only decimal input combinations are expected to occur. How can the cost of such a decoder be minimized compared to one that is simply

14、 a 4-to-16 decoder with six outputs removed? Write the logic equations for all ten outputs of the minimized decoder, assuming active-high inputs and outputs and no enable inputs. Minimal costMinimal risk32二-十進(jìn)制譯碼器0 0 0 0 0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11

15、1 0 01 1 0 11 1 1 01 1 1 11 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 00 0 1 0 0 0 0 0 0 00 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 00 0 0 0 0 1 0 0 0 00 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 1 0 00 0 0 0 0 0 0 0 1 00 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 0

16、 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0I3 I2 I1 I00123456789Y0 Y9偽碼任 意 項(xiàng)33Y0 = I3I2I1I0（minimal risk）I1I0I3I200 01 11 1000011110Y01ddddddY0 = I3I2I1I0（minimal cost）Y2 = I3I2I1I0I1I0I3I200 01 11 1000011110Y21ddddddY2 = I2I1I0I1I0I3I200 01 11 1000011110Y91Y9 = I3I2I1I0ddddddY9 = I3I034p.514 6.52 Draw the logi

17、c diagram for a circuit that uses the 74x148 to resolve priority among eight active-high inputs, I0I7, where I7 has the highest priority. The circuit should produce active-high address outputs A2A0 to indicate the number of the highest-priority asserted input. If no input is asserted, then A2A0 shou

18、ld be 111 and an IDLE output should be asserted. You may use discrete gates in addition to the 148. Be sure to name all signals with the proper active levels.一個(gè)自定義的編碼器要實(shí)現(xiàn)的電路74X148輸入：高電平有效低電平有效處理方法加反相器輸出A2A0：高電平有效低電平有效加反相器無有效輸入時(shí)：無有效輸入時(shí)：111111不取反有有效輸入時(shí)：IDLE=1用異或門處理74X148的輸出EO-L=0IDLE=0EO-L=1取反3536分析判定

19、優(yōu)先級(jí)電路：（利用74x148 ） 8個(gè)_電平有效輸入I0_LI7_L，_的優(yōu)先級(jí)最高 地址輸出A2A0，_電平有效 若輸出VALID高電平有效，則表示_A2A1A0GSEOEI74x148I7I0I0_LI7_LA2A1A0VALID低I0_L至少有一個(gè)輸入有效高p.514 6.53 Draw the logic diagram for a circuit that resolves priority among eight active-low inputs, I0_LI7_L, where I0_L has the highest priority. The circuit should

20、 produce active-high address outputs A2A0 to indicate the number of the highest-priority asserted input. If at least one input is asserted, then an AVALID output should be asserted. Be sure to name all signals with the proper active levels. This circuit canbe built with a single 74x148 and no other

21、gates.37八路數(shù)據(jù)選擇器構(gòu)成的電路如圖所示，寫出該電路的真值表及實(shí)現(xiàn)的邏輯函數(shù)表達(dá)式。Example38只用一片4選1數(shù)據(jù)選擇器實(shí)現(xiàn)邏輯函數(shù)。思考：（不允許用邏輯門電路輔助，輸入只提供原變量。） 39A3A2A1A0FA3A2A1A0F0 0 0 011 0 0 000 0 0 101 0 0 110 0 1 001 0 1 0d0 0 1 111 0 1 1d 0 1 0 00 1 1 0 0d0 1 0 101 1 0 1d0 1 1 011 1 1 0d0 1 1 101 1 1 1d采用數(shù)據(jù)選擇器74X151和必要的反相器設(shè)計(jì)一個(gè)組合電路。輸入為A3、A2、A1、A0 8421B

22、CD碼，當(dāng)A3、A2、A1、A0的等效十進(jìn)制數(shù)能被3整除時(shí)，輸出F=1，否則F=0。設(shè)計(jì)步驟：真值表降維電路圖例40思考：采用數(shù)據(jù)選擇器74X151和必要的反相器設(shè)計(jì)一個(gè)組合電路。輸入為四位二進(jìn)制數(shù)A=A3A2A1A0 ，當(dāng)A的等效十進(jìn)制數(shù)能被3整除時(shí)，輸出F=1，否F=0。采用數(shù)據(jù)選擇器74X151設(shè)計(jì)一個(gè)組合電路。當(dāng)輸入A3、A2、A1、A0為8421BCD碼時(shí)，輸出F=1，否則F=0。A3A2A1A0FA3A2A1A0F0 0 0 011 0 0 000 0 0 101 0 0 110 0 1 001 0 1 000 0 1 111 0 1 10 0 1 0 00 1 1 0 010 1

23、 0 101 1 0 100 1 1 011 1 1 000 1 1 101 1 1 11413輸入、5位的多路復(fù)用器輸入、輸出端口數(shù)分配6.63 Design a 3-input, 5-bit multiplexer that fits in a 24-pin IC package. Write the truth table and draw a logic diagram and logic symbol for your multiplexer.42Show how to realize the 4-input, 4-bit multiplexer with the functiona

24、lity described in Table below .S2S1S0端口 0 0 0P 0 0 1P 0 1 0P 0 1 1Q 1 0 0P 1 0 1P 1 1 0R 1 1 1T4片74x15143S2S1S0端口C1C0 0 0 0P0 0 0 0 1P0 0 0 1 0P0 0 0 1 1Q0 1 1 0 0P0 0 1 0 1P0 0 1 1 0R1 0 1 1 1T1 1S2S1S0端口 0 0 0P 0 0 1P 0 1 0P 0 1 1Q 1 0 0P 1 0 1P 1 1 0R 1 1 1TC1=S2S1C0=S1S0傳播延遲最小?C1=(S2S1)C0=(S1S0)

25、1110110 10 0Show how to realize the 4-input, 4-bit multiplexer with the functionality described in Table below .446.77 Design a customized multiplexer with five 4-bit input buses A, B, C, D, and E, selecting one of the buses to drive a 4-bit output bus T according to Table X6.77. You may use no more

26、 than three MSI and SSI ICs.S2S1S0Input to Select000A001B010A011C100A101D110A111E455路信號(hào)，每路4位選擇端S2S1S0用4個(gè)1/8 MUX?S2 S1 S0 0 0 B 0 1 C 1 0 D 1 1 E0 A1 B or C or D or E4選1的多路復(fù)用器 2片74X1532選1的多路復(fù)用器 1片74X157S2S1S0Input to select000A001B010A011C100A101D110A111E46Example6.20(f) 476.95 Design a comparator si

27、milar to the 74x85 that uses the opposite cascading order. That is, to perform a 12-bit comparison, the cascading outputs of the high-order comparator would drive the cascading inputs of the mid-order comparator, and the mid-order outputs would drive the low-order inputs. You neednt do a complete lo

28、gic design and schematic; a truth table and an application note showing the interconnection for a 12-bit comparison are sufficient.4849輸入：兩個(gè)8位無符號(hào)二進(jìn)制整數(shù) X 和 Y 一個(gè)控制信號(hào) M輸出：8位無符號(hào)二進(jìn)制整數(shù) Z邏輯功能：M = 1，Z = min(X,Y) M = 0，Z = max(X,Y)思路：（核心問題）（1）比較X,Y的大?。?）使Z為X,Y之一（3）控制邏輯 比較器（8位）多路復(fù)用器（二選一）根據(jù)M和X,Y的大小控制 多路復(fù)用器的地址選

29、擇端。Design a combinational circuit whose inputs are two 8-bit unsigned binary integers, X and Y, and a control signal M. The output of the circuit is an 8-bit unsigned binary integer Z such that Z = 0 if X = Y; otherwise, Z = min(X,Y) if M = 1, and Z = max(X,Y) if M = 0.50控制邏輯M多路復(fù)用器Z比較器XYXY思路：（核心問題）（

30、1）比較X,Y的大?。?）使Z為X,Y之一（3）控制邏輯 比較器（8位）多路復(fù)用器（二選一）根據(jù)M和X,Y的大小控制 多路復(fù)用器的地址選擇端。原理框圖51控制邏輯M多路復(fù)用器Z比較器XYXYGS1A4A1B4B74x1571Y4YGS1A4A1B4B74x1571Y4YP70 Q7074x682P=QPQX7:0Y7:0Z7:0S=0 Y=AS=1 Y=BM52MM PQ_L S0 00 11 01 1S=0 Y=AS=1 Y=B0110GS1A4A1B4B74x1571Y4YGS1A4A1B4B74x1571Y4YP70 Q7074x682P=QPQX7:0Y7:0Z7:0M=1，min(X

31、,Y)M=0，max(X,Y)53例：設(shè)計(jì)一個(gè)三個(gè)數(shù)的判斷電路。要求能夠判別三個(gè)4位二進(jìn)制數(shù)A、B、C是否相等、A是否最大、A是否最小，并分別給出“三個(gè)數(shù)相等”、“A最大”、“A最小”的輸出信號(hào)。可以附加必要的門電路。需要用 片74x85？54設(shè)計(jì)將BCD碼轉(zhuǎn)換成余3碼的碼制轉(zhuǎn)換電路方案一：利用基本門電路（SSI）實(shí)現(xiàn)1、列真值表0 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01

32、 0 0 11 0 1 0 1 1 1 1X3X0F3F0d2、卡諾圖化簡(jiǎn)（多輸出函數(shù)）3、電路處理，得到電路圖 “與-或”式 “與非-與非”式 “或-與”式 “或非-或非”式方案二：利用中規(guī)模集成電路MSI實(shí)現(xiàn) 譯碼器實(shí)現(xiàn)多輸出函數(shù)思考：有沒有更好的方法？55設(shè)計(jì)將BCD碼轉(zhuǎn)換成余3碼的碼制轉(zhuǎn)換電路一個(gè)更好的方法：余3碼 BCD碼 3 利用加法器（MSI）實(shí)現(xiàn)A0A1A2A3B0B1B2B3C0S0S1S2S3C474x283X0X1X2X3F0F1F2F3VCC110056例：使用一片74LS85（比較器）和一片74LS283（加法器）設(shè)計(jì)一個(gè)電路，將2421BCD碼（X3X2X1X0）轉(zhuǎn)

33、換為余3碼（Y3Y2Y1Y0）。 十進(jìn)制數(shù)2421碼余三碼十進(jìn)制數(shù)2421碼余三碼000000011510111000100010100611001001200100101711011010300110110811101011401000111911111100規(guī)律？輸入4輸入4輸出=輸入+0011輸出=輸入-0011加/減法器比較器輸出AGTBOUT=0比較器輸出AGTBOUT=157實(shí)現(xiàn)兩個(gè)BCD碼的加法運(yùn)算思考：兩個(gè)BCD碼與兩個(gè)4位二進(jìn)制數(shù)相加的區(qū)別 如果(X+Y)產(chǎn)生進(jìn)位信號(hào)C 或 在 10101111 之間 需要進(jìn)行修正 結(jié)果加6利用 F 表示是否需要修正F = C + S3S2S

34、1S0 + S3S2S1S0 + S3S2S1S0 + S3S2S1S0 + S3S2S1S0 + S3S2S1S0S1S0S3S200 01 11 1000011110111111F = C + S3S2 +S3S158相加判別修正A0 S0A1 S1A2 S2A3 S3B0B1B2B3C0 C474x283A0 S0A1 S1A2 S2A3 S3B0B1B2B3C0 C474x283X0X1X2X3Y0Y1Y2Y3F0F1F2F3CO實(shí)現(xiàn)兩個(gè)BCD碼的加法運(yùn)算 需要2個(gè)加法器，分別進(jìn)行加法運(yùn)算和修正 判別邏輯： F = C + S3S2 +S3S1 電路組成F實(shí)現(xiàn)兩個(gè)BCD碼的減法運(yùn)算？5

35、9Barrel shifter (桶式移位器)具有n個(gè)數(shù)據(jù)輸入和n個(gè)數(shù)據(jù)輸出控制輸入：指定輸入輸出之間如何移動(dòng)數(shù)據(jù) （移位方向、移位類型、移動(dòng)的位數(shù)）習(xí)題6.71 設(shè)計(jì)一個(gè)簡(jiǎn)單16位桶式移位器（向左循環(huán)移位）6.71 A 16-bit barrel shifter is a combinational logic circuit with 16 data inputs, 16 data outputs, and 4 control inputs. The output word equals the input word, rotated by a number of bit position

36、s specified by the control inputs. For example, if the input word equals ABCDEFGHIJKLMNOP (each letter represents one bit), and the control inputs are 0101 (5), then the output word is FGHIJKLMNOPABCDE. Design a 16-bit barrel shifter using combinational MSI parts discussed in this chapter. Your desi

37、gn should contain 20 or fewer ICs. Do not draw a complete schematic, but sketch and describe your design in general terms and indicate the types and total number of ICs required.60桶式移位器具有n個(gè)數(shù)據(jù)輸入和n個(gè)數(shù)據(jù)輸出控制輸入：指定輸入輸出之間如何移動(dòng)數(shù)據(jù) （移位方向、移位類型、移動(dòng)的位數(shù)）習(xí)題6.71 設(shè)計(jì)一個(gè)簡(jiǎn)單16位桶式移位器（向左循環(huán)移位）若輸入：A B C D E F G H I J K L M N O

38、P 則輸出：F G H I J K L M N O P A B C D E 用4位控制輸入S3:0指定移動(dòng)位數(shù)，比如 S=0101，1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 0 DIN15 DIN0DOUT15 DOUT061S3S2S1S0DOUT15S3S2S1S0DOUT150000DIN151000DIN70001DIN141001DIN60010DIN13 1010DIN5 0011DIN121011DIN40100DIN111100DIN30101DIN101101DIN20110DIN9 1110DIN1 0111DIN81111DIN0輸入： DIN15 DIN14 DIN1 DIN0輸出： DOUT15 DOUT14 DOUT1 DOUT0 思路：輸出的每一位都是從16個(gè)輸入中選出的。 多路復(fù)用器（數(shù)據(jù)選擇器）62方案一：利用74x1511、如何擴(kuò)展多路復(fù)用器？ 16個(gè)輸入端；4個(gè)地址選擇端；ENCBA YD0D7ENCBA YD0D7DIN7:0DIN15:8YYENAB Y