RISC-V技術(shù)及ISA架構(gòu)設(shè)計概述

1、Hot Chips Tutorial, Part-I:RISC-V Overview and ISA Design Why Instruction Set Architecture mattersWhy cant Intel sell mobile chips?99%+ of mobile phones/tablets based on ARM v7/v8 ISAWhy cant ARM partners sell servers?99%+ of laptops/desktops/servers based on AMD64 ISA (over 95%+ built by Intel)How

2、can IBM still sell mainframes?IBM 360, oldest surviving ISA (50+ years)ISA is most important interface in computer systemwhere software meets hardware Open Interfaces Work for Software!Why not successful free & open standards and free & open implementations, like other fields?3FieldOpen StandardFree

3、, Open Implement.Proprietary Implement.NetworkingEthernet, TCP/IPManyManyOSPosixLinux, FreeBSDM/S WindowsCompilersCgcc, LLVMIntel icc, ARMccDatabasesSQLMySQL, PostgresSQLOracle 12C, M/S DB2GraphicsOpenGLMesa3DM/S DirectXISA?x86, ARM, IBM360 Companies and their ISAs Come and GoProprietary ISA fortune

4、s tied to business fortunes and whimsDigital Equipment CorporationPDP-11, VAX, AlphaInteli960, i860, ItaniumMIPSSold to Imagination, then bought by Wave AI startup, now opening R6?SPARCWas opened by Sun, acquired by Oracle, now closed downARMSold to Softbank at 40% premiumNow 25% sold off to Abu Dha

5、bi investment fund4NVIDIA Tegra SoCToday, many ISAs on one SoCApplications processor (usually ARM)Graphics processorsImage processorsRadio DSPsAudio DSPsSecurity processorsPower-management processor dozen ISAs on some SoCs each with unique software stackWhy?Apps processor ISA too big, inflexible for

6、 acceleratorsIP bought from different places, each proprietary ISAEngineers build home-grown ISA cores56Do we need all these different ISAs?Must they be proprietary?Must they keep disappearing?What if there was one stable free and open ISA everyone could use for everything?RISC-V BackgroundIn 2010,

7、after many years and many research projects using MIPS, SPARC, and x86, time for architecture group at UC Berkeley to choose ISA for next set of projectsObvious choices: x86 and ARMx86 impossible too complex, IP issuesARM mostly impossible complex, no 64-bit in 2010, IP issuesSo we started “3-month

8、project” during summer 2010 to develop clean-slate ISAPrincipal designers: Andrew Waterman, Yunsup Lee, David Patterson, Krste AsanovicFour years later, May 2014, released frozen base user specmany tapeouts and several research publications along the wayName RISC-V (pronounced “risk-five”) represent

9、s fifth major Berkeley RISC ISA7RISC-I (1981)SOAR aka RISC-III (1984)SPUR aka RISC-IV (1988)First RISC-V (Raven-1, 28nm FDSOI,2011)RISC-II (1983)Hot Chips 20148RISC-V Foundation (2015- )RISC-V is the open- source hardware Instruction Set Architecture (ISA)Frozen base user spec released in 2014, cont

10、ributed, ratified, and openly published by the RISC-V FoundationRISC-V FoundationThe RISC - V Fo und a tio n is a no n- p ro fit e ntity se rving m e m b e rs a nd the ind ustryO ur m issio n is to a c c e le ra te RISC -V a d o p tio n with sha re d b e ne fit to the e ntire c o m m unity o f sta k

11、e ho ld e rs.Drive progression of ratified specs, compliance suite, and other technical deliverablesGrow the overall ecosystem / membership, promoting diversity while preventing fragmentationDeepen community engagement and visibility3002752502252001751501251007550250RISC-V Foundation Growth HistoryS

12、eptember 2015 to May 201910May 2019Mo retha n 250 RISC -V Me m b e rs in 28 C o untrie s Aro undtheWo rld 13 Universities 29 Consulting; Research23 Development Tools; SW and Cloud 104 Individual RISC-V developers and advocates 51 Machine Learning/AI; Commercial Chip Vendors; FPGA; Broad Market; Netw

13、orking; Application Processors, Graphics 45 Semiconductor IP; IP and Design Services; Foundry ServicesQ3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2 2015201520162016201620162017201720172017201820182018201820192019Calista Redmond, CEO, RISC-V FoundationPreviously, Vice-President of IBM Z Ecosystem division; Presid

14、ent of OpenPOWER Foundation.12Programs increase member value + engagement13Technical DeliverablesGuard against fragmentationManage and progress technical deliverables through work groups and development teamProcess and initiate technical work groupsDevelop and manage member sandbox portalCompliance

15、+ CertificationDevelop self serve testing and compliance certification suiteProvide visibility to additional compliance certification and verification optionsAdvocacy + OutreachEstablish technical advocate programEngage geographic and domain specific engineers via advocate-led formal and informal op

16、portunitiesEstablish alliances with other organizationsLearning + TalentDevelop multi-level learning modulesConnect universities, professors, and course materialDevelop badge and skill certificationMatch talent via online and event forumsVisibilityDrive constant drumbeat of member and foundation vis

17、ibility through multiple mediaEngage in industry events and host Foundation eventsCultivate strategic visibility through industry forums, analysts, and mediaMarketplaceProvide online marketplace of providers and productsOffer RFP matching to membersRISC-V EcosystemSoftwareHardwareISA specificationFo

18、undationComplianceGolden ModelOpen-source cores:Rocket, BOOM, RI5CY,Ariane, PicoRV32, Piccolo, SCR1, Swerv, Hummingbird,Commercial core providers: Andes, Bluespec, Cloudbear, Codasip, Cortus, C-Sky, Nuclei, SiFive, Syntacore, Inhouse cores:Nvidia, WDC, Alibaba,+othersOpen-source software:Gcc, binuti

19、ls, glibc, Linux, BSD, LLVM, QEMU, FreeRTOS,ZephyrOS, LiteOS, SylixOS, Commercial software: Lauterbach, Segger, IAR, Micrium, ExpressLogic, Ashling, Imperas, AntMicro, 14Why is RISC-V so popular?Engineers sometimes “dont see forest for the trees”The movement is not happening because some benchmark r

20、an 10% faster, or some implementation was 30% lower powerThe movement is happening because new business model changes everythingPick ISA first, then pick vendor or build own coreAdd your own extension without getting permissionImplementation features/PPA will followWhatever is broken/missing in RISC

21、-V will get fixed15Modest RISC-V Project Goal1 6Become the industry-standard ISA for all computing devicesIndustry Adoption StatusLarge companies adopting RISC-V for deeply embedded controllers in their SoCs (“minion cores”)2016 NVIDIA announced all future GPUs will use RISC-V2017 Western Digital an

22、nounced transition of all billion cores/year to RISC-VOthers waiting in the wingsCTOs across entire worldwide value chain of IC suppliers, system providers, service providers, are evaluating RISC-V strategies1 7RISC-V: An Everyday Design ChoiceFor embedded/IoT, RISC-V is already strong competitor, a

23、nd other areas adopting RISC-V alsoProduction ramp starting, expect “millions” of SoCs to ship with RISC-V cores in 2019SiFive announced 100 RISC-V IP design winsAndes announced 21 wins in 2018, 60 in 2019Message: You wont get fired for choosing RISC-V!1 8Replacing 2nd-tier ISAsSmaller proprietary-I

24、SA soft-core IP companies switching to RISC-V standard to access larger market:AndesCodasipCortusC-Skyothers to announceIf youre a softcore IP provider,you should have a RISC-V product in development1 9StartupsMany startups choosing RISC-V for new productsEsperanto announced 4,096-core 7nm RISC-V ch

25、ip, with high-end OoO coresFadu SSD controller announcementKendryte AI microcontroller, $3 chip with two RISC-V cores from open-source Rocket codebaseMost are stealthy so will not be visible for a whileWe havent had to tell startups about RISC-V; they find out pretty quickly when shopping for proces

26、sor IP2 0 Commercial Ecosystem ProvidersMainstream commercial ecosystem support rapidly appearing- Lauterbach, Micrium, Segger, IAR, Express Logic, Imperas, UltraSOC, AntMicro, Demand driving supply in commercial ecosystem2 1Government AdoptionIndia has adopted RISC-VUS DARPA mandated RISC-V in rece

27、nt security call for proposalsIsrael Innovation Authority creating GenPro incubator around RISC-VShanghai Municipal Govt supporting RISC-V companiesOther governments at various stages of investigationIf your country wishes to control security of its own information infrastructure, and promote its in

28、digenous semiconductor industry, support RISC-V2 2RISC-V in Education2 3RISC-V spreading quickly throughout curricula of top schoolsBooks available now! In multiple languages2 4ResearchEducationIndustryOpen ecosystem is key to keeping the virtuous cycle going RISC-V: Completing the Innovation CycleR

29、ISC-V ISA Tutorial2 5Whats Different about RISC-V?SimpleFar smaller than other commercial ISAsClean-slate designClear separation between user and privileged ISAAvoids architecture or technology-dependent featuresModular ISA designed for extensibility/specializationSmall standard base ISA, with multi

30、ple standard extensionsSparse &variable-length instruction encoding for vast opcode spaceStableBase and first standard extensions are frozenAdditions via optional extensions, not new versionsCommunity designedDeveloped with leading industry/academic experts and software developers2 6RISC-V Base Plus

31、 Standard ExtensionsFour base integer ISAsRV32E, RV32I, RV64I, RV128IRV32E is 16-register subset of RV32IOnly = 32)D = 64-bit double-precision IEEE FP (FLEN = 64)Q = 128-bit quad-precision IEEE FP (FLEN = 128)Q implies D, D implies FNon-destructive fused multiply-adds supportedNew instruction format

32、 with three sources and one destinationNarrower FP results are “NaN-boxed” to wider FP regsResult 1-extended to full FLEN width to avoid implementation-defined behavior, e.g., on RV64ID system, 32-bit FP result widened to FLEN=64 by filling upper 32 bits with all “1”s.Narrower results treated as NaN

33、 if incorrectly used as source to wider FP instructionVariable-Length EncodingExtensions can use any multiple of 16 bits as instruction lengthBranches/Jumps target 16-bit boundaries even in fixed 32-bit base-Consumes 1 extra bit of jump/branch address3 6“C”: Compressed Instruction ExtensionCompresse

34、d code important for:low-end embedded to save static code spacehigh-end commercial workloads to reduce cache footprintC extension adds 16-bit compressed instructions2-address forms with all 32 registers2-address forms with most frequent 8 registers1 compressed instruction expands to 1 base instructi

35、onAssembly lang. programmer & compiler obliviousAssembler and linker perform compression in current tool chains)RVC RVI decoder only 700 gates (2% of small core)All original 32-bit instructions retain encoding but now can be 16-bit aligned50%-60% instructions compress 25%-30% smaller3 738RV32I+ M, A

36、, F, D, Q, C+14Privileged+ 8 for M+ 11 for A+ 34for F, D, Q+ 46 for C+ 4 for64M/128M39RV32I / RV64I / RV128I + M, A, F, D, Q, C+ 12for 64I/128I+ 11 for64A/128A+ 6 for64F|D|Q/128F|D|Q40RV32I / RV64I / RV128I + M, A, F, D, Q, CRISC-V “Green Card”Simplicity breeds ContemptHow can simple ISA compete wit

37、h industry monsters?How do measure ISA quality?Static code bytes for programDynamic code bytes fetched for executionMicroarchitectural work generated for execution4 1100%141%131%129%169%80%100%120%160%180%RV64CRV64X86-64ARMv8MIPS6464-bit Address100%140%126%136%101%173%140%126%80%100%120%140%160%180%

38、32-bit AddressSPECint2006 compressed code size with save/restore optimization (relative to “standard” RVC)RISC-V now smallest ISA for 32- and 64-bit addressesAll results with same GCC compiler and options4 2Dynamic Bytes Fetched4 3RV64GC is lowest overall in dynamic bytes fetchedDespite current lack

39、 of support for vector operations Converting Instructions to MicroopsMultiple microinstructions from one macroinstruction Or one microinstruction from multiple macroinstructions4 4Microops are measure of microarchitectural work performedRISC-V Macro-Op Fusion Examples“Load effective address LEA” &(a

40、rrayoffset)slli rd, rs1, 1,2,3 add rd, rd, rs2“indexed load” Mrs1+rs2 add rd, rs1, rs2 ld rd, 0(rd)“clear upper word” / rd = rs1 & 0 xffff_ffffslli rd, rs1, 32 srli rd, rd, 32Can all be fused simply in decode stage-Many are expressible with 2-byte compressed instructions, so effectively just adds ne

41、w 4-byte instructionsRISC-V approach: use macroop fusion, dont grow ISA4 5RISC-V Competitive arch Effort after Fusion4 6Details in UCB 2016 TR and 4th RISC-V workshop talk by Chris CelioDave Ditzel, EsperantoRISC-V wasnt even on the shopping list of alternatives, but the more Esperantos engineers lo

42、oked at it, the more they realized it was more than a toy or just a teaching tool. “We assumed that RISC-V would probably lose 30% to 40% in compiler efficiency versus Arm or MIPS or SPARC because its so simple,” says Ditzel. “But our compiler guys benchmarked it, and darned if it wasnt within 1%.”A

43、rticle by Jim Turley, EE Journal, December 13, 20174 748 Fragmentation versus DiversityFragmentation:Same thing done different waysDiversity:Solving different problemsRISC-V Encoding TerminologyStandard: defined by the FoundationReserved: Foundation might eventually use this space for future standar

44、d extensionsCustom: Space for implementer-specific extensions, never claimed by Foundation4 9RISC-V Custom Extension Example5 0Standard RV32IMAFD SoftwareCustom SWLibrariesBase RV32IMAFDReservedCustomCustomedveresRRISC-V Custom Extension Example 25 1StandardRV32IMASoftwareCustom SW LibrariesBase RV3

45、2IMANon-Conforming ExtensionCustomCustomRISC-V Privileged ArchitectureThree privilege modesUser (U-mode)Supervisor (S-mode)Machine (M-mode)Supported combinations of modes:MM, UM, S, U(simple embedded systems) (embedded systems with protection)(systems running Unix-style operating systems)Hypervisors

46、 run in modified S mode (HS) (in progress)Prioritizes support for Type-2 Hypervisors like KVMCan also support Type-1 Hypervisors in same model5 2Simple Embedded Systems (M-mode only)No address translation/protection“Mbare” bare-metal modeTrap bad physical addresses preciselyAll code inherently trust

47、edLow implementation cost27 bits of architectural state (in addition to user ISA)- +27 more bits for timers- +27 more for basic performance counters5 3Secure Embedded Systems (M, U modes)M-mode runs secure boot and runtime monitorEmbedded code runs in U-modePhysical memory protection (PMP) on U-mode

48、 accessesInterrupt handling can be delegated to U-mode code-User-level interrupt supportProvides arbitrary number of isolated subsystemsOngoing work to define trusted execution environments5 4Device 2 InterruptsDevice 1InterruptsOtherInterruptsU-mode process 1U-mode process 2PMPPMPM-mode monitorVirt

49、ual Memory Architectures (M, S, U modes)Designed to support current Unix-style operating systemsSv32 (RV32)Demandd 32-bit virtual-address spaces2-level page table4 KiB pages, 4 MiB megapagesSv39 (RV64)Demandd 39-bit virtual-address spaces3-level page table4 KiB pages, 2 MiB megapages, 1 GiB gigapage

50、sSv48, Sv57, Sv64 (RV64)Sv39 + 1/2/3 more table levels5 5 S-Mode runs on top of M-modeM-mode runs secure boot and monitorS-mode runs OSU-mode runs application on top of OS or M-mode5 6Device 2 InterruptsDevice 1 InterruptsOther InterruptsU-mode appU-mode system processS-mode OSPMPPMPM-mode monitorHy

51、pervisorSupports Type-2 hypervisors (e.g., KVM) as well as Type-1 hypervisor (e.g., Xen)Current draft spec implemented in QEMU with early KVM portSupports recursive virtualization5 7RISC-V and SecuritySecurity is one of biggest challenges in contemporary computer architecture, so which to trust?Simp

52、le free ISA with open implementations and publicly scrutinized security systemsComplex proprietary ISAs with NDA-only security systemsRISC-V already the center of security architecture researchSmall set of hardware primitives support everything from embedded security to remote cloud enclaves5 8Foundation ISA Standards DevelopmentUnprivileged base and initial extensions now ratifiedRV32IMFDC, RV64IMFDC”A” extension has one minor issue to resolve (LR/SC progress)User ISA stable since 2014 releaseRun/halt debug spec ratifiedMemory model ratifiedPrivileged spec 1.11 ratifiedFormal m