MIPI技術(shù)及物理層測試的挑戰(zhàn)

MIPI

技術(shù)及物理層測試的挑戰(zhàn)–是德科技(Keysight)攜手MIPI聯(lián)盟和Synopsys共同推動MIPI技術(shù)發(fā)展內(nèi)容安排–

第一部?

MIPI

聯(lián)盟簡介、中國成員、規(guī)范框架以及未來走向–

第二部Synopsys

的

MIPI相關(guān)IP技術(shù)及其與UFS/SSIC/M-PCIe的互操作性–

第三部?

MIPI物理層發(fā)展規(guī)劃以及電氣特征測試方案MIPI聯(lián)盟—移動及相關(guān)產(chǎn)業(yè)的接口規(guī)范演講人MIPI聯(lián)盟-總經(jīng)理皮特.萊弗金Copyright

?

2013

MIPI

Alliance.

All

rights

reserved.MIPI

概述Copyright

?

2014

MIPI

Alliance.

All

rights

reserved.? MIPI聯(lián)盟是致力于發(fā)展移動及相關(guān)產(chǎn)業(yè)接口規(guī)范的國際組織– MIPI規(guī)范為移動手機及其他設(shè)備的運行提供基礎(chǔ)的接口解決方案– 現(xiàn)代的移動生態(tài)系統(tǒng)包括平板電腦、筆記本電腦、以及其他設(shè)備? MIPI聯(lián)盟成立于2003年，目前在世界范圍內(nèi)有275家企業(yè)成員– 企業(yè)成員包括：手機設(shè)備制造商、外圍設(shè)備制造商、軟件提供商、半導(dǎo)體公司、應(yīng)用程序處理器開發(fā)人員、知識產(chǎn)權(quán)提供商、測試和測試設(shè)備公司、相機、平板和筆記本電腦制造商。? MIPI有14個活躍的工作組– 模擬控制接口、電池接口、相機、調(diào)試、展示、低延遲接口、LML、市場營銷、實體、無線電頻、前端、傳感器、軟件及其同類、測試工作組以及UniPro? 聯(lián)盟已經(jīng)推行了超過45項移動生態(tài)系統(tǒng)規(guī)范? MIPI聯(lián)盟的戰(zhàn)略合作伙伴包括：– JEDEC,PCI-SIG?,MEMSIndustryGroup?,USB-IF,VESAMIPI聯(lián)盟的15家中國(包括香港)的成員包括還有36家來自臺灣的公司沒有列出Copyright

?

2014

MIPI

Alliance.

All

rights

reserved.我們將在上海舉行年度會議Copyright

?

2014

MIPI

Alliance.

All

rights

reserved.? MIPI聯(lián)盟開放與演示日將于10月9日(09:00–15:00)在上海舉行– 向所有的非會員、會員、媒體和分析師免費開放– 關(guān)于MIPI規(guī)范的演講（涉及物理層、傳感器、SoundWire、CSI以及DSI）– 演示日將與開放日同期舉行，現(xiàn)場將演示各種MIPI產(chǎn)品? 如果您對該活動感興趣，可通過以下網(wǎng)址在線注冊：/d/n4q5sqMIPI系統(tǒng)圖Copyright

?

2014

MIPI

Alliance.

All

rights

reserved.MIPI規(guī)范架構(gòu)包括：多媒體、數(shù)據(jù)/控制、跟蹤調(diào)試、芯片間的通信RFFE

-

RF

Front

EndeTrak

-

Envelope

Tracking

SPMI

-

Power

MgmtBIF

-

BatteryUFS

-StorageDSI

-DisplayCSI

-

CameraSLIMbus,

SoundWire-

AudioSPP

-

SneakPeek

ProtocolNIDnT

-

Narrow

Interfacefor

Debug

&

TraceTWP

-

TraceWrapper

ProtocolSTP

-

System

TraceProtocolUniPort-M

(UniPro

onM-PHY)LLI

–LowLatency

Interface

(onM-PHY)M-PCIe

–

Mobile

PCI

Express(PCIe

onM-PHY)SSIC

–

SuperSpeed

InterChip

(USB3

on

M-PHY)Copyright

?

2014

MIPI

Alliance.

All

rights

reserved.關(guān)于MIPI實體規(guī)范的新聞稿將于9月17日發(fā)布Copyright

?

2014

MIPI

Alliance.

All

rights

reserved.? MIPI聯(lián)盟推出MIPI

C-PHY與D-PHY的更新——新規(guī)范的發(fā)布將擴展MIPI聯(lián)盟為移動及相關(guān)產(chǎn)業(yè)應(yīng)用所提供物理層級規(guī)范的家族今天MIPI推出新的MIPI

C-PHY– 擴展了MIPI聯(lián)合會

的物理層級規(guī)范，拓寬了生產(chǎn)商們的接口選擇，同時也為公司基于特定商業(yè)策略或技術(shù)要求的差異化產(chǎn)品設(shè)計，提供了新的機遇– 專為程序處理器連接相機和顯示模塊設(shè)計? 更新了1.2版本的D-PHY以及3,1版本的M-PHY? 1.0版本MIPI

C-PHY

、1.2版本的D-PHY以及3,1版本的M-PHY現(xiàn)在對MIPI聯(lián)合會成員開放MIPI聯(lián)盟的未來——超越移動產(chǎn)業(yè)? 移動產(chǎn)業(yè)影響社會中的一切? 一切都變得更快、更小和更節(jié)能– MIPI聯(lián)盟將繼續(xù)研發(fā)規(guī)范，以充分利用移動設(shè)備技術(shù)的發(fā)展。Copyright

?

2014

MIPI

Alliance.

All

rights

reserved.總結(jié)Copyright

?2014

MIPI

Alliance.

All

rights

reserved.? 在2014～2015這兩年里，中國將成為MIPI聯(lián)盟的最新戰(zhàn)略重點地區(qū)，為更多想加入MIPI聯(lián)盟的中國公司提供機會，同時希望中國公司能夠在MIPI未來發(fā)展方向上做出貢獻。? MIPI聯(lián)盟將于10月9日在上海舉辦首個中國開放和演示日。―

屆時，將對所有提前在線注冊的MIPI會員和非會員，媒體，分析師以及相關(guān)企業(yè)、個人和業(yè)界專業(yè)人士免費開放。―

開放日將為MIPI的會員們提供一個公開交流的平臺和機會，并針對非會員和媒體設(shè)置了問答環(huán)節(jié)。? 我相信在未來，MIPI聯(lián)盟將會研發(fā)出更多先進的、更創(chuàng)新的標(biāo)準和規(guī)范。謝謝如需了解更多關(guān)于MIPI聯(lián)盟的常見問題以及會員申請等詳情，請按照以下方式聯(lián)系MIPI聯(lián)合會總經(jīng)理皮特.萊弗金先生。PeterLefkin–ManagingDirectorpeter.lefkin@Telephone:Copyright

?2014

MIPI

Alliance.

All

rights

reserved.–

第一部?

MIPI

聯(lián)盟簡介、中國成員、規(guī)范框架以及未來走向–

第二部Synopsys

的

MIPI相關(guān)IP技術(shù)及其與UFS/SSIC/M-PCIe的互操作性–

第三部?

MIPI物理層發(fā)展規(guī)劃以及電氣特征測試方案內(nèi)容安排Synopsys

DesignWare

MIPI

IPHaopeng

LiuSeptember,17,201414Application

ProcessorBaseband

ICDesignWare

MIPI

IPConnectivity

IP

Between

Various

ICsDSI2G/3G

RFICDigRF

3GSlaveDigRF3GDigRF

v4Master4G

RFICDigRF

v4SlaveDigRFv4M-PHYLLIM-PHYM-PHYM-PHY3G

PHYCSI-2HostDSIHostD-PHYD-PHYLLILLIDigRF

3GMaster3G

PHYSSIC

\M-PCIeHostM-PHYCompanion

ICM-PHYSSIC

\M-PCIeDeviceM-PHYStorage

ICSSICM-PCIeUFSUniProUFSHostCSI-2UniProUFSDeviceImage

SensorD-PHYCSI-2DeviceDisplayD-PHYDSIDeviceM-PHYCurrent

portfolioM-PHYSSIC

/M-PCIeDeviceSSIC

//M-PCIeHostM-PHYSSICM-PCIeM-PHYARA

ModuleUniPort-MUniProUniProApplicationM-PHYApplicationOptimizedandFlexible

D-PHYSupports

2.5G

speeds,

?

the

area

and

powerD-PHY

v1.2

specification2.5Gbps/lanePower,

Area

andPerformanceOptimizedVarietyofconfigurationsDSI

Host,

CSI2

DeviceCSI2

Host,

DSI

DeviceDifferent

#of

data

lanes

availableInteroperable

and

Integratedwith

SynopsysCSI2and

DSIcontrollersLowrisk

and

quicktime

to

marketAvailable

in

16nm

and

28nmRxD-PHYPPIInterfaceBlockPPIInterfaceBlockD-PHYw/

PLLTx

D-PHYRxD-PHYDSI

HostCSI2

DeviceCSI2

HostDSI

DeviceDesignWare

UFSv2.0

for

Mobile

AppsFuture

Proof,

Interoperable

Host

and

Device

SolutionFuture

ProofM-PHY,

UFS

IPPower

ModesCompact

andConfigurableHost

and

DeviceCustomersPrototypingSystemDeployedSource:

Samsungpresentation,

JEDECMobile

Forum

May

2013UFSSoftware

DriversLinux,

OS-lessUFS

Host

v2.00Fully

Verified,

Gear3UniPro

v1.60Fully

Verified,

FlexibleDin C C Dout

RMMISilicon-Proven

M-PHY

HS-Gear3

BSynopsys

M-PHY

Interoperablew/

UFS,

SSIC,

M-PCIeM-PCIe

Controller

andMIPI

Gear3

M-PHYCompliant

USB

SSICwith

M-PHYInteroperable

withTWO

differentUFSdevices內(nèi)容安排–

第一部?

MIPI

聯(lián)盟簡介、中國成員、規(guī)范框架以及未來走向–

第二部Synopsys

的

MIPI相關(guān)IP技術(shù)及其與UFS/SSIC/M-PCIe的互操作性–

第三部?

MIPI物理層發(fā)展規(guī)劃以及電氣特征測試方案MIPI

物理層測試的挑戰(zhàn)–李凱測試主題的內(nèi)容安排MIPI

物理層的發(fā)展MIPI

物理層的電氣特點物理層測試的挑戰(zhàn)以及測試方案?

發(fā)送端的測試?

接收端的測試?

回波損耗的測試總結(jié)Our

solutions

aredriven

and

supported

by

Agilent

expertsinvolved

in

international

standards

committees:JointElectronic

Devices

Engineering

Council

(JEDEC)PCISpecialInterest

Group

(PCI-SIG?)VideoElectronics

Standards

Association

(VESA)Serial

ATA

International

Organization(SATA-IO)Serial

Attached

SCSICommittee

(T10)USB-Implementers

Forum

(USB-IF)Mobile

IndustryProcessor

Interface

(MIPI)

AllianceOptical

CommunicationsAndmany

othersWe’re

active

in

standard

meetings,

workshops,

plugfests,and

seminars.We

get

involved

so

you

benefit

with

the

right

solutions

whenyou

need

themKeysight

的標(biāo)準跟蹤和應(yīng)用項目計劃Jim

ChoateUSB-IF

Compliance

CommitteeUSB

3.0

Electrical

Test

SpecWGRick

EadsPCI-SIG

BoardMemberBrian

FetzDisplayPort

PhyCTS

EditorVESA

Board

MemberKeysight

maintains

engagement

in

the

top

high

techstandards

organizationsPerry

KellerJEDECBoardMemberThomas

DipponHDMI

Forum

BoardMemberMin-Jie

ChongSATA

PHY/LOGO,

SAS

T10,MIPI

PHY/CTSContributorKeysight

的專家團隊-我們理解您未來的需求UniProUFSPhysicalStandardProtocolStandardDigRF v3

D-PHYC-PHYCSI-2DSI-1DigRFv4M-PHYApplicationDSI-2CSI-3MIPI

的物理層、協(xié)議層以及承載的應(yīng)用LLISSIC M-PCIeMIPI

物理層標(biāo)準的最新變化M-PHY

Gear

4Double

the

data

rate

ofM-PHY

Gear3

(~5.8Gbps)Data

rate

will

increaseto

~11.6GbpsVariable

M-PHY

data

rateCurrentfixed

rate

is

inefficientand

high

overheadD-PHY

1.2

and

2.0Increasedata

rate

from

1.5Gbps

up

to

3.5GbpsAdd

RX

deskew(burden

at

RX)Support

up

to

8

lanes

per

clockC-PHY

(previously

known

as

3-Phase

D-PHY)3-wiresignal

architecture,

vs.2-wiredifferential

used

in

D-PHYIncreasethe

numberofbits

persymbol

(~2.28

bit/symbol)Projected

rate

at2.5GSym/s

(effective

data

rate

of~5.7Gbps)測試主題的內(nèi)容安排MIPI

物理層的發(fā)展MIPI

物理層的電氣特點物理層測試的挑戰(zhàn)以及測試方案?

發(fā)送端的測試?

接收端的測試?

回波損耗的測試總結(jié)High

speedmode,Differential

signaling,

100ohm

termination,source

synchronous

with

double

data

rate

clockingLowpower

modeUnterminated,

not

differential,

clockembedded

within

dataD-PHY

物理層的特點高速模式和低功耗模式M-PHY

物理層的特點高速模式和低速模式High

Speed

NRZ

(HS)

and

Lower

Speed

(LS)

modes-

Common

LSmode:

Pulse

Width

Modulation

(PWM)Always

differential

and

8b/10b

codedHigh

and

low

voltage

swing

operationsTerminated

(100

ohm)

or

not

terminated

operationPWM

SchemeRTRTTXDPTXDNRXDPRXDN

TerminationsZHIZHIVLDRTRTTXRXC-PHY

物理層的特點曾被稱為

3相

D-PHY3-wire

(trio

A,

B,

C)

signal

represents

a

lanevs.

2-wire

in

D-PHYNew

encoding

scheme

to

increase

the

number

of

bits

per

symbol(~2.28bit/symbol)Embeddedclockrecovered

from

each

symbol

transitionSignal

is

transmitted

single-ended

but

received

using

differential

receiversReuse

LP

mode

defined

in

D-PHYD-PHY

10-wire

signalsC-PHY

9-wire

signals

(3-trios)C-PHY

的信號特點高速信號的波形Transmit:

A,

B

and

CReceive:

A-B,

B-C

and

C-AC-PHY

的眼圖和模板高速信號測試Clock

is

recovered

from

the

earliest

edge

of

a

symbol

transition.Adelay

circuit

withnegative

hold

time

isused

tosample

data.Supposed

tobemore

resistant

tonoise

and

jitter

on

thesystem.31Strong-1Weak-10V

thresholdWeak-0Strong-0C-PHY

測試中還有待解決的一些問題Whatarethe

jitter

and

eye

maskdefinitions?Availability

ofdynamic

termination

board

requiredfor

TX

test

and

calibration

ofthe

RX

stresssignal.Whatarethe

test

patterns

to

use

for

test?How

iserrordetection

achieved

since

no3-wireED

(errordetector)isavailable?Implement

error

counter

inDUT

and

provide

side-bandinterface

for

error

read-outWhatisthe

rightfigureofmeritinstead

ofBERforRX

test?內(nèi)容安排MIPI

物理層的發(fā)展MIPI

物理層的電氣特點物理層測試的挑戰(zhàn)以及測試方案?

發(fā)送端的測試?

接收端的測試?

回波損耗的測試總結(jié)發(fā)送端測試的挑戰(zhàn)Test

boarddesign

forchipsetDynamic

terminations

between

operation

modesProbe

noise,

response

and

loadingHuge

list

ofconformance

test

requirementMultilane

testingwith

oscilloscope

limited

channelsRemoving

test

setuploss

from

measurementCorrelating

physical

and

protocol

issues適用于芯片、模組測試的測試板TestVehicle

Board

(TVB)TVB/mipi-

testing/workspace/StartPagePHYChip不同工作模式下的動態(tài)端接Reference

Termination

Board

(RTB)Reference

Termination

Board(RTB) terminates

the

signalsdynamically

according

to

theoperation

terminationrequirement.D-PHY

and

C-PHY

RTB,

as

wellas

fixedM-PHY

loadboard

areavailable./services/

testing/mipi/fixtures.phpPHYChipTVBRTBSMAProbe探頭的噪聲、頻響和負載影響PaProbeswith

low

noise

andloading

(as

low

as

70

fF)are

available.S-parameter

stored

in

the

probe

amplifier.PrecisionProbe

can

be

used

for

ACcalibration.Flexible

probe

accessories:o

Solder-in

probe

head

o

ZIF

probe

andtipsSocket

headBrowser2.92mm/SMA

headExample

25

GHzZIFprobe

andtipInfiniiMax

ProbesMIPI

信號的探測方法–

D-PHY

andC-PHY

probing

option:1. Solder

down

on

dynamic

load

(50-ohm

and

open)–

M-PHY

probing

options:Solder

down

on

100-ohm

differential

loadDirectconnection

intoscopeSMA

probe

head–

Notes: Direct

DC

connection

is

recommended

if

it

doesn’timpact

transmitter

performance

bycomparing

resultsbetween

DC

(without

cap)

and

AC(with

cap)

connections.

Ifperformance

decreases,

use

SMA

probe

head.M-PHY

HS-G3

的信號測試對比測試條件：發(fā)送端沒有預(yù)加重，沒有傳輸通道Direct

AC-coupled

intoscopefront-endDirect

DC-coupled

intoscopefront-endInfiniiMaxII

1169A

SMAProbeInfiniiMaxIII

N2800A

SMAProbeM-PHY

HS-G3

的信號測試對比測試條件：發(fā)送端沒有預(yù)加重，

經(jīng)過CH1參考通道InfiniiMax

IIIN2800A

SMA

ProbeDirect

AC-coupled

intoscopefront-endDirectDC-coupled

intoscopefront-endInfiniiMax

II

1169A

SMA

Probe大量的一致性測試項目Electrical

TransmitterSignal

GroupTest

ParametersHSClockPHigHh-YSpeed

ClockElectrical

TransmitterCharacteristicsStatic

Common

Mode

Voltage

(Vcmtx)Vcmtx

MismatchDifferential

Voltage(VOD)Differential

VoltageMismatchSingle-Ended

Output

High

Voltage

(VOHHS)Common-Level

Variations

Above

450MHz

(VCMTX(HF))Common-Level

Variations

Between

50-450MHz

(VCMTX(LF))20%-80%

Rise

Time

(tR)20%-80%

Fall

Time

(tF)HS

DataHPigHh-SYpeed

DataCharacteristicsStatic

Common

Mode

Voltage

(Vcmtx)Vcmtx

MismatchDifferential

Voltage(VOD)Differential

VoltageMismatchSingle-Ended

Output

High

Voltage

(VOHHS)Common-Level

Variations

Above

450MHz

(VCMTX(HF))Common-Level

Variations

Between

50-450MHz

(VCMTX(LF))20%-80%

Rise

Time

(tR)20%-80%

Fall

Time

(tF)Signal

GroupTest

ParametersLP

Clock

/Data

PHYLP

TX

ElectricalCharacteristicsThevenin

Output

HighVoltage

Level

(VOH)Thevenin

Output

LowVoltage

Level

(VOL)30%-85%

Post-EoT

Rise

Time

(TREOT)15%-85%

Fall

Time

(TFLP)15%-85%

Rise

Time

(TRLP)Pulse

Width

of

LP

TX

Exclusive-ORClock(TLP-PULSE-TX)Periodof

L

TX

Exclusive-ORClock

(TLP-PER-TX)SlewRateVs.CLoadLP-HSDataTimingGlobal

Operation

forDataSignalsTLPXLP

Exit:

DATA

TX

THS-PREPARELP

Exit:

DATA

TX

THS-PREPARE+THS-ZEROHS

Exit:

DATA

TX

THS-TRAILHS

Exit:

DATA

TX

TEOTHS

Exit:

DATA

TX

THS-EXITLP-HSClockTimingGlobal

Operation

forClockLP

Exit:

CLK

TX

THS-EXITLP

Exit:

CLK

TX

TLPXLP

Exit:

CLK

TX

TCLK-PREPARELP

Exit:

CLK

TX

TCLK-PREPARE+TCLK-ZEROLP

Exit:

CLK

TX

TCLK-TRAILHS

Exit:

LK

TX

TEOTHS

Clock-Data

TimingHS

Data-Clock

TimingHSClock

Instantaneous

(UIinst)HSClockRising

Edge

Alignments

toFirst

Payload

BitData-to-Clock

Skew

(TSKEW(TX))D-PHY

物理層測試時間參數(shù)測試MIN:

50nsMAX:35ns+4*UIMIN:

40ns

MIN:MAX:

100ns55ns+4*UIMIN:max{n*8*UI,60ns+n*4*UI}MAX:105ns+n*12*UIn=1

forwarddirection

HS

moden=4

backward

direction

HS

modeUI:1GB/s=

1nsMIN:40ns+4*UIMAX:85ns+6*UIMIN:145ns+10*UI-THS-PrepareMAX:35ns1GB/s:

UI=1nsHS-PREPARE:MIN:

44nsMAX:91nsHS-ZERO:MIN:

64ns

=

145ns+10*1ns-91nsM-PHY

CTSv3.0r14

要求的高速信號的測試項目HS-TX

TestsHS-G1HS-G2HS-G3BurstContinuousLASARTNT1.1.1

f_OFFSETYesYesYesYesYesYesNoYesNo1.1.2

PSDCMInfoNoNoYesNoYesYesYesNo1.1.3

PREPARE_LengthYesYesYesYesNoYesYesYesNo1.1.4

VCMYesYesYesYesNoYesYesYesNo1.1.5

VDIF_DCYesYesYesYesNoYesYesYesNo1.1.6

G1/G2

TEYE_TX,VDIF_ACYesYesNoYesYesYesYesYesNo1.1.7

G3TEYE_TX,

VDIF_ACNoNoYesYesYesYesYesYesNo1.1.8

TR_TF_HSYesYesYesYesNoYesYesYesNo1.1.9

L2L_SKEWYesYesYesYesNoYesNoYesNo1.1.10SR_DIF[MAX]YesNoNoYesNoYesYesYesNo1.1.10SR_DIF[MIN]YesNoNoYesNoYesYesYesNo1.1.11SR_DIFMonotonicityYesNoNoYesNoYesYesYesNo1.1.12?SR_DIFResolutionYesNoNoYesNoYesYesYesNo1.1.13TINTRA_SKEWYesYesYesYesOptionalYesYesYesNo1.1.14TPULSEYesYesYesYesNoYesYesYesNo1.1.15TJYesYesYesNoYesYesYesYesNo1.1.16STTJYesYesYesInfoYesYesYesYesNo1.1.17DJYesYesYesNoYesYesYesYesNo1.1.18STDJYesYesYesInfoYesYesYesYesNoM-PHY

眼圖和抖動的測試Node-emphasis

in

G1

and

G2.

G3

requires

de-emphasis.Nominal

3.5dB

de-emphasis

for

LA

and

SA

swingNominal

6dB

de-emphasis

for

LA

swingG4

requires

CTLE

and

one-tap

DFE

at

receiver.Different

BER

1E-10

eye

mask

definition

for

G1,

G2

and

G3.G4

leverages

G3

reference

channels

and

also

to

include

reference

packagemodel.TJ,

DJ,STTJ

andSTDJarenormative

withcontinuous

signal.

DJ

andSTDJareinformative

withburst

using

TIEpp

method.G1

–

0.2UI

opening

between

0.4-0.9UINo

channel0.2UI

eye

opening

at0.5UINo

channelDiamond

mask

at

0.5UIEmbed

CH1–

SA

and

CH2–

LA

swingC-PHY

物理層的測試大量的時間參數(shù)測試–

–來源于D-PHY但又不太一樣Rise/fall

timemeasured

between

-58mVto58mVthresholds

onS-Wtransitions.

W-Wtransitions

are

slowest,

but

S-Ware

criticaltoeye-opening.Eye

maskdefined

atthe

receiver.Embed

6-port

model

–IL/RL

and

CTLE,aswell

asXtalk

from

adjacent

channels.Jitter

still

undefined.Common

point

replaces

common

mode

test.C-PHY

上升/下降時間、眼圖和抖動的測試自動的信號一致性測試軟件Configure

theDevice

Under

TestSelect

Tests.Automatically

generatetest

report.多通道測試Limited

oscilloscope

channels

prevent

full

automatedtesting

of

multilane

MIPI

interface.Overcome

with

switch

matrix,

which

automates

laneswitching

and

test.Switch

matrix

calibration

to

remove

loss

and

skew.2x6

(1x6

differential)Switch

MatrixAgilent

U3020AS264

differential

lanesconfiguredDSA

90000

X-Series16GHz

AgilentOscilloscope消除測試電纜、探頭損耗帶來的影響Computed

insertionlossgain

function

based

onmeasured

S21

(Yellow)Original

signalfrequencycontent

(green)Frequency

content

withlosscompensationapplied

(Blue)使用示波器和矢網(wǎng)的去嵌入功能(InfiniiSim)

或者示波器的TDT修正功能(PrecisionProbe)物理層和協(xié)議層的聯(lián)合調(diào)試在示波器里進行MIPI的協(xié)議解碼

(舉例：

UFS/

UniPro)Simultaneousshow

UFS

andUniPro

packetdecode

onanalogwaveform.Move

back

andforth

betweenUFS

and

UniPropacketsShowswhether

thebits

arecorrectlyreceivedwiththe

CRCverification.通過CRC校驗進行物理層和協(xié)議層的聯(lián)合調(diào)試Calm

colorshows

the

packetsarereceived

correctly

with

no

error

whenthe

computed

CRC

matchesCRCtransmitted

in

the

packet.Signalintegrity

andprotocol

are

good.Brightcolor

warns

the

packetsarereceived

incorrectly

when

thecomputed

CRC

andCRC

transmittedin

the

packet

do

not

match.

This

couldbe

related

tosignal

integrity

orprotocol

issues.User

can

go

in

todebug

the

issues.測試主題的內(nèi)容安排MIPI

物理層的發(fā)展MIPI

物理層的電氣特點物理層測試的挑戰(zhàn)以及測試方案?

發(fā)送端的測試?

接收端的測試?

回波損耗的測試總結(jié)接收端的測試Stressed

Signal

GeneratorRJDJISIRxChipTxLoop

BackRJR+JDR+JJD+JISIErrorDetectorStressed

SignalJitter

CocktailISI接收端測試的挑戰(zhàn)Receiver

stress

signal

generationVarious

timingrequirementsComplex

jittercocktailProgramming

designs

into

test

modesNo

standardization

inthePHY

specMethod

varies

by

the

protocolError

detection

with

different

protocolsNo

standardizationSpecific

method

defined

inprotocol

spec,

not

inPHYspecNot

mandatory

(optional

normative

/

recommendation)Asymmetrical

lane

configurationCustomTest

BoardTPISI

Conformance

ChannelBERTPatternGeneratorw/

TTCsBreakout

TraceASICRXDUTTXRefClkInternal

Loopbackor

Error

counterReplica

TraceM-PHY接收端測試的連接產(chǎn)生壓力信號并根據(jù)CTS要求進行校準535mm580mm45mm100

OhmDifferentialProbeRT-OscilloscopeTestboard

with

Replica

Tracescreating

testpoint

(TP)

for

calibrationequivalent

tothe

ASIC-input

pins使用M8020A進行M-PHY接收端測試的連接1:1

matchofCTS

proposed

set-up

with

actual

Agilent

J-BERT

set-upISI

conformance

channel

relaized

through

N4915

60001

SATA

ISI

trace

(2)RT-OscilloscopeJ-BERT

M8020A100

OhmDifferentialProbeloopRX

backErrCtrM-M-TXN4915-60001D-PHY

接收端測試的典型配置需要通過合路的方式同時產(chǎn)生HS和LP的信號DUT舉例：支持1對時鐘線和2對數(shù)據(jù)線的基于81250的配置產(chǎn)生D-PHY的壓力信號的例子C-PHY接收測試設(shè)置

(One

Trio)Two

M8190A

AWG

modules

+

one

M8192A

sync

module

isneeded

to

drivethe

four

signalsM8190A

AWG

isflexibleenough

to

support

C-PHYwaveforms

without

external

circuitryABCOnly

3

of

4

available

channelsneededto

drive

a

C-PHX

laneDABCD4th

channel

available

for

any

aux

signal1Gsym/s的C-PHY信號－LP和HS狀態(tài)的切換Sequence

of

lowpowerand

hispeed

signalseparated

(offset-shifted,

left)

andoverlaid

(sameoffset,

right)眾多的的接收容限測試項目CTSchapterTitleATHS-mode2.1.1HS-RXDifferential

DC

Input

Voltage

Amplitude

Tolerance2.1.2HS-RX

Accumulated

Differential

Input

Voltage

Tolerance2.1.3HS-RXCommon

Mode

Input

Voltage

Tolerance2.1.4HS-RXDifferential

Termination

Enable

Time2.1.5HS-RXDifferential

Termination

Disable

Time2.1.6HS-RXLane-to-Lane

Skew

(TL2L-SKEW-HS-RX)-2.1.7HS-RXReceiver

Jitter

Tolerance2.1.8HS-RXFrequency

Offset

Tolerance2.1.9HS-RXPREPARE

Length

Capability

Verification2.1.10HS-RXSyncLength

Capability

VerificationLS-mode(PWM)2.2.1PWM-RX

Differential

DC

Input

Voltage

Amplitude

Tolerance2.2.2PWM-RX

Accumulated

Differential

Input

Voltage

Tolerance2.2.3PWM-RX

Common

Mode

Input

Voltage

Tolerance2.2.4PWM-RX

Differential

Termination

Enable

Time2.2.5PWM-RX

Differential

Termination

Disable

Time2.2.6PWM-RX

Lane-to-Lane

Skew

(TL2L-SKEW-PWM-RX)-2.2.7PWM-RX

Receive

BitDuration

Tolerance2.2.8PWM-RX

Receive

Ratio,PWM-G1

and

Above2.2.9PWM-RX

Receive

Minor

Duration

inPWM-G0-Parameters

of

selected

itemCalibrationsHS,

NRZ

(RT)LP,

PWM

(NT)RX

testsHS,

NRZ

(RT)LP,

PWM

(NT)N5990A接收容限自動測試軟件M-PHYpacketframing把被測件設(shè)置成測試模式的方法使用芯片廠商方法或通過總線協(xié)議

(帶幀結(jié)構(gòu))M-PHY

的數(shù)據(jù)幀生成軟件支持81250并行誤碼儀和N4903B串行誤碼儀基于M-PHY協(xié)議的錯誤檢查Challenges

withdifferent

protocols:No

standardizationSpecific

method

defined

in

protocol

spec,

not

in

PHY

specNot

mandatory

(optional

normative

/recommendation)Asymmetrical

lane

configuration