EDA實驗四簡單數(shù)字電子系統(tǒng)的設計7284

EDA實驗四簡單數(shù)字電子系統(tǒng)的設計一、教學目的:1.熟練掌握元件例化語言2.學會用模塊化的設計方法進行數(shù)字電子系統(tǒng)的設計3.理解自頂向下設計的設計方法4.熟練掌握硬件仿真測試的方法二、教學內(nèi)容：1.設計一個32位二進制計數(shù)器2.設計一個8位數(shù)碼掃描顯示電路3.用元件例化語句將計數(shù)器和數(shù)碼掃描顯示電路組成簡單數(shù)字電子系統(tǒng)4.將此電子系統(tǒng)下載到硬件進行仿真測試三、教學重點:1.用VHDL語言設計一2.用VHDL語言設計一個8位數(shù)四、教學難點：個32位二進制計數(shù)器并進行功能仿真碼掃描顯示電路用元件例化語句將計數(shù)器和數(shù)碼掃描顯示電路組成簡單數(shù)字電子系統(tǒng)五、教學方法：講解、多媒體演示六、教學過程：實驗內(nèi)容：元件例化語句將計數(shù)器和數(shù)碼掃描顯示電路組成簡單數(shù)字電子系統(tǒng)1、32位二進制計數(shù)器2、8位數(shù)碼掃描顯示電路3、元件例化語句將計數(shù)器和數(shù)碼掃描顯示電路組成簡單數(shù)字電子系統(tǒng)4、下載測試實驗參考程序：1、32位二進制計數(shù)器libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycount32isport(clk:instd_logic;over:outstd_logic;--ò?3?D?o?point:outstd_logic_vector(7downto0);data32:outstd_logic_vector(31downto0));endcount32;architectureBehavioralofcount32issignaltemp:std_logic_vector(31downto0);beginprocess(clk)beginifclk'eventandclk='1'thentemp<=temp+1;endif;endprocess;data32<=temp;over<='0';point<=(others=>'0');endBehavioral;2、8位數(shù)碼掃描顯示電路libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityledisport(clk_led:instd_logic;overclosepoint:instd_logic;:instd_logic_vector(7downto0);:instd_logic_vector(7downto0);data32:instd_logic_vector(31downto0);duanwei:outstd_logic_vector(7downto0);:outstd_logic_vector(7downto0));endled;architectureBehavioralofledissignalmux8:std_logic_vector(2downto0);signaldata4:std_logic_vector(3downto0);beginp1:process(clk_led)beginifclk_led'eventandclk_led='1'thenmux8<=mux8+1;endif;endprocessp1;p2:process(mux8,over)beginifover='1'thenwei<="01111111";elsecasemux8iswhen"000"=>ifclose(0)='0'thenwei<="11111110";elsewei<="11111111";endif;data4<=data32(3downto0);duan(7)<=point(0);when"001"=>ifclose(1)='0'thenwei<="11111101";elsewei<="11111111";endif;data4<=data32(7downto4);duan(7)<=point(1);when"010"=>ifclose(2)='0'thenwei<="11111011";elsewei<="11111111";endif;data4<=data32(11downto8);duan(7)<=point(2);when"011"=>ifclose(3)='0'thenwei<="11110111";elsewei<="11111111";endif;data4<=data32(15downto12);duan(7)<=point(3);when"100"=>ifclose(4)='0'thenwei<="11101111";elsewei<="11111111";endif;data4<=data32(19downto16);duan(7)<=point(4);when"101"=>ifclose(5)='0'thenwei<="11011111";elsewei<="11111111";endif;data4<=data32(23downto20);duan(7)<=point(5);when"110"=>ifclose(6)='0'thenwei<="10111111";elsewei<="11111111";endif;data4<=data32(27downto24);duan(7)<=point(6);when"111"=>ifclose(7)='0'thenwei<="01111111";elsewei<="11111111";endif;data4<=data32(31downto28);duan(7)<=point(7);whenothers=>wei<="11111111";endcase;endif;endprocessp2;p3:process(data4,over)beginifover='1'thenduan(6downto0)<="0000110";elsecasedata4iswhen"0000"=>duan(6downto0)<="0111111";when"0001"=>duan(6downto0)<="0000110";when"0010"=>duan(6downto0)<="1011011";when"0011"=>duan(6downto0)<="1001111";when"0100"=>duan(6downto0)<="1100110";when"0101"=>duan(6downto0)<="1101101";when"0110"=>duan(6downto0)<="1111101";when"0111"=>duan(6downto0)<="0000111";when"1000"=>duan(6downto0)<="1111111";when"1001"=>duan(6downto0)<="1101111";when"1010"=>duan(6downto0)<="1110111";when"1011"=>duan(6downto0)<="1111100";when"1100"=>duan(6downto0)<="0111001";when"1101"=>duan(6downto0)<="1011110";when"1110"=>duan(6downto0)<="1111001";when"1111"=>duan(6downto0)<="1110001";whenothers=>duan(6downto0)<="0000000";endcase;endif;endprocessp3;endBehavioral;2、頂層程序libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycountledisport(oe,er:outstd_logic_vector(3downto0);clk:instd_logic;clk_led:instd_logic;close:instd_logic_vector(7downto0);wei:outstd_logic_vector(7downto0);duan:outstd_logic_vector(7downto0));endcountled;architectureBehavioralofcountlediscomponentcount32port(clk:instd_logic;over:outstd_logic;point:outstd_logic_vector(7downto0);data32:outstd_logic_vector(31downto0));endcomponent;componentledport(clk_led:instd_logic;overclosepoint:instd_logic;:instd_logic_vector(7downto0);:instd_logic_vector(7downto0);data32:instd_logic_vector(31downto0);duanwei:outstd_logic_vector(7downto0);:outstd_logic_vector(7downto0));endcomponent;signalt0:std_l