電子設(shè)計(jì)自動(dòng)化中英文對(duì)照外文翻譯文獻(xiàn)

中英文對(duì)照外文翻譯文獻(xiàn)(文檔含英文原文和中文翻譯)ElectronicDesignAutomationEDA(ElectronicDesignAutomation)technologyisanewtechnologyofthemodernfieldofelectricalengineering,whichprovidescomputer-basedinformationtechnologyandthemethodsofcircuitdesign.EDAtechnologydevelopmentandapplicationofgreatlypromotedthedevelopmentoftheelectronicsindustry.WiththedevelopmentofEDAtechnology,hardwaredesignofelectroniccircuitscanrelyonalmostallcomputerstoaccomplish,thusgreatlyshorteningthecycleofhardwareelectroniccircuitdesign,enablingmanufacturerstoquicklydevelopavarietyofsmallquantitiesofproductstomeetthemarketdemand.EDAtechnology,thebasicideaisthehelpofcomputers,theEDAsoftwareplatformtocompleteelectroniccircuitdesign,simulationandPCBdesignoftheentireprocess.Formorecomplexcircuits,ifnecessary,canbeusedtoimplementprogrammablelogicdevices.EDAtechnologynotonlyontheElectronicCourseandanalysisofsimulationexperimentstoaddressthevarietyoflaboratorycomponents,specificationsandquantityrestrictionsarenotsufficienttoavoiddamagetothestudentsinthelabcomponentsanddevicestostimulateinterestinlearning,todeveloptheiranalysis,electronicproductdesignanddevelopmentability,butalsoe-workerstodesign,developapowerfultoolforelectronicproducts.ThinkingofEDAtechnologyeducationandindustrypromotionisatechnologyhotspotintoday'sworld,EDAtechnologyisindispensableinthemodernelectronicsindustrytoatechnology.EDAtechnologyhasabroadmeaning,butalsoaprogressivedevelopmentofthefieldhasastrongvitality.Today'sEDAtechnologyhasreacheda"systemonachip"(SOC,SystemOnChip)stage.DeveloperscanusethepowerfulEDAdesignsoftware,theuseofIP(IntellectualProperty)IPcore,coupledwithhisinnovativethinking,andbuildtheirowncustomchips,whichhavetheirownIPrightstodesignspecificintegratedcircuit(ASIC,ApplicationSpecificIC.)EDAtechnologyinthepopularityofteaching,practicalapplicationsbasedonprogrammabledevicetechnology,whichincludesfourbasicconditions:①large-scaleprogrammabledevices,itistheuseofEDAtechniquescarrierelectronicsystemdesign;②hardwaredescriptionlanguageItistheuseofEDAtechnologiesforelectronicsystemdesign,themainmeansofexpression;③softwaredevelopmenttools,itistheuseofEDAtechnologiesforintelligentelectronicsystemdesignautomationdesigntools.④experimentaldevelopmentsystem,whichistheuseofEDAtechnologyforelectronicsystemsDownloadtoolsandhardwaredesignverificationtools.ProgrammableLogicControl(CPLD/FPGA)Inourdesign,wewasselectedCPLD/FPGA,ascomparedwiththetraditionalMCUhasmanyadvantages,mainlyinthefollowingareas:①advancedprogrammingveryeasy.CPLD/FPGAproducts,partofthedaisychainin-systemprogrammingmode.Thisadvancedmethodofprogramminghasbecometheworld'sdevelopmenttrendofvarioustypesofprogrammabledevices.Becauseitobviatestheexpensiveandinconvenientoperationdedicatedprogrammer,justneedtodownloadaverysimpleprogrammingcircuitandaPC,printercommunicationcableontheline.Itisnotprogrammedpressure,theTTLlevellinecanbeprogrammedatanytime,andtheso-calledmulti-chipdaisychainserialprogramming.Itsprogrammingupto1milliontimes,suchasLattice'sislesandAMD'sMACHfamily.Inaddition,programmingcaneasilyachieveinfrared,ultrasonicorradioprogrammingprogrammer,orthroughthetelephonelineremoteonlineprogramming.Thesefeaturesareincommunicationdevicesandmilitaryspecialpurposedevices.②highspeed.CPLD/FPGAclockdelayofuptonslevel,combinedwiththeparallelwork,intheultrahigh-speedreal-timemonitoringandcontrolapplicationsandhasaverybroadapplicationprospects.IfyouusetheFLEX10K50ALTERAdevelopmentnetworkimagethroughUSBinterface,real-timeencryption/decryptionASICsystem,carriedoutinFLEX10K50upto56-bitparallelbinaryarithmetic,eachencryption/decryptioncycleofonlyafewμs,andtheMCUtakesnearly1minute.AnotherexampleisinthemoldmanufacturingEDMprocessing,motorcontrol,theeffectiveoperationoftheprocessingpartsfromonlyafewμs,whichisrequiredforthecontrolofsensitiveandhigh-speedcircuitfeedingservice,notashortcircuitorarcingislessthanthebreakdown.Obviously,thiswork,MCUisdifficulttodirectlyparticipate.IfdirectfeedingbyispLSI1032servicecontrol,feedingontheclosed-loopmotorspeedservice,theuseofsamplingispLSIdirectcontroloftheAD1674,8-bitaccuracyusingamaximumspeedof8μs/each,inordertoachieveagoodclosed-loopspeedcontrolofsynchronousand.③highreliability.Inhighreliabilityapplications,MCU'sshortcomingsasaCPLD/FPGAapplicationleftalotofuseless.AlthoughthefunctionofthisgroupdevelopedthedeviceisachievedthroughtheEDAsoftware.Butthephysicalmechanismlikea74LS164aspurelyahardwarecircuitisveryreliable.Throughtherationaldesignofmostapplications,noneedtoconsiderthecomplexresetandinitialization.Designusingasimplestatementjustidleinitialentryintothesame,wecaneffectivelypreventanypossible"death"phenomenon.Becauseitisworkinginparallel,itcanbeusedaseitherinputpininterruptmonitoringissimilartopinMCU,andthereactionrateisonlysatisfiedwonderfulclass.CPLD/FPGA,highreliabilityisalsoreflectedinalmosttheentiresystemcanbedownloadedonthesamechip,thusgreatlyreducingthevolume,easytomanageandshielding.④powerful,applicationsarebroad.Currently,CPLD/FPGAtoselectalargerange,accordingtodifferentapplicationsusedifferentcapacitychips,suchasLattice'sispLSIandAMD'sMACH,thesmallestchipforthe1000equivalentlogicgates,thelargestofseveralonehundredthousand.ALTERAandXILINXgateintroducedmillionsofCPLD/FPGAcanachievealmostanyformofdigitalcircuitsordigitalsystemsdesign.Withthewideapplicationofsuchdevicesandthecostdroppedsignificantly,andthemarketrateincrease,CPLD/FPGAinthesystemrateisalmostequaltothedirectapplicationofASICdevelopment.⑤easytouse,developconvenient.ThedesignofSCMexpertsinapplicationsystemisverysimple.However,forbeginners,suchastheCPU'swork,manyoftheusageofspecialregisters,interruptconcepts,etc.,reallyisnotaneasytask.Incontrast,CPLD/FPGAapplicationdoesnotrequiretoomuchpreparationtolearntheknowledge,aslongasalittlebitofdesignofdigitalcircuitsandcomputersoftwarebasics,youcanintheshorttermtohandlebasicdesignanddevelopmentskills.Andinturn,tolearntouseSCM,itappearedhundredsoftimesmore.Thisisundoubtedlyhighforustoprovideashortcuttolearning,standingontheshouldersofgiants,ofcoursefastertobesuccessful.Itcanbepredicted,thestudyofEDAtechnologyboomandtheCPLD/FPGAapplicationboomneverinferiortoboomoverthepast10years,singlechip.⑥shortdevelopmentcycle.EDAsoftwarefeaturesasthecorrespondingsoundandpowerful,convenientandreal-timesimulationcapabilities,andintuitiveimageofthedevelopmentprocess,andthehardwarefactorsinvolvedverylittle,itcanbeverycomplicatedinaveryshorttimethesystemdesign,whichistheproducttomarketquicklythemostvaluablefeatures.SomeEDAexpertspredict,thefutureoflarge-scalesystemsofCPLD/FPGAdesignisjustallkindsoflogicandthenapplytheIPcore(CORE)oftheassembly,thedesigncycle,onlyhour.TIcompanythateightypercentofanASICIPcorefeaturesavailablesuchasready-madelogicsynthesis.1.DevelopmentoflanguageVHDLVHDL(VeryHighSpeed??IntegratedCircuitHardwareDescriptionLanguage)isaveryhighspeedintegratedcircuithardwaredescriptionlanguage,itcandescribethefunctionofthehardwarecircuitry,signalconnectivityandthetimebetweenlanguages.Itcanbemoreeffectivethanthecircuitdiagramtoexpressthecharacteristicsofthehardwarecircuit.UsingtheVHDLlanguage,youcanproceedtothegeneralrequirementsofthesystem,sincethedetailedcontentwillbedesignedtocomedowntoearth,andfinallytocompletetheoveralldesignofthesystemhardware.IEEEVHDLlanguagehasbeentheindustrystandardasadesigntofacilitatereuseandsharingtheresults.Atpresent,itcannotbeappliedanalogcircuitdesign,buthasbeenputintoresearch.VHDLprogramstructure,including:entity(Entity),structure(Architecture),configure(Configuration),PackageCollection(Package)andtheLibrary(Library).Amongthem,theentityisthebasicunitofaVHDLprogram,byentityandthestructureoftwoparts:thephysicaldesignsystemthatisusedtodescribetheexternalinterfacesignal;structureusedtodescribethebehaviorofthesystem,thesystemprocessesorsystemdatastructureform.Configurationselecttherequiredlanguagefromthelibrarysystemdesignunittoformdifferentversionsofdifferentspecifications,sothatthefunctionisdesignedtochangethesystem.Collectionofrecordsofthedesignmodulepackagetosharethedatatypes,constants,subroutinesandsoon.Databaseusedtostorethecompiledentities,thebodystructure,includingthecollectionandconfiguration:oneisthedevelopmentofengineeringsoftwareuser,theotheristhemanufacturer'sdatabase.VHDL,themainfeaturesare:①powerful,highflexibility:VHDLlanguageisapowerfullanguagestructure,clearandconcisecodecanbeusedtodesigncomplexcontrollogic.VHDLlanguagealsosupportshierarchicaldesign,supportdesigndatabasesandbuildreusablecomponents.Currently,VHDLlanguagehasbecomeadesign,simulation,synthesisofstandardhardwaredescriptionlanguage.②Deviceindependence:VHDLlanguageallowsdesignerstogenerateadesigndonotneedtofirstselectaspecificdevice.Forthesamedesigndescription,youcanuseavarietyofdifferentdevicestructurestoachieveitsfunction.Sothedesigndescriptionstage,abletofocusondesignideas.Whenthedesign,simulation,aftertheadoptionofaspecificdevicespecifiedintegrated,adaptercanbe.③Portability:VHDLlanguageisastandardlanguage,sotheuseofVHDLdesigncanbecarriedoutbydifferentEDAtoolsupport.Transplantedfromonetoanothersimulationtoolssimulationtools,synthesistoolsfromaporttoanotherintegratedtool,fromaworkingplatformintoanotherworkingplatform.EDAtoolsusedinatechnicalskills,inothertoolscanalsobeused.④top-downdesignmethods:thetraditionaldesignapproachisbottom-updesignorflatdesign.Bottom-updesignmethodologyistostartthebottomofthemoduledesign,thegradualformationofthefunctionalmodulesofcomplexcircuits.Advantageofthisdesignisobviousbecauseitisahierarchicalcircuitdesign,thegeneralcircuitsub-moduleareinaccordancewiththestructureorfunctionofdivision,sothecircuitlevelclear,clearstructure,easypeopletodevelop,whilethedesignarchivefileiseasy,easycommunication.Bottom-updesignisalsoveryobviousshortcomings,theoveralldesignconceptisoftennotleavingbecausethecostofmonthsoflow-leveldesigninvain.Flatdesignisamodulecontainingonlythecircuit,thecircuitdesignisstraightforwardand,withnodivisionstructureandfunction,itisnothierarchicalcircuitdesign.Advantagesofsmallcircuitdesigncansavetimeandeffort,butwiththeincreasingcomplexityofthecircuit,thisdesignhighlightstheshortcomingsoftheabnormalchanges.Top-downdesignapproachistodesigntop-levelcircuitdescription(topmodel),andthenthetop-levelsimulationusingEDAsoftware,ifthetop-leveldesignofthesimulationresultsmeettherequirements,youcancontinuetolowerthetop-levelmodulebythedivisionlevelandsimulation,designofsuchalevelwilleventuallycompletetheentirecircuit.Top-downdesignmethodcomparedwiththefirsttwoareobviousadvantages.⑤richdatatypes:asahardwaredescriptionlanguageVHDLdatatypesareveryrichlanguage,inadditiontoVHDLlanguageitselfdozensofpredefineddatatypes,intheVHDLlanguageprogrammingalsocanbeuser-defineddatatypes.Std_logicdatatypesinparticulartheuseofVHDLlanguagecanmakethemostrealisticcomplexsignalsinanalogcircuits.⑥modelingconvenience:theVHDLlanguagecanbeintegratedinthestatementandthestatementareavailableforsimulation,behaviordescriptionability,thereforeparticularlysuitableforsignalmodelinglanguageVHDL.ThecurrentVHDLsynthesizertocomplexarithmeticcomprehensivedescriptions(suchas:QuartusⅡ2.0andaboveversionsofstd_logic_vectortypeofdatacanadd,subtract,multiply,divide),sothecircuitmodelingforcomplexsimulationofVHDLlanguage,whetherorcomprehensivedescriptionofthelanguageareveryappropriate.⑦richruntimeandpackages:ThecurrentpackagesupportsVHDL,veryrich,mostlyintheformoflibrariesstoredinaspecificdirectory,theusercanatanytime.SuchastheIEEElibrarycollectionstd_logic_1164,std_logic_arith,std_logic_unsignedotherpackage.IntheCPLD/FPGAsynthesis,EDAsoftwarevendorscanalsousethevariouslibrariesandprovidepackage.VHDLlanguageandtheuserusingavarietyofresultscanbestoredinalibrary,inthedesignofthefollow-upcancontinuetouse.⑧VHDLlanguageisamodelinghardwaredescriptionlanguage,sowithordinarycomputerlanguages??areverydifferent,commoncomputerlanguageistheCPUclockaccordingtothebeat,afteraninstructiontoperformthenextinstruction,soinstructionisasequential,thatistheorderofexecution,andexecutionofeachinstructiontakesaspecifictime.VHDLlanguagetodescribetheresultswiththecorrespondinghardwarecircuit,whichfollowsthecharacteristicsofhardware,thereisnoorderofexecutionofthestatementisexecutedconcurrently;andstatementsthatdonotlikeordinarysoftware,takesometimeeachinstruction,justfollowtheirownhardwaredelay.2.DevelopmentEnvironmentMAX+PLUSⅡ/QUARTERⅡAlteraCorporationistheworld'sthreemajorCPLD/FPGAmanufacturersofthedevicesitcanachievethehighestperformanceandintegration,notonlybecauseoftheuseofadvancedtechnologyandnewlogicstructure,butalsobecauseitprovidesamoderndesigntoolsMAX+PLUSⅡprogrammablelogicdevelopmentsoftware,thesoftwareislaunchedthethirdgenerationofAlteraPLDdevelopmentsystem.NothingtodowiththestructureprovidesadesignenvironmentforAlteraCPLDdesignerstoeasilydesignentry,quickprocessing,anddeviceprogramming.MAX+PLUSⅡprovidesacomprehensivelogicdesigncapabilities,includingcircuitdiagrams,textandwaveformdesignentryandcompilation,logicsynthesis,simulationandtiminganalysis,anddeviceprogramming,andmanyotherfeatures.Especiallyintheschematicso,MAX+PLUSⅡisconsideredthemosteasytouse,themostfriendlyman-machineinterfacePLDdevelopmentsoftware.MAX+PLUSⅡcandevelopanythingotherthantheadditionAPEX20KCPLD/FPGA.MAX+PLUSⅡdevelopmentsystemhasmanyoutstandingfeatures:①openinterface.②designandconstructionrelated:MAX+PLUSⅡsupportAltera'sClassic,ACEX1K,MAX3000,MAX5000,MAX7000,MAX9000,FLEX6000,FLEX8000andFLEX10Kseriesofprogrammablelogicdevices,gatecountis600~250000doors,offerstheindustryreallyhasnothingtodowiththestructureofprogrammablelogicdesignenvironment.MAX+PLUSⅡcompileralsoprovidesapowerfullogicsynthesisandoptimizationtoreducetheburdenontheuser'sdesign.③canberunonmultipleplatforms:MAX+PLUSⅡsoftwarePC-basedWindowsNT4.0,Windows98,Windows2000operatingsystems,butalsoinSunSPARCstations,HP9000Series700/800,IBMRISCSystem/6000suchasrunonworkstations.④fullyintegrated:MAX+PLUSⅡsoftwaredesigninput,processing,calibrationfunctionsarefullyintegratedwithintheprogrammablelogicdevelopmenttools,whichcanbedebuggedmorequicklyandshortenthedevelopmentcycle.⑤modulartools:designerscaninputfromavarietyofdesign,editing,calibrationandprogrammingtoolstochoosethedevicetoformauser-styledevelopmentenvironment,whennecessary,toretainonthebasisoftheoriginalfeaturestoaddnewfeatures.TheMAX+PLUSⅡSeriessupportsavarietyofdevices,designersneedtolearnnewdevelopmenttoolsforthedevelopmentofnewdevicestructures.⑥mail-descriptionlanguage(HDL):MAX+PLUSⅡsoftwaresupportsavarietyofHDLdesignentry,includingthestandardVHDL,VerilogHDLandAltera'sowndevelopedhardwaredescriptionlanguageAHDL.⑦M(jìn)egaCoreFunction:MegaCorearepre-validatedfortherealizationofcomplexsystem-levelfunctionsprovidedbytheHDLnetlistfile.ItACEX1K,MAX7000,MAX9000,FLEX6000,FLEX8000andFLEX10Kdevicesprovidethemostoptimaldesign.UserscanpurchasethemfromtheAlteraMegaCore,usingthemcanreducethedesigntask,designerscanmakemoretimeandenergytoimprovethedesignandfinalproductup.⑧OpenCoreFeatures:MAX+PLUSⅡsoftwarewithopencharacteristicsofthekernel,OpenCorecometobuyproductsfordesignersdesigntheirownassessment.Atthesametime,MAX+PLUSⅡtherearemanyotherdesignentrymethods,including:①graphicdesigninput:MAX+PLUSⅡgraphicdesigninputthanothersoftwareeasiertousefeatures,becausetheMAX+PLUSⅡprovidesarichlibraryunitforthedesignercalls,especiallyintheMAX2LIBintheprovisionofthemflibraryincludesalmostall74seriesofdevices,intheprimlibraryprovidesalloftheseparatedigitalcircuitdevices.Solongasadigitalcircuitknowledge,almostnolearningcantakeadvantageofexcessMAX+PLUSⅡforCPLD/FPGAdesign.MAX+PLUSⅡalsoincludesavarietyofspeciallogicmacros(Macro-Function)andtheparametersofthetrillionofnewfeatures(Mega-Function)module.Fulluseofthesemodulesaredesignedtogreatlyreducetheworkloadofdesignerstoshortendesigncyclesandmultiply.②Enterthetexteditor:MAX+PLUSⅡtextinputlanguageandcompilersystemsupportsAHDL,VHDLlanguage,VERILOGlanguageofthethreeinputmethods.③waveinput:Ifyouknowtheinput,outputwaveform,thewaveforminputcanalsobeused.④hybridapproach:MAX+PLUSⅡdesignanddevelopmentenvironmentforgraphicaldesignentry,texteditinginput,waveformeditinginputhybridediting.Todo:ingraphicsediting,waveformeditingmodulebyeditingthetextinclude"modulename.Inc"ortheuseofFunction(.....)Return(....)Waycall.Similarly,thetexteditingmoduleinputformcanalsobecalledwhenthegraphicseditor,AHDLcompilerresultscanbeusedintheVHDLlanguage,VHDLcompileroftheresultscanalsobeenteredintheAHDLlanguageorgraphictouse.Thisflexibleinputmethods,todesigntheuserhasbroughtgreatconvenience.Altera'sQuartusⅡisacomprehensivePLDdevelopmentsoftwaretosupporttheschematic,VHDL,VerilogHDL,andAHDL(AlteraHardwareDescriptionLanguage)andotherdesigninputforms,embeddeddevices,andintegrateditsownsimulator,youcancompletethedesigninputtocompletethehardwareconfigurationofthePLDdesignprocess.QuartusⅡintheXP,LinuxandUnixontheuse,inadditiontousingtheTclscripttocompletethedesignprocess,toprovideacompletegraphicaluserinterfacedesign.Withrunningspeed,unifiedinterface,featureset,easytouseandsoon.Altera'sQuartusⅡsupportIPcore,includingtheLPM/MegaFunctionmacrofunctionmodulelibrary,allowinguserstotakefulladvantageofsophisticatedmodules,simplifyingthedesigncomplexityandspeedupthedesignspeed.Goodforthird-partyEDAtoolsupportalsoallowstheusertothevariousstagesinthedesignprocessusingthefamiliarthird-partyEDAtools.Inaddition,QuartusⅡandDSPBuildertoolsandbyMatlab/Simulinkcombination,youcaneasilyachieveavarietyofDSPapplications;supportAltera'sprogrammablesystemchip(SOPC)development,setsystem-leveldesign,embeddedsoftwaredevelopment,programmablelogicdesigninone,isacomprehensivedevelopmentplatform.MAX+PLUSⅡgenerationasAltera'sPLDdesignsoftware,duetoitsexcellenteaseofusehasbeenwidelyused.AlterahasnowstoppedMAX+PLUSⅡupdatesupport,QuartusⅡnotonlysupportthedevicetypeascomparedtotherichandthegraphicalinterfacechanges.AlteraQuartusⅡincludedinmanysuchSignalTapⅡ,ChipEditorandRTLViewerdesignaids,integratedSOPCandHardCopydesignprocess,andinheritMAX+PLUSⅡfriendlygraphicalinterfaceandeasytouse.MAX+PLUSⅡgenerationasAltera'sPLDdesignsoftware,duetoitsexcellenteaseofusehasbeenwidelyused.AlterahasnowstoppedMAX+PLUSⅡupdatesupport,QuartusⅡnotonlysupportthedevicetypeascomparedtotherichandthegraphicalinterfacechanges.AlteraQuartusⅡincludedinmanysuchSignalTapⅡ,ChipEditorandRTLViewerdesignaids,integratedSOPCandHardCopydesignprocess,andinheritMAX+PLUSⅡfriendlygraphicalinterfaceandeasytouse.AlteraQuartusⅡasaprogrammablelogicdesignenvironment,duetoitsstrongdesigncapabilitiesandintuitiveinterface,moreandmoredigitalsystemsdesignerswelcome.Altera'sQuartusⅡisthefourthgenerationofprogrammablelogicPLDsoftwaredevelopmentplatform.Theplatformsupportsaworkinggroupunderthedesignrequirements,includingsupportforInternet-basedcollaborativedesign.QuartusplatformandCadence,ExemplarLogic,MentorGraphics,SynopsysandSynplicityEDAvendorsandotherdevelopmenttoolsarecompatible.LogicLockimprovethesoftwaremoduledesignfeatures,addedFastFitcompileroptions,andpromotethenetworkeditingperformance,andimproveddebuggingcapabilities.MAX7000/MAX3000devicesandotheritemstosupporttheproduct.電子設(shè)計(jì)自動(dòng)化EDA(電子設(shè)計(jì)自動(dòng)化)技術(shù)是現(xiàn)代電子工程領(lǐng)域的一項(xiàng)新技術(shù),它提供了計(jì)算機(jī)信息技術(shù)和電路設(shè)計(jì)方法。EDA技術(shù)的發(fā)展和應(yīng)用,極大地促進(jìn)了電子行業(yè)的發(fā)展。EDA技術(shù)的發(fā)展,硬件設(shè)計(jì)的電子電路可以依賴幾乎所有電腦完成,從而大大縮短周期的硬件電子電路設(shè)計(jì),讓制造商快速開發(fā)各種少量的產(chǎn)品,以滿足市場(chǎng)需求。EDA技術(shù),基本觀點(diǎn)是電腦的幫助下,EDA軟件平臺(tái)來(lái)完成電子電路設(shè)計(jì)、仿真和PCB設(shè)計(jì)的整個(gè)過(guò)程。對(duì)于更復(fù)雜的電路,如有必要,可用于實(shí)現(xiàn)可編程邏輯器件。EDA技術(shù)不僅在電子課程和分析仿真實(shí)驗(yàn)來(lái)解決各種各樣的實(shí)驗(yàn)室組件,規(guī)格和數(shù)量限制是不夠的,以避免傷害到學(xué)生在實(shí)驗(yàn)室組件和設(shè)備來(lái)刺激學(xué)習(xí)興趣,開發(fā)他們的分析、電子產(chǎn)品的設(shè)計(jì)和開發(fā)能力,但也e工人設(shè)計(jì),開發(fā)一個(gè)強(qiáng)大的工具,電子產(chǎn)品。思想教育和行業(yè)的EDA技術(shù)推廣是一個(gè)技術(shù)熱點(diǎn)在當(dāng)今世界,EDA技術(shù)是現(xiàn)代電子工業(yè)中不可或缺的技術(shù)。EDA技術(shù)具有廣泛的含義,但也是一個(gè)漸進(jìn)發(fā)展的領(lǐng)域有強(qiáng)大的生命力。今天的EDA技術(shù)已經(jīng)達(dá)到了一個(gè)“片上系統(tǒng)(SOC芯片,系統(tǒng))階段。開發(fā)人員可以使用強(qiáng)大的EDA設(shè)計(jì)軟件,使用IP(知識(shí)產(chǎn)權(quán))的IP核心,加上他的創(chuàng)新思維,構(gòu)建自己的定制芯片,它具有自己的知識(shí)產(chǎn)權(quán)設(shè)計(jì)專用集成電路(ASIC,特定于應(yīng)用程序的集成電路)。EDA技術(shù)在教學(xué)的普及,基于可編程設(shè)備的實(shí)際應(yīng)用技術(shù),其中包括四個(gè)基本條件:①大規(guī)?？删幊淘O(shè)備,它是利用EDA技術(shù)載體的電子系統(tǒng)設(shè)計(jì);②硬件描述語(yǔ)言它是使用EDA技術(shù)的電子系統(tǒng)設(shè)計(jì),主要表達(dá)情感的方式;③軟件開發(fā)工具,它是使用EDA技術(shù)的智能電子系統(tǒng)設(shè)計(jì)自動(dòng)化設(shè)計(jì)工具。④實(shí)驗(yàn)開發(fā)系統(tǒng),它是使用EDA技術(shù)在電子系統(tǒng)下載工具和硬件設(shè)計(jì)驗(yàn)證工具。可編程邏輯控制(CPLD/FPGA)在我們的設(shè)計(jì)中我們之所以選用CPLD/FPGA，因?yàn)樗c傳統(tǒng)的MCU相比有著許多優(yōu)點(diǎn)，主要有以下幾個(gè)方面：①編程方式簡(jiǎn)便先進(jìn)。CPLD/FPGA產(chǎn)品中部分是采用菊花鏈在系統(tǒng)編程方式的。這種先進(jìn)的編程方式已成為當(dāng)今世界上各類可編程器件發(fā)展的趨勢(shì)。因?yàn)樗s了價(jià)格昂貴，操作不便的專用編程器，只需要一個(gè)十分簡(jiǎn)單的下載編程電路和一條PC機(jī)的打印機(jī)通訊線就行了。它無(wú)須編程高壓，在TTL電平下隨時(shí)可進(jìn)行在線編程，并可進(jìn)行所謂菊花鏈?zhǔn)蕉嗥芯幊?。其編程次?shù)多達(dá)1萬(wàn)次，如Lattice的isles和AMD公司的MACH系列。此外，還可輕易地實(shí)現(xiàn)紅外編程，超聲編程或無(wú)線編程，或通過(guò)電話線遠(yuǎn)程在線編程。這些功能在通訊器件和軍事器件上有特殊用途。②高速。CPLD/FPGA的時(shí)鐘延遲可達(dá)ns級(jí)，結(jié)合其并行工作方式，在超高速應(yīng)用領(lǐng)域和實(shí)時(shí)測(cè)控方面有非常廣闊的應(yīng)用前景。如果利用ALTERA的FLEX10K50開發(fā)通過(guò)USB接口的網(wǎng)絡(luò)圖像實(shí)時(shí)加密/解密ASIC系統(tǒng)，在FLEX10K50中進(jìn)行高達(dá)56位二進(jìn)制的并行四則運(yùn)算，每一加密/解密周期只需數(shù)μs，而MCU需時(shí)近1分。又如在模具制造業(yè)的電火花成型加工中，電機(jī)控制的加工件的有效運(yùn)行距離僅數(shù)μs，這要求極敏感和高速的控制飼服電路系統(tǒng)，否則不是發(fā)生短路拉弧，就是擊穿不足。顯然，這方面的工作，MCU也是難于直接參與的。如果利用ispLSI1032進(jìn)行直接飼服控制，對(duì)測(cè)速電機(jī)的閉環(huán)飼服，利用ispLSI對(duì)AD1674直接進(jìn)行采樣控制，8位采用精度，最高速度達(dá)8μs/每次，從而實(shí)現(xiàn)了良好的閉環(huán)同步和變速控制。③高可靠性。在高可靠應(yīng)用領(lǐng)域，MCU的缺憾為CPLD/FPGA的應(yīng)用留下了很大的用武之地。這組器件盡管在功能開發(fā)上是通過(guò)EDA軟件實(shí)現(xiàn)的。但物理機(jī)制卻像一片74LS164那樣純屬硬件電路，十分可靠。通過(guò)合理設(shè)計(jì)，大多數(shù)應(yīng)用中，無(wú)須考慮復(fù)雜的復(fù)位和初始化。設(shè)計(jì)中只需利用簡(jiǎn)單的語(yǔ)句將閑置狀態(tài)導(dǎo)入同一初始入口，就能有效防止任何可能的“死機(jī)”現(xiàn)象。由于是并行工作，它的任一輸入腳都可用作類似于MCU的中斷監(jiān)測(cè)引腳，且反應(yīng)速度僅為納妙級(jí)。CPLD/FPGA的高可靠性還表現(xiàn)在幾乎可將整個(gè)系統(tǒng)下載于同一芯片中，從而大大縮小了體積，易于管理和屏蔽。④功能強(qiáng)大，應(yīng)用廣闊。目前，CPLD/FPGA的可選擇范圍很大，可根據(jù)不同的應(yīng)用選用不同容量的芯片，如Lattice的ispLSI和AMD公司的MACH，最小芯片的等效邏輯門為1000門，最大達(dá)數(shù)十萬(wàn)門。ALTERA和XILINX公司推出的百萬(wàn)門的CPLD/FPGA可實(shí)現(xiàn)幾乎任何形式的數(shù)字電路或數(shù)字系統(tǒng)的設(shè)計(jì)。隨著這類器件的廣泛應(yīng)用和成本的大幅下降，以及產(chǎn)品上市速率的提高，CPLD/FPGA在系統(tǒng)中的直接應(yīng)用率正直逼ASIC的開發(fā)。⑤易學(xué)易用，開發(fā)便捷。單片機(jī)應(yīng)用系統(tǒng)的設(shè)計(jì)對(duì)于行家里手來(lái)說(shuō)是十分簡(jiǎn)單的事。然而，對(duì)于初學(xué)者，諸如CPU的工作方式、眾多特殊寄存器的用法、中斷概念等等，著實(shí)不是一件容易的事。相比之下，CPLD/FPGA應(yīng)用的學(xué)習(xí)卻不需要太多的預(yù)備知識(shí)，只要稍具一點(diǎn)數(shù)字電路和計(jì)算機(jī)軟件設(shè)計(jì)的基礎(chǔ)知識(shí)，就能在短期內(nèi)掌握基本的設(shè)計(jì)方法和開發(fā)技巧。而且反過(guò)來(lái)去學(xué)用單片機(jī)，就顯得輕車熟路多了。這無(wú)疑是高技術(shù)為我們的學(xué)習(xí)提供了捷徑，站在巨人的肩膀當(dāng)然能更快地獲得成功?？梢灶A(yù)言，我國(guó)EDA技術(shù)的學(xué)習(xí)熱潮和CPLD/FPGA的應(yīng)用熱潮決不會(huì)遜色于過(guò)去10年的單片機(jī)熱潮。⑥開發(fā)周期短。由于相應(yīng)的EDA軟件功能完善而強(qiáng)大，仿真能力便捷而實(shí)時(shí)，開發(fā)過(guò)程形象而直觀，兼之硬件因素涉及甚少，因此可以在很短時(shí)間內(nèi)完成十分復(fù)雜的系統(tǒng)設(shè)計(jì)，這是產(chǎn)品快速進(jìn)入市場(chǎng)的最寶貴的特征。一些EDA專家預(yù)言，未來(lái)的大系統(tǒng)的CPLD/FPGA設(shè)計(jì)僅僅是各類再應(yīng)用邏輯與IP核(CORE)的拼裝，其設(shè)計(jì)周期僅以小時(shí)計(jì)。TI公司認(rèn)為，一個(gè)ASIC百分之八十的功能可用IP核等現(xiàn)成邏輯合成。一.開發(fā)語(yǔ)言VHDLVHDL(VeryHighSpeedIntegratedCircuitHardwareDescriptionLanguage)是非常高速集成電路硬件描述語(yǔ)言，是可以描述硬件電路的功能、信號(hào)連接關(guān)系及定時(shí)關(guān)系的語(yǔ)言．它能比電路原理圖更有效地表示硬件電路的特性。使用VHDL語(yǔ)言，可以就系統(tǒng)的總體要求出發(fā)，自上至下地將設(shè)計(jì)內(nèi)容細(xì)化，最后完成系統(tǒng)硬件的整體設(shè)計(jì)。VHDL語(yǔ)言已作為一種IEEE的工業(yè)標(biāo)準(zhǔn)，設(shè)計(jì)結(jié)果便于復(fù)用和交流。目前，它還不能應(yīng)用于模擬電路的設(shè)計(jì)，但已有人投入研究。VHDL程序結(jié)構(gòu)包括：實(shí)體(Entity)、結(jié)構(gòu)體(Architecture)、配置(Configuration)、包集合(Package)及庫(kù)(Library)。其中，實(shí)體是一個(gè)VHDL程序的基本單元，由實(shí)體說(shuō)明和結(jié)構(gòu)體兩部分組成：實(shí)體說(shuō)明用于描述設(shè)計(jì)系統(tǒng)的外部接口信號(hào)；結(jié)構(gòu)體用于描述系統(tǒng)的行為、系統(tǒng)數(shù)據(jù)的流程或系統(tǒng)組織結(jié)構(gòu)形式。配置用語(yǔ)從庫(kù)中選取所需的單元來(lái)組成系統(tǒng)設(shè)計(jì)的不同規(guī)格的不同版本，使被設(shè)計(jì)系統(tǒng)的功能發(fā)生變化。包集合存放各設(shè)計(jì)模塊能共享的數(shù)據(jù)類型、常數(shù)、子程序等。庫(kù)用于存放已編譯的實(shí)體、構(gòu)造體、包集合及配置：一種是用戶自己開發(fā)的工程軟件，另一種是制造商提供的庫(kù)。VHDL語(yǔ)言的主要特點(diǎn)是：①功能強(qiáng)大，靈活性高：VHDL語(yǔ)言是一種功能強(qiáng)大的語(yǔ)言結(jié)構(gòu)，可用簡(jiǎn)潔明確的代碼來(lái)進(jìn)行復(fù)雜控制邏輯的設(shè)計(jì)。同時(shí)VHDL語(yǔ)言還支持層次化的設(shè)計(jì)，支持設(shè)計(jì)庫(kù)和可重復(fù)使用的元件生成。目前，VHDL語(yǔ)言已成為一種設(shè)計(jì)、仿真、綜合的標(biāo)準(zhǔn)硬件描述語(yǔ)言。②器件無(wú)關(guān)性：VHDL語(yǔ)言允許設(shè)計(jì)者在生成一個(gè)設(shè)計(jì)時(shí)不需要首先選擇一個(gè)具體的器件。對(duì)于同一個(gè)設(shè)計(jì)描述，可以采用多種不同器件結(jié)構(gòu)來(lái)實(shí)現(xiàn)其功能。因此設(shè)計(jì)描述階段，可以集中精力從事設(shè)計(jì)構(gòu)思。當(dāng)設(shè)計(jì)、仿真通過(guò)后，指定具體的器件綜合、適配即可。③可移植性：VHDL語(yǔ)言是一種標(biāo)準(zhǔn)的語(yǔ)言，故采用VHDL進(jìn)行的設(shè)計(jì)可以被不同的EDA工具所支持。從一個(gè)仿真工具移植到另一個(gè)仿真工具，從一個(gè)綜合工具移植到另一個(gè)綜合工具，從一個(gè)工作平臺(tái)移植到另一個(gè)工作平臺(tái)。在一個(gè)EDA工具中采用的技術(shù)技巧，在其它工具中同樣可以采用。④自頂向下的設(shè)計(jì)方法：傳統(tǒng)的設(shè)計(jì)方法是，自底向上的設(shè)計(jì)或平坦式設(shè)計(jì)。自底向上的設(shè)計(jì)方法是先從底層模塊設(shè)計(jì)開始，逐漸由各個(gè)模塊形成功能復(fù)雜的電路。這種設(shè)計(jì)方法優(yōu)點(diǎn)是很明顯的，因?yàn)樗且环N層次設(shè)計(jì)電路，一般電路的子模塊都是按照結(jié)構(gòu)或功能劃分，因此這種電路層次清楚，結(jié)構(gòu)明確，便于多人合作開發(fā)，同時(shí)設(shè)計(jì)文件易于存檔，易于交流。自底向上設(shè)計(jì)方法的缺點(diǎn)也很明顯，往往由于整體設(shè)計(jì)思路不對(duì)而使的花費(fèi)幾個(gè)月的低層設(shè)計(jì)付之東流。平坦式設(shè)計(jì)是整個(gè)電路只含有一個(gè)模塊，電路的設(shè)計(jì)是平鋪直敘的，沒(méi)有結(jié)構(gòu)和功能上的劃分，因此不是層次電路的設(shè)計(jì)方式。優(yōu)點(diǎn)是小型電路設(shè)計(jì)時(shí)可以節(jié)省時(shí)間和精力，但隨著電路復(fù)雜程度的增加，這種設(shè)計(jì)方式的缺點(diǎn)變的異常突出。自頂向下的設(shè)計(jì)方法是將要設(shè)計(jì)的電路進(jìn)行最頂層的描述（頂層建模），然后利用EDA軟件進(jìn)行頂層仿真，如果頂層設(shè)計(jì)的仿真結(jié)果滿足要求，則可以繼續(xù)將頂層劃分的模塊進(jìn)行低一級(jí)的劃分并仿真，這樣一級(jí)一級(jí)設(shè)計(jì)最終將完成整個(gè)電路的設(shè)計(jì)。自頂向下的設(shè)計(jì)方法與前面兩種方法相比優(yōu)點(diǎn)是很明顯的。⑤數(shù)據(jù)類型豐富：作為硬件描述語(yǔ)言的一種VHDL語(yǔ)言的數(shù)據(jù)類型非常豐富，除了VHDL語(yǔ)言自身預(yù)定義的十種數(shù)據(jù)類型外，在VHDL語(yǔ)言程序設(shè)計(jì)中還可以由用戶自定義數(shù)據(jù)類型。特別是std_logic數(shù)據(jù)類型的使用，使得VHDL語(yǔ)言能最真實(shí)模擬電路中的復(fù)雜信號(hào)。⑥建模方便：由于VHDL語(yǔ)言中可綜合的語(yǔ)句和用于仿真的語(yǔ)句齊備，行為描述能力強(qiáng)，因此VHDL語(yǔ)言特別適合信號(hào)建模。目前VHDL的綜合器能對(duì)復(fù)雜的算術(shù)描述進(jìn)行綜合（如：QuartusⅡ2.0以上的版本都能對(duì)std_logic_vector類型的數(shù)據(jù)進(jìn)行加、減、乘、除），因此對(duì)于復(fù)雜電路的建模VHDL語(yǔ)言無(wú)論仿真還是綜合都是非常合適的描述語(yǔ)言。⑦運(yùn)行庫(kù)和程序包豐富：目前支持VHDL語(yǔ)言的程序包很豐富，大多以庫(kù)的形式存放在特定的目錄下，用戶可隨時(shí)調(diào)用。如IEEE庫(kù)收集了std_logic_1164、std_logic_arith、std_logic_unsigned等程序包。在CPLD/FPGA綜合時(shí)，還可以使用EDA軟件商提供的各種庫(kù)和程序包。而且用戶利用VHDL語(yǔ)言編寫的各種成果都可以以庫(kù)的形式存放，在后續(xù)的設(shè)計(jì)中可以繼續(xù)使用。⑧VHDL語(yǔ)言是一種硬件電路的建模描述語(yǔ)言，因此與普通的計(jì)算機(jī)語(yǔ)言有較大差別，普通計(jì)算機(jī)語(yǔ)言是CPU按照時(shí)鐘的節(jié)拍，一條指令執(zhí)行完后才能執(zhí)行下一條指令，因此指令執(zhí)行是有先后順序的，也即是順序執(zhí)行，而每條指令的執(zhí)行占用特定的時(shí)間。而與VHDL語(yǔ)言描述結(jié)果相對(duì)應(yīng)的是硬件電路，它遵循硬件電路的特點(diǎn)，語(yǔ)句的執(zhí)行沒(méi)有先后順序，是并發(fā)的執(zhí)行的；而且語(yǔ)句的執(zhí)行不象普通軟件那樣每條指令占用一定的時(shí)間，只是遵循硬件電路自身的延遲時(shí)間。二.開發(fā)環(huán)境MAX+PLUSⅡ/QUARTERⅡAltera公司是世界三大CPLD／FPGA廠家之一，它的器件能達(dá)到最高的性能和集成度，不僅僅因?yàn)椴捎昧讼冗M(jìn)的工藝和全新的邏輯結(jié)構(gòu)，還在于它提供了現(xiàn)代化的設(shè)計(jì)工具一MAX+PLUSⅡ可編程邏輯開發(fā)軟件，該軟件是Altera公司推出的第三代PLD開發(fā)系統(tǒng)。提供了一種與結(jié)構(gòu)