數(shù)字邏輯實(shí)驗(yàn)-計(jì)數(shù)器的設(shè)計(jì)與仿真

實(shí)驗(yàn)七計(jì)數(shù)器的設(shè)計(jì)與仿真一、實(shí)驗(yàn)內(nèi)容1．調(diào)用系統(tǒng)中的74LS163芯片，對(duì)其進(jìn)行波形仿真，驗(yàn)證其功能。2．用VHDL語言設(shè)計(jì)一個(gè)能夠?qū)崿F(xiàn)同樣功能的電路（能同步清零、同步置數(shù)的4位二進(jìn)制計(jì)數(shù)器）。3．修改代碼，將這個(gè)計(jì)數(shù)器修改為模10計(jì)數(shù)器。二、電路功能介紹及仿真74LS163：同步清零同步置數(shù)的4位二進(jìn)制計(jì)數(shù)器1、邏輯框圖2、邏輯功能表3、調(diào)用系統(tǒng)中的74LS163芯片，對(duì)其進(jìn)行波形仿真仿真波形圖如下：4、4位二進(jìn)制計(jì)數(shù)器（1）VHDL語言 libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_unsigned.all;entityerjinzhiisport(clk,clrn,ent,enp,ldn:inSTD_LOGIC;a:inSTD_LOGIC_VECTOR(3downto0);qi:outSTD_LOGIC_VECTOR(3downto0);rco:outSTD_LOGIC);enderjinzhi;architecturebhvoferjinzhiissignalcqi:STD_LOGIC_VECTOR(3downto0);beginprocess(clk,clrn,ent,enp,ldn)beginifclk'eventandclk='1'thenifclrn='0'thencqi<="0000";rco<='0';elsifldn='0'orent='0'orenp='0'thencqi<=cqi;rco<='0';elsifldn='1'andent='1'andenp='1'thenif(a="0000")thencqi<="0001";elsif(a="0001")thencqi<="0010";elsif(a="0010")thencqi<="0011";elsif(a="0011")thencqi<="0100";elsif(a="0100")thencqi<="0101";elsif(a="0101")thencqi<="0110";elsif(a="0110")thencqi<="0111";elsif(a="0111")thencqi<="1000";elsif(a="1000")thencqi<="1001";elsif(a="1001")thencqi<="1010";elsif(a="1010")thencqi<="1011";elsif(a="1011")thencqi<="1100";elsif(a="1100")thencqi<="1101";elsif(a="1101")thencqi<="1110";elsif(a="1110")thencqi<="1111";rco<='1';elsif(a="1111")thencqi<="0000";rco<='0';endif;endif;elsecqi<=cqi;endif;qi<=cqi;endprocess;endbhv;（2）仿真波形圖5、模10計(jì)數(shù)器（1）VHDL語言LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK:INSTD_LOGIC;--時(shí)鐘信號(hào)CLR:INSTD_LOGIC;--清零信號(hào)EN:INSTD_LOGIC;--計(jì)數(shù)使能信號(hào)CN:OUTSTD_LOGIC;--記數(shù)輸出信號(hào) COUNT10:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCNT10;ARCHITECTUREARTOFCNT10ISSIGNALSCOUNT10:STD_LOGIC_VECTOR(3DOWNTO0);BEGINCOUNT10<=SCOUNT10;PROCESS(CLK,CLR,EN)BEGINIF(CLR='1')THENSCOUNT10<="0000";CN<='0';ELSIFRISING_EDGE(CLK)THENIF(EN='1')THENIFSCOUNT10="1001"THENCN<='1';SCOUNT10<="0000";ELSE