單片機(jī)AT89C52簡(jiǎn)要說(shuō)明.doc

附錄A 英文原文Microcomputer AT89C52 Synoptic ElucidationThe microcomputer AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator, and clock circuitry.In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning.The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset,for the figure 1.Pin DescriptionVCC:Supply voltage.GND:Ground.Port 0:Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 can also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification.External pull-ups are required during program verification.Port 1:Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2:Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3:Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RST:Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG:Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Other- wise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN:Program Store Enable is the read strobe to external program memory.When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP:External Access Enable. EA must be strapped to GND in order to enable the 圖A.1 AT89C52方框圖device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions.This pin also receives the12-volt programming enable voltage(VPP) during Flash programming when 12-volt programming is selected.XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier.Special Function Registers：Not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H,RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priori- ties can be set for each of the six interrupt sources in the IP register.Data Memory:The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1:Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.Timer 2:Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON.Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition,the maxi- mum count rate is 1/24 of the oscillator frequency.To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.Capture Mode:In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. Auto-Reload (Up or Down Counter):Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.Timer 2 automatically count up when DCEN = 0. In this mode, two option s are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software.If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transi- tion also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers,TH2 and TL2, respect- tively.A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers.The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an inter- rupt.Baud Rate Generator：Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or trans- mitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4.The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.The baud rates in Modes 1 and 3 are determined by Timer2s overflow rate according to the following （A.1）equation.Modes1 and 3 band rates= （A.1） The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally,as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency).The baud rate formula is given below（A.2）.= （A.2） where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer Timer 2 as a baud rate generator is showed. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.附錄B 中文翻譯單片機(jī)AT89C52簡(jiǎn)要說(shuō)明AT89C52提供以下標(biāo)準(zhǔn)功能：8k字節(jié)Flash閃速存儲(chǔ)器，256字節(jié)內(nèi)部RAM，32個(gè)I/O口線(xiàn)，3個(gè)16位定時(shí)/計(jì)數(shù)器，一個(gè)6向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89C52可降至0Hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式。空閑方式停止CPU的工作，但允許RAM，定時(shí)/計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。如圖A.1所示。引腳功能說(shuō)明VCC：電源電壓GND：地P0口：P0口是一組8位漏極開(kāi)路型雙向I/O口，也即地址/數(shù)據(jù)總線(xiàn)復(fù)用口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門(mén)電路，對(duì)端口P0寫(xiě)“1”時(shí)，可作為高阻抗輸入端用。在訪(fǎng)問(wèn)外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線(xiàn)分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)線(xiàn)復(fù)用，在訪(fǎng)問(wèn)期間激活內(nèi)部上拉電阻。在Flash編程時(shí)，P0口接受指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外界上拉電阻。P1口：P1口是一個(gè)內(nèi)部帶上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口，作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。與AT89C51不同之處是，P1.0和P1.1還可以作為定時(shí)/計(jì)數(shù)器2的外部計(jì)數(shù)輸入（P1.0/T2）和輸入（P1.1/T2EX）。Flash編程和程序校驗(yàn)期間，P1接受低8位地址。P2口：P2口是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)端口P2寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。在訪(fǎng)問(wèn)外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVXRI指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪(fǎng)問(wèn)8位地址的外部數(shù)據(jù)存儲(chǔ)器（如執(zhí)行MOVXRI指令）時(shí)，P2口輸出P2鎖存器的內(nèi)容。Falsh編程和校驗(yàn)時(shí)，P2亦接受高位地址和一些控制信號(hào)。P3口：P3口是一組帶有內(nèi)部上拉電阻的8位雙向I/O口。P3口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)P3口寫(xiě)入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入輸出口，此時(shí)，被外部拉低的P3口將用上拉電阻輸出電流（IIL）。P3口除了作為一般的I/O口線(xiàn)外，更重要的用途是它的第二功能。此外，P3口還可接受一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上的高電平將使單片機(jī)復(fù)位。ALE/：當(dāng)訪(fǎng)問(wèn)外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。一般情況下，ALE仍以時(shí)鐘振蕩頻率的1/6輸出固定的脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪(fǎng)問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過(guò)一個(gè)ALE脈沖。 對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（）。 如有必要，可通過(guò)對(duì)特殊功能寄存器（SFR）區(qū)中的8EH單元的D0位置位，可禁止ALE操作。該位置位后，只有一條MOVX和MOVC指令才能將ALE激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE禁止位無(wú)效。 ：程序存儲(chǔ)允許（）輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C52由外部程序存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪(fǎng)問(wèn)外部數(shù)據(jù)存儲(chǔ)器，將跳過(guò)兩個(gè)信號(hào)。/VPP：外部訪(fǎng)問(wèn)允許。欲使CPU僅訪(fǎng)問(wèn)外部程序存儲(chǔ)器（地址為0000H-FFFFH），端必須保持低電平（接地）。需注意的是：如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平（接VCC端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電源Vpp，當(dāng)然這必須是該器件是使用12V編程電壓Vpp。XTAL1：振蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。XTAL2：振蕩器反相放大器的輸出端。特殊功能寄存器：在A(yíng)T89C52片內(nèi)存儲(chǔ)器中，80H-FFH共128個(gè)單元為特殊功能寄存器（SFE）。并非所有的地址都被定義，從80HFFH共128個(gè)字節(jié)只有一部分被定義，還有相當(dāng)一部分沒(méi)有定義。對(duì)沒(méi)有定義的單元讀寫(xiě)將是無(wú)效的，讀出的數(shù)值將不確定，而寫(xiě)入的數(shù)據(jù)也丟失。不應(yīng)將數(shù)據(jù)“1”寫(xiě)入未定義的單元，由于這些單元在將來(lái)的產(chǎn)品中可能賦予新的功能，再這種情況下，復(fù)位后這些單元數(shù)值總是“0”。AT89C52除了與AT89C51所有的定時(shí)/計(jì)數(shù)器0/計(jì)數(shù)器1外，還增加了一個(gè)定時(shí)/計(jì)數(shù)器2。定時(shí)/計(jì)數(shù)器2的控制和狀態(tài)位于T2CON和T2MOD中，寄存器對(duì)（RCA02H、RCAP2L）是定時(shí)器2在16位捕獲方式或16位自動(dòng)重載方式下的捕獲/自動(dòng)重載寄存器。中斷寄存器：AT89C52有6個(gè)中斷源，2個(gè)中斷優(yōu)先級(jí)，IE寄存器控制各中斷位，IP寄存器中6個(gè)中斷源的每一個(gè)可定為2個(gè)優(yōu)先級(jí)。數(shù)據(jù)寄存器：AT89C52有256個(gè)字節(jié)的內(nèi)部RAM，80H-FFH高128個(gè)字節(jié)與特殊功能寄存器（SFR）地址是重疊的，也就是高128字節(jié)的RAM和特殊功能寄存器的地址是相同的，但物理上它們是分開(kāi)的。當(dāng)一條指令訪(fǎng)問(wèn)7FH以上的內(nèi)部地址單元時(shí)，指令中使用的尋址方式是不同的，也即尋址方式?jīng)Q定是訪(fǎng)問(wèn)高128字節(jié)RAM還是訪(fǎng)問(wèn)特殊功能寄存器。如果指令是直接尋址方式則為訪(fǎng)問(wèn)特殊功能寄存器。定時(shí)器0和定時(shí)器1：AT89C52的定時(shí)器0和定時(shí)器1的工作方式與AT89C51相同。定時(shí)器2：定時(shí)器2是一個(gè)16位定時(shí)/計(jì)數(shù)器。它既可當(dāng)定時(shí)器用，也可作為外部事件計(jì)數(shù)器使用，其工作方式由特殊功能寄存器T2CON的C/T2選擇。定時(shí)器2有三種工作方式：捕獲方式，自動(dòng)重載方式（向上或向下計(jì)數(shù)）方式和波特率發(fā)生器方式，工作方式由T2CON的控制位來(lái)選擇。定時(shí)器2由兩個(gè)8位寄存器TH2和TL2組成，在定時(shí)器工作方式中，每個(gè)機(jī)器周期TL2寄存器的值加1，由于一個(gè)機(jī)器周期由12個(gè)振蕩時(shí)鐘構(gòu)成，因此，計(jì)數(shù)速率為振蕩頻率的1/12。在計(jì)數(shù)工作方式時(shí)，當(dāng)T2引腳上外部輸入信