嵌入式系統(tǒng)導論3硬件設(shè)計 arm

1、嵌入式系統(tǒng)導論,第三章,嵌入式系統(tǒng)硬件,Introduction to Embedded System,中南大學信息科學與工程學院,專題,1:S3c4510,及其應(yīng)用系統(tǒng)設(shè)計,S3c4510,概述,S3c4510,系統(tǒng)管理,Cache,內(nèi)部控制器,設(shè)計事例,專題,1:S3c4510,及其應(yīng)用系統(tǒng)設(shè)計,一,S3C4510,概述,S3C4510B 16/32-bit RISC microcontroller,Arm Core,集成功能,8K-byte unified cache/SRAM,I2C interface,Ethernet controller,HDLC,GDMA,UART,Timers

2、,Programmable I/O ports,Interrupt controller,專題,1:S3c4510,及其應(yīng)用系統(tǒng)設(shè)計,S3C4510,概述,Cont.,cost-effective, high-performance,應(yīng)用領(lǐng)域,通信、控制,ARM,Advanced RISC Machines,公司、一類微處理器、一種技術(shù),1991,年,ARM,公司成立于英國劍橋，主要,出售芯片設(shè)計技術(shù)的授權(quán),IP,工業(yè)控制、消費類電子產(chǎn)品、通信系統(tǒng),網(wǎng)絡(luò)系統(tǒng)、無線系統(tǒng)等,基于,ARM,技術(shù)的微處理器應(yīng)用約占據(jù)了,32,位,RISC,微處理器,75,以上的市場份額,ARM,Advanced RI

3、SC Machines,采用,RISC,架構(gòu)的,ARM,微處理器一般具有如下特,點,1,體積小、低功耗、低成本、高性能,2,支持,Thumb,16,位,ARM,32,位）雙指令,集，能很好的兼容,8,位,16,位器件,3,大量使用寄存器，指令執(zhí)行速度更快,4,大多數(shù)數(shù)據(jù)操作都在寄存器中完成,5,尋址方式靈活簡單，執(zhí)行效率高,6,指令長度固定,ARM,Advanced RISC Machines,ARM,微處理器系列,ARM7,系列,ARM9,系列,ARM9E,系列,ARM10E,系列,SecurCore,系列,Intel,的,Xscale,Intel,的,StrongARM,ARM7,ARM9

4、,ARM9E,和,ARM10,為,4,個通用處理器系列，每一個系列提,供一套相對獨特的性能來滿足不同應(yīng)用領(lǐng)域的需求,SecurCore,系列,專門為安全要求較高的應(yīng)用而設(shè)計,ARM,Advanced RISC Machines,ARM7,系列,具有嵌入式,ICE,RT,邏輯，調(diào)試開發(fā)方便,極低的功耗，適合對功耗要求較高的應(yīng)用，如便攜,式產(chǎn)品,能夠提供,0.9MIPS/MHz,的三級流水線結(jié)構(gòu),代碼密度高并兼容,16,位的,Thumb,指令集,對操作系統(tǒng)的支持廣泛，包括,Windows,CE,Linux,Palm,OS,等,指令系統(tǒng)與,ARM9,系列,ARM9E,系列和,ARM10E,系列兼,容

5、，便于用戶的產(chǎn)品升級換代,主頻最高可達,130MIPS,高速的運算處理能力能勝,任絕大多數(shù)的復雜應(yīng)用,ARM,Advanced RISC Machines,ARM9,系列,5,級整數(shù)流水線，指令執(zhí)行效率更高,提供,1.1MIPS/MHz,的哈佛結(jié)構(gòu),支持,32,位,ARM,指令集和,16,位,Thumb,指令集,支持,32,位的高速,AMBA,總線接口,全性能的,MMU,支持,Windows,CE,Linux,Palm,OS,等多種主流嵌入式操作系統(tǒng),MPU,支持實時操作系統(tǒng),支持數(shù)據(jù),Cache,和指令,Cache,具有更高的指,令和數(shù)據(jù)處理能力,ARM,Advanced RISC Mach

6、ines,ARM9E,微處理器系列,支持,DSP,指令集，適合于需要高速數(shù)字信號處理的,場合,5,級整數(shù)流水線，指令執(zhí)行效率更高,支持,32,位,ARM,指令集和,16,位,Thumb,指令集,支持,32,位的高速,AMBA,總線接口,支持,VFP9,浮點處理協(xié)處理器,全性能的,MMU,支持,Windows,CE,Linux,Palm,OS,等多種主流嵌入式操作系統(tǒng),MPU,支持實時操作系統(tǒng),支持數(shù)據(jù),Cache,和指令,Cache,具有更高的指令和數(shù),據(jù)處理能力,主頻最高可達,300MIPS,ARM,Advanced RISC Machines,ARM10E,微處理器系列,支持,DSP,指令

7、集，適合于需要高速數(shù)字信號處理的,場合,6,級整數(shù)流水線，指令執(zhí)行效率更高,支持,32,位,ARM,指令集和,16,位,Thumb,指令集,支持,32,位的高速,AMBA,總線接口,支持,VFP10,浮點處理協(xié)處理器,全性能的,MMU,支持,Windows,CE,Linux,Palm,OS,等多種主流嵌入式操作系統(tǒng),支持數(shù)據(jù),Cache,和指令,Cache,具有更高的指令和數(shù),據(jù)處理能力,主頻最高可達,400MIPS,內(nèi)嵌并行讀,寫操作部件,ARM,Advanced RISC Machines,StrongARM,微處理器系列,Intel,StrongARM,SA-1100,處理器是采用,AR

8、M,體系結(jié)構(gòu)高度集成的,32,位,RISC,微處理器,融合了,Intel,公司的設(shè)計和處理技術(shù)以及,ARM,體系結(jié)構(gòu)的電源效率,采用在軟件上兼容,ARMv4,體系結(jié)構(gòu)、同時采,用具有,Intel,技術(shù)優(yōu)點的體系結(jié)構(gòu),ARM,Advanced RISC Machines,Xscale,處理器,基于,ARMv5TE,體系結(jié)構(gòu),它支持,16,位的,Thumb,指令和,DSP,指令集,數(shù)字移動電話、個人數(shù)字助理和網(wǎng)絡(luò)產(chǎn)品等,Samsung S3C4510B,簡介,集成,ARM7TDMI,RISC,處理器核,合用于對價格及功耗敏感的應(yīng)用,結(jié)構(gòu)框圖如下,Samsung S3C4510B,簡介,Archit

9、ecture,Integrated system for embedded ethernet,applications,Fully 16/32-bit RISC architecture,Little/Big-Endian mode supported basically, the,internal architecture is big-endian.So, the little,endian mode only support for external memory,Efficient and powerful ARM7TDMI core,Cost-effective JTAG-based

10、 debug solution,Boundary scan,Samsung S3C4510B,簡介,System Manager,8/16/32-bit external bus support for ROM/SRAM,flash memory, DRAM, and external I/O,One external bus master with bus request,acknowledge pins,Support for EDO/normal or SDRAM,Programmable access cycle (0-7 wait cycles,Four-word depth wri

11、te buffer,Cost-effective memory-to-peripheral DMA,interface,Samsung S3C4510B,簡介,Unified Instruction/Data Cache,Two-way, set-associative, unified 8K-byte cache,Support for LRU (least recently used) protocol,Cache is configurable as an internal SRAM,I2C Serial Interface,Master mode operation only,Baud

12、 rate generator for serial clock generation,Samsung S3C4510B,簡介,Ethernet Controller,DMA engine with burst mode,DMA Tx/Rx buffers (256 bytes Tx, 256 bytes Rx,MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes Rx,Data alignment logic,Endian translation,100/10-Mbit per second operation,Full compliance with

13、IEEE standard 802.3,MII and 7-wire 10-Mbps interface,Full-duplex mode with PAUSE feature,Samsung S3C4510B,簡介,HDLCs,HDLC protocol features,Selectable CRC or No CRC mode,Automatic CRC generator preset,Baud rate generator,NRZ/NRZI/FM/Manchester data formats for Tx/Rx,Loop-back and auto-echo modes,Tx/Rx

14、 FIFOs have 8-word (8,32-bit) depth,Endian translation,Programmable interrupts,Modem interface,Up to 10 Mbps operation,2-channel DMA buffer descriptor for Tx/Rx on each HDLC,Samsung S3C4510B,簡介,UARTs,Two UART (serial I/O) blocks with DMA-based or interrupt,based operation,Support for 5-bit, 6-bit, 7

15、-bit, or 8-bit serial data transmit,and receive,Programmable baud rates,1 or 2 stop bits,Odd or even parity,Break generation and detection,Parity, overrun, and framing error detection,16 clock mode,Infra-red (IR) Tx/Rx support (IrDA,Samsung S3C4510B,簡介,Timers,Two programmable 32-bit timers,Interval

16、mode or toggle mode operation,Programmable I/O,18 programmable I/O ports,Pins individually configurable to input, output, or,I/O mode for dedicated signals,Samsung S3C4510B,簡介,Interrupt Controller,21 interrupt sources, including 4 external interrupt,sources,Normal or fast interrupt mode (IRQ, FIQ,Pr

17、ioritized interrupt handling,Samsung S3C4510B,簡介,Operating Voltage Range,3.3 V,5,Operating Temperature Range,0,C to + 70,C,Operating Frequency,Up to 50 MHz,Package Type,208-Pin QFP,Samsung S3C4510B,Samsung S3C4510B,簡介,系統(tǒng)配置(8,JTAG(5,存儲器接口,83,Ethernet(18,HDLC(9*2,UART(5*2,I,2,C(2,PIO18,INT4,DMA2*2,TIM

18、ER2,18,Samsung S3C4510B,簡介,Samsung S3C4510B,簡介,Samsung S3C4510B,簡介,Samsung S3C4510B,簡介,Samsung S3C4510B,簡介,Samsung S3C4510B,簡介,Samsung S3C4510B,簡介,Samsung S3C4510B,編程,處理器,2,種狀態(tài),ARM,執(zhí)行,32-bit, word-aligned ARM,指令,THUMB,執(zhí)行,16-bit, half-word-aligned THUMB,指令,優(yōu)點,根據(jù)需要優(yōu)化存儲,狀態(tài)之間方便轉(zhuǎn)換,Samsung S3C4510B,編程,存儲格

19、式,byte order,Big-Endian,Msb is low addr,Addrss by MSB,Little-Endian,Lsb is low addr,Addrss by LSB,Samsung S3C4510B,編程,存儲格式,byte order,0 x12,0 x78,0 x56,0 x34,Example: ADDRESS:0 x10000 DATA:0 x12345678,0 x10000 0 x10001 0 x10002 0 x10003,0 x78,0 x12,0 x34,0 x56,字節(jié)地址,大端存儲模式,小端存儲模式,對嵌入式系統(tǒng),當直接操作硬件時,字節(jié)順序

20、很重要,S3C4510,內(nèi)部為,Big-endian,外部可以通過配置引腳選擇外部數(shù)據(jù)存儲方式,Samsung S3C4510B,編程,ARM7TDMI,支持,7,種操作模式,User (usr,正常操作狀態(tài),FIQ (fiq,數(shù)據(jù)傳輸、通道處理中斷,IRQ (irq,一般中斷處理,Supervisor (svc,系統(tǒng)保護模式,Abort mode (abt,取指出錯,System (sys,超級用戶模式,Undefined (und,非法指令時進入該狀態(tài),Samsung S3C4510B,編程,ARM7TDMI 31,個寄存器,31,個,32,位通用寄存器,6,個狀態(tài)寄存器,Samsung

21、S3C4510B,編程,ARM7TDMI 31,個寄存器,Samsung S3C4510B,編程,ARM7TDMI,指令集,指令少，但與條件組合非常復雜,在此不詳細講解,無論使用,uClinux,還是,VxWorks,在移植過,程中僅需要很少匯編指令,Samsung S3C4510B,編程,ARM7TDMI,指令例子,設(shè)置,SYSCFG,寄存器,ldr,r0, =SYSCFG,* Cache Off, Write Buffer Off, 4K SRAM, 4K CACHE *,ldr,r1, =0 x87ffff80,str,r1, r0,Samsung S3C4510B,系統(tǒng)管理,總線仲裁,

22、比較簡單，固定優(yōu)先級,提供存儲器控制信號,重點討論,Samsung S3C4510B,系統(tǒng)管理,5*(ROM/SRAM/FLASH)+ 4*(DRAM/SDRAM)+ 4*(EXTIO) + 8K ISRAM+16K SPR,可以把它們定義在,64M,存儲空間的任意位置,存儲器映像,Samsung S3C4510B,系統(tǒng)管理,系統(tǒng)啟動時存儲器映像,啟動時，除,CS0,外，其它均無效,CS0,接,BootRom,放置啟動代碼,BSP/BIOS/Boot loader,Samsung S3C4510B,系統(tǒng)管理,系統(tǒng)管理寄存器,Samsung S3C4510B,系統(tǒng)管理,系統(tǒng)配置寄存器,0,必須為

23、零,1,Cache Enable,2:Write Buffer Enable 5-4:Cache Mode(cache,與,sram,劃分,15-6:Internal SRAM base pointer,表示內(nèi)部,SRAM,的,A25-A16,25-16:Special register bank base pointer,表示,SPR,基地址，以,64K,為單位,30-26,產(chǎn)品,ID,00001 = S3C4510X (KS32C50100,11001 = S3C4510B,31:DRAM,還是,SDRAM,0 x37ffff91,含義：內(nèi)部,SRAM,基地址,0 x3fe0000,SPR

24、,基地址為,0 x3ff0000,Samsung S3C4510B,系統(tǒng)管理,時鐘控制寄存器,15:0 Clock diving value,If all bits are 0, non-divided clock is used. Only one bit can,be set in CLKCON15:0. That is, the clock diving value is,defined as 1,2,4,8,16,.Internal system clock, fMCLK,fICLK/(CLKCON+1,16 ROM bank 5 wait enable,17 ROM bank 5 a

25、ddress/data bus MUX enable,19:18 MUX bus Address (tAC,31 Test bit,This bit should be always 0,Samsung S3C4510B,系統(tǒng)管理,系統(tǒng)時鐘,Note:CLKSEL=1,外部時鐘,Samsung S3C4510B,系統(tǒng)管理,EXTERNAL I/O ACCESS CONTROL,REGISTERS (EXTACON0/1,2,個,32bit,寄存器,設(shè)置,4,個,EXTIO banks,每個,bank,設(shè)置,4,個時間,tCOSx :Chip selection set-up time on n

26、OE,tACSx: Address set-up time before nECS,tCOHx:Chip selection hold time on nOE,tACCx:Access cycles (nOE low time,Samsung S3C4510B,系統(tǒng)管理,EXTERNAL I/O ACCESS CONTROL,REGISTERS (EXTACON0/1,tACS = 0 (0 cycle) tCOS = 0 (0 cycle,tACC = 4 (5 cycles) tCOH = 0 (0 cycle,Samsung S3C4510B,系統(tǒng)管理,DATA BUS WIDTH RE

27、GISTER,EXTDBWTH,DSRx:ROM/SRAM/FLASH,DSDx:DRAM/SDRAM,DSXx:EXTIO,B0SIZE1:0 = , 8 bits,B0SIZE1:0 = , 16 bits,B0SIZE1:0 = , 32 bits,注意,啟動時,DSR0,由,B0SIZE,確定,Samsung S3C4510B,系統(tǒng)管理,ROM/SRAM/FLASH CONTROL,REGISTERS (ROMCON,Samsung S3C4510B,系統(tǒng)管理,ROM/SRAM/FLASH CONTROL,REGISTERS (ROMCON,1:0 Page mode configur

28、ation (PMC,00 = Normal ROM 01 = 4-word page,10 = 8-word page 11 = 16-word page,3:2 Page address access time (tPA,00 = 5 cycles 01 = 2 cycles,10 = 3 cycles 11 = 4 cycles,6:4 Programmable access cycle (tACC,000 = Disable bank 001 = 2 cycles,010 = 3 cycle 011 = 4 cycles,110 = 7 cycle 111 = Reserved,19:

29、10 ROM/SRAM/Flash bank # base pointer,base pointer 16,29:20 ROM/SRAM/FLASH bank # next pointer,This value is the current bank end address 16 + 1,Samsung S3C4510B,系統(tǒng)管理,ROM/SRAM/FLASH CONTROL,REGISTERS (ROMCON,Normal,tACC = 4 (5 cycles,Samsung S3C4510B,系統(tǒng)管理,ROM/SRAM/FLASH CONTROL,REGISTERS (ROMCON,tAC

30、C = 2 (3 cycles) tPA = 1 (2 cycles,PMC = 1 (4 word page,Samsung S3C4510B,系統(tǒng)管理,DRAM CONTROL REGISTERS,0 EDO mode (EDO,0 = Normal 1 = EDO DRAM,2:1 CAS strobe time (tCS) 3:3 CAS pre-charge time (tCP) 6:4 Reserved,7 RAS to CAS delay (tRC or tRCD,0 = 1 cycle 1 = 2 cycles,9:8 RAS pre-charge time (tRP,00 =

31、 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles,19:10 DRAM bank # base pointer,base pointer 16,29:20 DRAM bank # next pointer,current bank end address 16 + 1,31:30 Number of column address bits in DRAM bank # (CAN,00 = 8 bits 01 = 9 bits,10 = 10 bits 11 = 11 bits,Samsung S3C4510B,系統(tǒng)管理,DRAM CONTROL REGISTERS,Samsung S3C4510B,系統(tǒng)管理,DRAM CONTROL REGISTERS,Col:9,Row:13,Bank:2,SIZE:=16M,CPU,內(nèi)部地址信號,A0-A8 A9-A21 A22,Col Row Bnk,引腳信號,A0-A8 A0-A12 A13,對照上表,CAN,應(yīng)為,01,Samsung S3C4510B,系統(tǒng)管理,DRAM REFRESH AND EXTERNAL I/O,CONTROL REGISTER(R