串行4路DA轉(zhuǎn)換器TLC5620的英文數(shù)據(jù)手冊

1、tlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised november 20011post office box 655303 ? dallas, texas 75265dfour 8-bit voltage output dacsd5-v single-supply operationdserial interfacedhigh-impedance reference inputsdprogrammable 1 or 2 times output rangeds

2、imultaneous update facilitydinternal power-on resetdlow-power consumptiondhalf-buffered outputapplicationsdprogrammable voltage sourcesddigitally controlled amplifiers/attenuatorsdmobile communicationsdautomatic test equipmentdprocess monitoring and controldsignal synthesisdescriptionthe tlc5620c an

3、d tlc5620i are quadruple 8-bit voltage output digital-to-analog converters (dacs) withbuffered reference inputs (high impedance). the dacs produce an output voltage that ranges between eitherone or two times the reference voltages and gnd, and the dacs are monotonic. the device is simple to use,runn

4、ing from a single supply of 5 v. a power-on reset function is incorporated to ensure repeatable start-upconditions.digital control of the tlc5620c and tlc5620i are over a simple three-wire serial bus that is cmos compatibleand easily interfaced to all popular microprocessor and microcontroller devic

5、es. the 11-bit command wordcomprises eight bits of data, two dac-select bits, and a range bit, the latter allowing selection between the times1 or times 2 output range. the dac registers are double buffered, allowing a complete set of new values to bewritten to the device, then all dac outputs are u

6、pdated simultaneously through control of ldac. the digitalinputs feature schmitt triggers for high noise immunity.the 14-terminal small-outline (d) package allows digital control of analog functions in space-criticalapplications. the tlc5620c is characterized for operation from 0 c to 70 c. the tlc5

7、620i is characterizedfor operation from 40 c to 85 c. the tlc5620c and tlc5620i do not require external trimming.available optionspackagetasmall outline(d)plastic dip(n)0 c to 70 ctlc5620cdtlc5620cn 40 c to 85 ctlc5620idtlc5620inplease be aware that an important notice concerning availability, stand

8、ard warranty, and use in critical applications oftexas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.1234 567141312111098gndrefarefbrefcrefddataclkvddldacdacadacbdaccdacdloadn or d package(top view)production data in ormation is current as o publica

9、tion date.products conform to specifications per the terms of texas instrumentsstandard warranty. production processing does not necessarily includetesting of all parameters.copyright 2001, texas instruments incorporatedtlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november

10、1994 revised november 20012post office box 655303 ? dallas, texas 75265functional block diagramdacdacpower-onresetserialinterface 2latchlatchlatchlatchdac 2 2latchlatchlatchlatchdac 2ldac refa+ refb refc clkrefddataloaddacadacbdaccdacd888888882345768131211109terminal functionsterminalnameno.i/odescr

11、iptionclk7iserial interface clock. the input digital data is shifted into the serial interfaceregister on the falling edge of the clock applied to the clk terminal.daca12odac a analog outputdacb11odac b analog outputdacc10odac c analog outputdacd9odac d analog outputdata6iserial interface digital da

12、ta input. the digital code for the dac is clocked into theserial interface register serially. each data bit is clocked into the register on thefalling edge of the clock signal.gnd1iground return and reference terminalldac13iload dac. when the ldac signal is high, no dac output updates occur whenthe

13、input digital data is read into the serial interface. the dac outputs are onlyupdated when ldac is taken from high to low.load8iserial interface load control. when ldac is low, the falling edge of the loadsignal latches the digital data into the output latch and immediately produces theanalog voltag

14、e at the dac output terminal.refa2ireference voltage input to dac a. this voltage defines the output analog range.refb3ireference voltage input to dac b. this voltage defines the output analog range.refc4ireference voltage input to dac c. this voltage defines the output analog range.refd5ireference

15、voltage input to dac d. this voltage defines the output analog range.vdd14ipositive supply voltagetlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised november 20013post office box 655303 ? dallas, texas 75265detailed descriptionthe tlc5620 is implemented usin

16、g four resistor-string dacs. the core of each dac is a single resistor with256 taps, corresponding to the 256 possible codes listed in table 1. one end of each resistor string is connectedto the gnd terminal and the other end is fed from the output of the reference input buffer. monotonicity ismaint

17、ained by use of the resistor strings. linearity depends upon the matching of the resistor elements and uponthe performance of the output buffer. since the inputs are buffered, the dacs always present a high-impedanceload to the reference source.each dac output is buffered by a configurable-gain outp

18、ut amplifier that can be programmed to times 1 or times2 gain.on power up, the dacs are reset to code 0.each output voltage is given by:vo(daca|b|c|d) + refcode256(1 )rng bit value)where code is in the range 0 to 255 and the range (rng) bit is 0 or 1 within the serial control word.table 1. ideal out

19、put transferd7d6d5d4d3d2d1d0output voltage00000000gnd00000001(1/256) ref (1+rng)?01111111(127/256) ref (1+rng)10000000(128/256) ref (1+rng)?11111111(255/256) ref (1+rng)data interfacewith load high, data is clocked into the data terminal on each falling edge of clk. once all data bits havebeen clock

20、ed in, load is pulsed low to transfer the data from the serial input register to the selected dac asshown in figure 1. when ldac is low, the selected dac output voltage is updated when load goes low. whenldac is high during serial programming, the new value is stored within the device and can be tra

21、nsferred tothe dac output at a later time by pulsing ldac low as shown in figure 2. data is entered most significant bit(msb) first. data transfers using two 8-clock cycle periods are shown in figures 3 and 4.rnga1a0d7d6d5d4d3d2d1d0dac updateclkdataloadtsu(data-clk)tv(data-clk)tsu(clk-load)tw(load)t

22、su(load-clk)figure 1. load-controlled update (ldac = low)tlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised november 20014post office box 655303 ? dallas, texas 75265rngclkdataloadldacdac updatea1a0d7d6d5d4d3d2d1d0tsu(data-clk)tv(data-clk)tw(ldac)tsu(load-ld

23、ac)figure 2. ldac-controlled updatea1a0rngd7d6d5d4d3d2d1d0clkdataloadldacclk lowfigure 3. load-controlled update using 8-bit serial word (ldac = low)a1a0rngd7d6d5d4d3d2d1d0clkdataloadldacclk lowfigure 4. ldac-controlled update using 8-bit serial wordtable 2 lists the a1 and a0 bits and the selection

24、 of the updated dacs. the rng bit controls the dac outputrange. when rng = low, the output range is between the applied reference voltage and gnd, and whenrng = high, the range is between twice the applied reference voltage and gnd.table 2. serial input decodea1a0dac updated00daca01dacb10dacc11dacdt

25、lc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised november 20015post office box 655303 ? dallas, texas 75265linearity, offset, and gain error using single-end supplieswhen an amplifier is operated from a single supply, the voltage offset can still be either

26、positive or negative. witha positive offset voltage, the output voltage changes on the first code change. with a negative offset the outputvoltage may not change with the first code depending on the magnitude of the offset voltage.the output amplifier attempts to drive the output to a negative volta

27、ge. however, because the most negativesupply rail is ground, the output cannot drive below ground and clamps the output at 0 v.the output voltage then remains at zero until the input code value produces a sufficient positive output voltageto overcome the negative offset voltage, resulting in the tra

28、nsfer function shown in figure 5.dac codeoutputvoltage0 vnegativeoffsetfigure 5. effect of negative offset (single supply)this offset error, not the linearity error, produces this breakpoint. the transfer function would have followed thedotted line if the output buffer could drive below ground.for a

29、 dac, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) afteroffset and full scale are adjusted out or accounted for in some way. however, single-supply operation does notallow for adjustment when the offset is negative due to the breakpoint in the trans

30、fer function. so the linearityis measured between full-scale code and the lowest code that produces a positive output voltage. the code iscalculated from the maximum specification for the negative offset voltage.tlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 rev

31、ised november 20016post office box 655303 ? dallas, texas 75265equivalent inputs and outputsgndvrefinputvddto dacresistorstring_+vdddacvoltage outputisink60 atypical84 k?84 k? 1 2outputrangeselectinput fromdecoded dacregister stringinput circuitoutput circuitgndabsolute maximum ratings over operatin

32、g free-air temperature range (unless otherwise noted)?supply voltage (vdd gnd) 7 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage range gnd 0.3 v to vdd + 0.3 v. . . . . . . . . . . . . . . . . .

33、. . . . . . . . . . . . . . . . . . . . . . . . . . . reference input voltage range, vid gnd 0.3 v to vdd + 0.3 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, ta:tlc5620c 0 c to 70 c. . . . . . . . . . . . . . . . . . . . . . . . .

34、. . . . . . . . . . . tlc5620i 40 c to 85 c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, tstg 50 c to 150 c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from

35、 case for 10 seconds 260 c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?stresses beyond those listed under “ absolute maximum ratings ” may cause permanent damage to the device. these are stress ratings only, andfunctional operation of the device at these or any other conditions bey

36、ond those indicated under “ recommended operating conditions” is notimplied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.recommended operating conditionsminnommaxunitsupply voltage, vdd4.755.25vhigh-level input voltage, vih0.8 vddvlow-level input

37、voltage, vil0.8vreference voltage, vref a|b|c|dvdd 1.5vanalog full-scale output voltage, rl = 10 k?3.5vload resistance, rl10k?setup time, data input, tsu(data-clk) (see figures 1 and 2)50nsvalid time, data input valid after clk , tv(data-clk) (see figures 1 and 2)50nssetup time, clk eleventh falling

38、 edge to load, tsu(clk-load) (see figure 1)50nssetup time, load to clk , tsu(load-clk) (see figure 1)50nspulse duration, load, tw(load) (see figure 1)250nspulse duration, ldac, tw(ldac) (see figure 2)250nssetup time, load to ldac , tsu(load-ldac) (see figure 2)0nsclk frequency1mhzoperating free air

39、temperaturettlc5620c070 coperating free-air temperature, tatlc5620i 4085 ctlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised november 20017post office box 655303 ? dallas, texas 75265electrical characteristics over recommended operating free-air temperature

40、range, vdd = 5 v 5%,vref = 2 v, 1 gain output range (unless otherwise noted)parametertest conditionsmintypmaxunitiihhigh-level input currentvi = vdd10 aiillow-level input currentvi = 0 v10 aio(sink)output sink currenteach dac output20 aio(source)output source currenteach dac output2maiinput capacita

41、nce15creference input capacitance15pfiddsupply currentvdd = 5 v2mairefreference input currentvdd = 5 v,vref = 2 v10 aellinearity error (end point corrected)vref = 2 v,2 gain (see note 1) 1lsbeddifferential-linearity errorvref = 2 v,2 gain (see note 2) 0.9lsbezszero-scale errorvref = 2 v,2 gain (see

42、note 3)030mvzero-scale-error temperature coefficientvref = 2 v,2 gain (see note 4)10 v/ cefsfull-scale errorvref = 2 v,2 gain (see note 5)60mvfull-scale-error temperature coefficientvref = 2 v,2 gain (see note 6) 25 v/ cpsrrpower-supply rejection ratiosee notes 7 and 80.5mv/vnotes:1.integral nonline

43、arity (inl) is the maximum deviation of the output from the line between zero and full scale (excluding the effectsof zero code and full-scale errors).2.differential nonlinearity (dnl) is the difference between the measured and ideal 1 lsb amplitude change of any two adjacent codes.monotonic means t

44、he output voltage changes in the same direction (or remains constant) as a change in the digital input code.3.zero-scale error is the deviation from zero voltage output when the digital input code is zero.4.zero-scale-error temperature coefficient is given by: zsetc = zse(tmax) zse(tmin)/vref 106/(t

45、max tmin).5.full-scale error is the deviation from the ideal full-scale output (vref 1 lsb) with an output load of 10 k?.6.full-scale-error temperature coefficient is given by: fsetc = fse(tmax) fse (tmin)/vref 106/(tmax tmin).7.zero-scale-error rejection ratio (zse rr) is measured by varying the vd

46、d from 4.5 v to 5.5 v dc and measuring the proportion ofthis signal imposed on the zero-code output voltage.8.full-scale-error rejection ratio (fse rr) is measured by varying the vdd from 4.5 v to 5.5 v dc and measuring the proportion ofthis signal imposed on the full-scale output voltage.operating

47、characteristics over recommended operating free-air temperature range, vdd = 5 v 5%,vref = 2 v, 1 gain output range (unless otherwise noted)test conditionsmintypmaxunitoutput slew ratecl = 100 pf,rl = 10 k?1v/ soutput settling timeto 0.5 lsb,cl = 100 pf,rl = 10 k ?,see note 910 slarge-signal bandwid

48、thmeasured at 3 db point100khzdigital crosstalkclk = 1-mhz square wave measured at daca-dacd50dbreference feedthroughsee note 1060dbchannel-to-channel isolationsee note 1160dbreference input bandwidthsee note 12100khznotes:9.settling time is the time between a load falling edge and the dac output re

49、aching full scale voltage within +/ 0.5 lsb starting froman initial output voltage equal to zero.10.reference feedthrough is measured at any dac output with an input code = 00 hex with a vref input = 1 v dc + 1 vpp at 10 khz.11.channel-to-channel isolation is measured by setting the input code of on

50、e dac to ff hex and the code of all other dacs to 00 hexwith vref input = 1 v dc + 1 vpp at 10 khz.12.reference bandwidth is the 3 db bandwidth with an input at vref = 1.25 v dc + 2 vpp and with a full-scale digital-input code.tlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e no

51、vember 1994 revised november 20018post office box 655303 ? dallas, texas 75265parameter measurement information10 k?cl = 100 pftlc5620dacadacb?dacdfigure 6. slew, settling time, and linearity measurementstypical characteristicsfigure 7024681012141618t time svdd = 5 vta = 25 ccode 00 to ff hexrange =

52、 2vref = 2 v3102ldacoutputvoltagevvopositive rise and settling timefigure 8024681012141618t time s3102ldacvdd = 5 vta = 25 ccode ff to 00 hexrange = 2vref = 2 voutputvoltagevvonegative fall and settling timetlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised

53、november 20019post office box 655303 ? dallas, texas 75265typical characteristicsfigure 934.83.60102030405060dacoutputvoltagevdac output voltagevsoutput load5708090100vorl output load k?vdd = 5 v,vref = 2.5 v,range = 2xfigure 1021.50.5001020304050602.53.5470809010013dac output vol

54、tagevsoutput loadvdd = 5 v,vref = 3.5 v,range = 1xdacoutputvoltagevvorl output load k?figure 1143100123outputsourcecurrentma57output source currentvsoutput voltage84526vdd = 5 vta = 25 cvref = 2 vrange = 2input code = 255io(source)vo output voltage vfigure 1210.90.850.8supplycurrentma1.11.15supply c

55、urrentvstemperature1.21.050.95 50050100vdd = 5 vvref 2 vrange = 2input code = 255iddt temperature ctlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised november 200110post office box 655303 ? dallas, texas 75265typical characteristicsfigure 13110100grelativega

56、indbf frequency khzrelative gainvsfrequency10000 2 4 6 8 10 12 14 16 18 20vdd = 5 vta = 25 cvref = 1.25 vdc + 2 vppinput code = 255figure 141101001000grelativegaindbf frequency khzrelative gainvsfrequency10000100 10 20 30 40 50 60vdd = 5 vta = 25 cvref = 2 vdc + 0.5 vppinput code = 255application in

57、formationnote a:resistor r w 10 k?rtlc5620dacadacb?dacd_+vofigure 15. output buffering schemetlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised november 200111post office box 655303 ? dallas, texas 75265mechanical datad (r-pdso-g*) plastic small-outline pack

58、age14 pin shown4040047/ b 10/940.228 (5,80)0.244 (6,20)0.069 (1,75) max0.010 (0,25)0.004 (0,10)1140.014 (0,35)0.020 (0,51)a0.157 (4,00)0.150 (3,81)780.044 (1,12)0.016 (0,40)seating plane0.010 (0,25)pins *0.008 (0,20) noma mina maxdimgage plane0.189(4,80)(5,00)0.1978(8,55)(8,75)0.337140.344(9,80)160.

59、394(10,00)0.3860.004 (0,10)m0.010 (0,25)0.050 (1,27)0 8notes:a.all linear dimensions are in inches (millimeters).b.this drawing is subject to change without notice.c.body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).d.four center pins are connected to die mount pad.e

60、.falls within jedec ms-012tlc5620c, tlc5620iquadruple 8-bit digital-to-analog convertersslas081e november 1994 revised november 200112post office box 655303 ? dallas, texas 75265mechanical datan (r-pdip-t*) plastic dual-in-line package200.975(24,77)0.940(23,88)180.9200.850140.7750.745(19,69)(18,92)1