51單片機中英文資料

1、AT89S51單片機中英文資料2009-05-08 16:07中文資料：http:/www.go-AT89S51 (8位微控制單片機，片內(nèi)含4K bytes可系統(tǒng)編程的存儲器)AT89S51是美國ATMEL公司生產(chǎn)的低功耗，高性能CMOS 8位單片機，片內(nèi)含4k bytes的可系統(tǒng)編程的Flash只讀程序存儲器，器件采用ATMEL公司的高密度、非易失性存儲技術(shù)生產(chǎn)，兼容標準8051指令系統(tǒng)及引腳。它集Flash程序存儲器既可在線編程（ISP)也可用傳統(tǒng)方法進行編程及通用8位微處理器于單片芯片中，ATMEL公司的功能強大，低價位AT89S51單片機可為您提供許多高性價比的應(yīng)用場介，可靈活應(yīng)用于各

2、種控制領(lǐng)域。主要性能參數(shù)：·與MCS-51 產(chǎn)品指令系統(tǒng)完全兼:容·4k字節(jié)在線系統(tǒng)編程(ISP) Flash閃速存儲器·1000次擦寫周期·4. 0-5. 5V的工作電壓范圍·全靜態(tài)工作模式：0Hz-33MHz·三級程序加密鎖·128×8字節(jié)內(nèi)部RAM·32個可編程I/O口線·2個16位定時/計數(shù)器·6個中斷源·全雙工串行UART通道·低功耗空閑和掉電模式·中斷可從空閑模式喚醒系統(tǒng)·看門狗(WDT)及雙數(shù)據(jù)指針·掉電標識和快速編程特性

3、·靈活的在線系統(tǒng)編程(ISP一字節(jié)或頁寫模式)功能特性概述：    AT89S51提供以下標準功能：4k字節(jié)Flash閃速存儲器，128字節(jié)內(nèi)部RAM， 32個I/O口線，看門狗（WDT），兩個數(shù)據(jù)指針，兩個16位定時/計數(shù)器，一個5向量兩級中斷結(jié)構(gòu)，一個全雙工串行通信口，片內(nèi)振蕩器及時鐘電路。同時，AT89S51可降至0Hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式。空閑方式停止CPU的工作，但允許RAM，定時/計數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個硬件復(fù)位。引腳功能說明

4、：    ·Vcc： 電源電壓    ·GND：地    ·P0口：P0口是一組8位漏極開路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口用時，每位能驅(qū)動8個TTL邏輯門電路，對端口寫1可作為高阻抗輸入端用。      在訪問外部數(shù)據(jù)存儲器或程序存儲器時，這組口線分時轉(zhuǎn)換地址(低8位)和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。      在Flash編程時，P0 口接收

5、指令字節(jié)，而在程序校驗時，輸出指令字節(jié)，校驗時，要求外接上拉電阻。   ·P1口：P1是一個帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級可驅(qū)動(吸收或輸出電流)4個TTL邏輯門電路。對端口寫1，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口。作輸入口使用時，囚為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流(In)。    Flash編程和程序校驗期間 P 1接收低8位地址。   ·P2口：P2是一個帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級可驅(qū)動(吸收或輸出電流)4個TTL

6、邏輯門電路。對端口寫1，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口，作輸入口使用時，囚為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流(In)。在訪問外部程序存儲器或16位地址的外部數(shù)據(jù)存儲器(例如執(zhí)行MOVX DPTR指令)時，P2口送出高 8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲器(如執(zhí)行MOVX Ri指令)時，P2口線卜的內(nèi)容(也即特殊功能寄存器（SFR)區(qū)中P2寄存器的內(nèi)容)，在整個訪問期間不改變。    Flash編程或校驗時，P2亦接收高位地址和其它控制信號。     ·P3口：P3

7、口是一組帶有內(nèi)部上拉電阻的8位雙向I/O口。P3口輸出緩沖級可驅(qū)動(吸收或輸出電流)4個TTL邏輯門電路。對P3 口寫入“1”時，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時，被外部拉低的P3 口將用上拉電阻輸出電流（In）。 P3口除了作為一般的I/O口線外，更重要的用途是它的第二功能。P3 口還接收一些用于Flash閃速存儲器編程和程序校驗的控制信號。·RST：復(fù)位輸入。當(dāng)振蕩器工作時，RST引腳出現(xiàn)兩個機器周期以上高電平將使單片機復(fù)位。WDT溢出將使該引腳輸出高電平，設(shè)置SFR AUXR 的DISRTO位（地址8EH）可打開或關(guān)閉該功能。DISRTO位缺省為RESET輸出

8、高電平打開狀態(tài)。·ALE/PROG：當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時，ALE(地址鎖存允許)輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲器，ALE仍以時鐘振蕩頻率的1/6輸出固定的正脈沖信號，囚此它可對外輸出時鐘或用于定時目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時將跳過一個ALE脈沖。對Flash存儲器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過對特殊功能寄存器（SFR)區(qū)中的8EH單元的D0位置位，可禁正ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會被激活。此外，該引腳會被微弱拉高，單片機執(zhí)行外部程序時，應(yīng)設(shè)置ALE無效。·

9、PSEN：程序儲存允許(PSEN)輸出是外部程序存儲器的讀選通信號，當(dāng)AT89S51由外部程序存儲器取指令(或數(shù)據(jù))時，每個機器周期兩次PSEN有效，即輸出兩個脈沖。當(dāng)訪問外部數(shù)據(jù)存儲器，沒有兩次有效的PSEN信號。·EA/VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲器(地址為0000H-FFFFH), EA端必須保持低電平(接地)。需注意的是：如果加密位LB1被編程，復(fù)位時內(nèi)部會鎖存EA端狀態(tài)。如EA端為高電平(接Vcc端)，CPU則執(zhí)行內(nèi)部程序存儲器中的指令。Flash存儲器編程時，該引腳加上+12 V的編程電壓Vpp。·XTAL 1：振蕩器反相放大器及內(nèi)部時鐘發(fā)

10、生器的輸入端。·XTAL2：振蕩器反相放大器的輸出端。·特殊功能寄存器：    特殊功能寄存器的于片內(nèi)的空間分布的這些地址并沒有全部占用，沒有占用的地址亦不可使用，讀這些地址將得到一個隨意的數(shù)值。而寫這些地址單元將不能得到預(yù)期的結(jié)果。·中斷寄存器：各中斷允許控制位于IE寄存器，5個中斷源的中斷優(yōu)先級控制位于IP寄存器。·雙時鐘指針寄存器：   為更方便地訪問內(nèi)部和外部數(shù)據(jù)存儲器，提供了兩個16位數(shù)據(jù)指針寄存器：DP0位于SFR(特殊功能寄存器)區(qū)塊中的地址82H, 83H和DP1位于地址84H, 85H，

11、當(dāng)SFR中的位DPS=0選擇DP0，而DPS=1則選擇DP1。用戶應(yīng)在訪問相應(yīng)的數(shù)據(jù)指針寄存器前初始化DPS位。·電源空閑標志：    電源空閑標志（POF）在特殊功能寄存器SFR中PCON的第4位(PCON.4，電源打開時POF置1，它可由軟件設(shè)置睡眠狀態(tài)并不為復(fù)位所影響。·程序存儲器：    如果EA引腳接地(GND)，全部程序均執(zhí)行外部存儲器。在AT89S51,假如EA接至Vcc(電源+)，程序首先執(zhí)行地址從0000H-OFFFH （4KB）內(nèi)部程序存儲器，而執(zhí)行地址為1000H-FFFFH (60KB)的外

12、部程序存儲器。·數(shù)據(jù)存儲器：AT89S51的具有128字節(jié)的內(nèi)部RAM，這128字節(jié)可利用直接或間接尋址方式訪問，堆棧操作可利用間接尋址方式進行，128字節(jié)均可設(shè)置為堆棧區(qū)空間。·看門狗定時器(WDT)：WDT是為了解決CPU程序運行時可能進入混亂或死循環(huán)而設(shè)置，它由一個14bit計數(shù)器和看門狗復(fù)位SFR (WDTRST)構(gòu)成。外部復(fù)位時，WDT默認為關(guān)閉狀態(tài)，要打開WDT，用戶必須按順序?qū)?1EH和0E1H寫到WDTRST寄存器（SFR地址為OA6H,當(dāng)啟動了WDT，它會隨晶體振蕩器在每個機器周期計數(shù)，除硬件復(fù)位或WDT溢出復(fù)位外沒有其它方法關(guān)閉WDT，當(dāng)WDT溢出，將使

13、RSF引腳輸出高電平的復(fù)位脈沖。·定時器0和定時器1：定時器0和1都是一個16位定時/計數(shù)器。AT89S51（8-bit Micro controller with 4K Bytes Flash）The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytesof In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile me

14、mory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monoli

15、thic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.Features：.Compatible with MCS.-51 Products4K Bytes of In-System Programmable (ISP) Flash Memory    一Endurance: 1000 Write/Erase

16、 Cycles4.0V to 5.5V Operating RangeFully Static Operation: 0 Hz to 33 MHzThree-level Program Memory Lock128 x 8-bit Internal RAM32 Programmable I/O LinesTwo 16-bit Timer/CountersSix Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down

17、ModeWatchdog TimerDual Data PointerPower-off FlagFast Programming TimeFlexible ISP Programming (Byte and Page Mode)Green (Pb/Halide-free) Packaging OptionThe AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16

18、-bit timer/counters, a five-vector two一level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode

19、stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.VCC：Supply voltage (all packa

20、ges except 42-PDIP).GND：Ground (all packages except 42一PDIP; for 42-PDIP GND connects only the logic core and the embedded program memory).VDD：Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory.PWRVDD：Supply voltage for the 42-PDIP which connects only t

21、he I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage.PWRGND：Ground for the 42一PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application boar

22、d MUST connect both GND and PWRGND to the board ground.Port 0：Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high一impedance inputs.Port 0 can also be configured to be the multip

23、lexed low-order address/data bus during accesses to external program and data memory. In this mode, PO has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verificatio

24、n.Port 1：Port 1 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled

25、low will source current (lip) because of the internal pull一ups.Port 2：Port 2 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull一ups and can be used as inp

26、uts. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal pull一ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVXDPTR). In this a

27、pplication, Port 2 uses strong internal pull一ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVXRI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programmi

28、ng and verification.Port 3：Port 3 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 3 pins that are extern

29、ally being pulled low will source current (lip) because of the pull-ups.Port 3 receives some control signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S51，as shown in the following table.RST：Reset input. A high on this pin for two

30、machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/P

31、ROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may beus

32、ed for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the

33、pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory.When the AT89S51 is executing code from external program memory, PSEN is activated twice each machi

34、ne cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bi

35、t 1 is programmed, EA will be internally latched on reset.EA should be strapped to Vcc for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operat

36、ing circuit.XTAL2：Output from the inverting oscillator amplifierSpecial Function Registers：Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have a

37、n indeterminate effect.User software should not write 1 s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Interrupt Registers:The individual interrupt enable bits are in the IE

38、register. Two priorities can be set for each of the five interrupt sources in the IP register.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.

39、Bit DPS=0 in SFR AUXR1 selects DPO and DPS=1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to "1”during p

40、ower up. It can be set and rest under software control and is not affected by reset.Memory Organization：MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K                           bytes each of external Program and Data Memory can be addressed.