eda課程設計報告(2)

1、.正文一、設計思路1.基于QUASTUS II平臺，利用DDS（直接數(shù)字信號合成）技術，采用VHDL語言，設計一波形信號發(fā)生器。首先根據(jù)對各波形的幅度進行采樣，獲得各波形的波形數(shù)據(jù)表，然后FPGA根據(jù)輸入的時鐘（頻率可根據(jù)要求可變）作為地址信號，從FPGA數(shù)據(jù)線上輸出相應的波形數(shù)據(jù)，再送入實驗板上的D/A轉(zhuǎn)換芯片進行轉(zhuǎn)換為模擬信號，最后送入濾波電路濾波后輸出。2.實驗整體框圖如下：由斜降鋸齒波模塊（dj）、斜升鋸齒波模塊（dz）、方波模塊（fb）、三角波模塊（jcb）、階梯波模塊（jtb）、6選1選擇器（xz）正弦波模塊（zx）以及、譯碼顯示模塊（ym）組成。二、設計輸入文件與調(diào)試；1.分頻器

2、 用4個100分頻器串接實現(xiàn)。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity fenpin isport (clk: in std_logic; clkfen: out std_logic); end fenpin;architecture fenpin of fenpin issignal clk_mid: std_logic;begin process(clk) variable data:integer range 0 to 99; begin if clkevent and

3、 clk=1 then if data=99 then data:=0; clk_mid=not clk_mid; else data:=data+1;end if;nd if;clkfen=clk_mid;end process;end fenpin;2.遞減（鋸齒波）波形數(shù)據(jù)產(chǎn)生模塊設計采用2550循環(huán)加法計數(shù)器實現(xiàn)。設計思路是: reset 是復位信號, 要首先考慮。tmp 是引進的一個中間變量。通過賦值給輸出值。clk 是時鐘信號, 當復位信號有效時, 輸出為1, 輸出最大值設為“255”,最小值設為“0”,從“0”開始, 當時鐘檢測到有上升沿的時候, 輸出就會呈現(xiàn)遞減的趨勢, 減“1

4、”。LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;USE IEEE. STD_LOGIC_UNSIGNED.ALL;ENTITY dj IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END dj;ARCHITECTURE behave OF dj ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN IF reset=0THEN tmp:=11111111; E

5、LSIF clkEVENT AND clk=1THEN IF tmp=00000000THEN Tmp:=11111111; ELSE tmp:=tmp-1; END IF;END IF; q=tmp; END PROCESS;END behave;3.遞增（鋸齒波）波形數(shù)據(jù)產(chǎn)生模塊設計采用0255 循環(huán)加法計數(shù)器實現(xiàn)。與遞減相反。LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY dz IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC

6、_VECTOR (7 DOWNTO 0);END dz;ARCHITECTURE behave OF dz ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN IF reset=0THEN tmp:=00000000; ELSIF clkEVENT AND clk=1THEN IF tmp=11111111THEN tmp:=00000000; ELSE tmp:=tmp+1; END IF; END IF;q=tmp; END PROCESS;END behave;4.方波波形數(shù)據(jù)產(chǎn)生模

7、塊設計采用高/ 低電平實現(xiàn), 用cnt 來控制方波的周期, 用a 的值來控制輸出到底是高電平還是低電平。LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;ENTITY fb IS PORT (clk,reset: IN STD_LOGIC; q:OUT INTEGER RANGE 0 TO 255);END fb; ARCHITECTURE behave OF fb ISSIGNAL a: BIT;BEGIN PROCESS (clk,reset) VARIABLE cnt: INTEGER range 0 to 31; BEGIN IF reset=0THE

8、N A=0; ELSIF clkEVENT AND clk=1THEN IF cnt31 THENCnt:=cnt+1; ELSE cnt:=0; a=NOT a;END IF; END IF; END PROCESS; Process (clk,a) BEGINIF clkEVENT AND clk=1THEN IF a=1THEN Q=255; ELSE Q=0; END IF; END IF;END PROCESS;END behave;5.三角波波形數(shù)據(jù)產(chǎn)生模塊設計采用02550 循環(huán)加/ 減法計數(shù)器實現(xiàn)。LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.AL

9、L;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY jcb IS PORT (clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END jcb;ARCHITECTURE behave OF jcb ISBEGIN PROCESS (clk,reset) VARIABLE tmp: STD_LOGIC_VECTOR (7 DOWNTO 0); VARIABLE a: STD_LOGIC; BEGIN IF reset=0THEN tmp:=00000000; ELSIF clkEVENT AND

10、 clk=1THEN IF a=0THENIF tmp=11111110THEN tmp:=11111111; a:=1; ELSE tmp:=tmp+1; END IF;ELSE IF tmp=00000001THEN tmp:=00000000; a:=0;ELSE tmp:=tmp-1; END IF; END IF;END IF;q=tmp; END PROCESS;END behave6.階梯波形數(shù)據(jù)產(chǎn)生模塊設計可采用八進制計數(shù)器實現(xiàn), 每次階梯常數(shù)為32 。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_uns

11、igned.all;entity jtb isport(clk,reset:in std_logic;q:out std_logic_vector(7 downto 0);end jtb;architecture a of jtb isbeginprocess(clk,reset)variable tmp:std_logic_vector(7 downto 0);beginif reset=0 thentmp:=00000000;else if clkevent and clk=1 thenif tmp=11111111 thentmp:=00000000;elsetmp:=tmp+16;en

12、d if;end if;end if;q=tmp;end process;end a;7.正弦波波形數(shù)據(jù)產(chǎn)生模塊設計采用描點法來描述正弦波,在仿真波形中可以看到輸入輸出引腳設置, 其中clk 輸入時鐘端口, reset 為輸入復位端口, d 為整數(shù)輸出端口, 一個周期選取64 個點, 計算出64 個常數(shù)后, 查表輸出5 。復位信號的級別高于其它信號, 而且低電平是有效電平, 所以整個程序的工作狀態(tài)應處于高電平狀態(tài)。當時鐘檢測到上升沿時,計數(shù)器計數(shù), 描點工作開始。沒達到最大值之前,一直自加, 否則就自動轉(zhuǎn)為“0”。那么首先要確定這64 個點。然后在程序里用case 語句來擇。library i

13、eee;use ieee.std_logic_arith.all;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity zx is port(clk:in std_logic; reset:in std_logic; q:out std_logic_vector(7 downto 0);end zx;architecture behav of zx is signal b:integer range 0 to 63; signal d:integer range 0 to 255;beginprocess(clk)

14、begin if reset=0then b=0; elsif clkevent and clk=1 then if b=63 then b=0; else bddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddnull; end case; end process; qqqqqqqNULL; END CASE; END PROCESS; END behave; 9譯碼library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use ieee.s

15、td_logic_unsigned.all;entity ym is port( clk,rst :in std_logic; data :in std_logic_vector(7 downto 0); sel :out std_logic_vector(2 downto 0); data_disp:out std_logic_vector(6 downto 0);end ym;architecture RTL of ym issignal count :integer range 9 downto 0;signal temp :integer range 4 downto 0;signal

16、 number_h,number_t,number_l:integer range 0 to 9;begin process(data,clk,rst)beginif(rst=0)then number_h=0; number_t=0; number_l=200 AND to_integer(unsigned(data)-200=50)then number_h=2; number_t=5; number_l=200 AND to_integer(unsigned(data)-200=40)then number_h=2; number_t=4; number_l=200 AND to_int

17、eger(unsigned(data)-200=30)then number_h=2; number_t=3; number_l=200 AND to_integer(unsigned(data)-200=20)then number_h=2; number_t=2; number_l=200 AND to_integer(unsigned(data)-200=10)then number_h=2; number_t=1; number_l=200)then number_h=2; number_t=0; number_l=100 AND to_integer(unsigned(data)-1

18、00=90)then number_h=1; number_t=9; number_l=100 AND to_integer(unsigned(data)-100=80)then number_h=1; number_t=8; number_l=100 AND to_integer(unsigned(data)-100=70)then number_h=1; number_t=7; number_l=100 AND to_integer(unsigned(data)-100=60)then number_h=1; number_t=6; number_l=100 AND to_integer(

19、unsigned(data)-100=50)then number_h=1; number_t=5; number_l=100 AND to_integer(unsigned(data)-100=40)then number_h=1; number_t=4; number_l=100 AND to_integer(unsigned(data)-100=30)then number_h=1; number_t=3; number_l=100 AND to_integer(unsigned(data)-100=20)then number_h=1; number_t=2; number_l=100

20、 AND to_integer(unsigned(data)-100=10)then number_h=1; number_t=1; number_l=100)then number_h=1; number_t=0; number_l=90)then number_h=0; number_t=9; number_l=80)then number_h=0; number_t=8; number_l=70)then number_h=0; number_t=7; number_l=60)then number_h=0; number_t=6; number_l=50)then number_h=0

21、; number_t=5; number_l=40)then number_h=0; number_t=4; number_l=30)then number_h=0; number_t=3; number_l=20)then number_h=0; number_t=2; number_l=10)then number_h=0; number_t=1; number_l=to_integer(unsigned(data)-10;elsenumber_h=0;number_t=0;number_l=to_integer(unsigned(data);end if;end process;proc

22、ess( clk,rst,temp,number_h,number_l) begin if(clkevent and clk=1)then if(temp=2)then temp=0; else tempsel=001; countsel=010; countsel=100; countNULL; end case;end process;process(count)begin case count iswhen 0=data_dispdata_dispdata_dispdata_dispdata_dispdata_dispdata_dispdata_dispdata_dispdata_dispnull;end case;end process;end RTL;1.遞減鋸齒波仿真結(jié)果三、仿真與驗證結(jié)果2.遞增鋸齒波仿真結(jié)果3.方波仿真結(jié)果4.階梯波仿真結(jié)果5、三角波仿真結(jié)果6.正弦波仿真結(jié)果四、設計結(jié)論運用VHDL 語言進行智能函數(shù)發(fā)生器功能的設計具有以下優(yōu)勢: 信號發(fā)生器的功能測試與仿真實驗結(jié)果表明, 時序和波形正確, 達到了設計的功能要求