計算機結(jié)構(gòu)英文版課件：Chapter 16 Control Unit Operation

1、William Stallings Computer Organization and Architecture7th EditionChapter 16Control Unit Operation1/45Micro-OperationsA computer executes a programFetch/execute cycleEach cycle has a number of stepssee pipeliningCalled micro-operationsEach step does very littleAtomic operation of CPU2Constituent El

2、ements of Program Execution3Fetch - 4 RegistersMemory Address Register (MAR) Connected to address busSpecifies address for read or write opMemory Buffer Register (MBR) Connected to data busHolds data to write or last data readProgram Counter (PC) Holds address of next instruction to be fetchedInstru

3、ction Register (IR) Holds last instruction fetched4Fetch SequenceAddress of next instruction is in PCAddress (MAR) is placed on address busControl unit issues READ commandResult (data from memory) appears on data busData from data bus copied into MBRPC incremented by 1 (in parallel with data fetch f

4、rom memory)Data (instruction) moved from MBR to IRMBR is now free for further data fetches5Data Flow (Fetch Diagram)(1)(2)(2)(3)(4)6Fetch Sequence (symbolic)t1:MAR - (PC)t2:MBR - (memory) PC - (PC) +1t3:IR - (MBR)(tx = time unit/clock cycle)ort1:MAR - (PC)t2:MBR - (memory)t3:PC - (PC) +1 IR - (MBR)7

5、Rules for Clock Cycle GroupingProper sequence must be followedMAR - (PC) must precede MBR - (memory)Conflicts must be avoidedMust not read & write same register at same timeMBR - (memory) & IR - (MBR) must not be in same cycleAlso: PC - (PC) +1 involves additionUse ALUMay need additional micro-opera

6、tions8Data Flow (Indirect Diagram)(1)(1)(2)9Indirect CycleMAR - (IRaddress) - address field of IRMBR - (memory)IRaddress - (MBRaddress)MBR contains an addressIR is now in same state as if direct addressing had been used(What does this say about IR size?)10Data Flow (Indirect Diagram)(1)(2)(2)(3)(5)(

7、4)(6)(7)(8)11Data Flow (Interrupt Diagram)(2)(3)(1)(4)(5)12Interrupt Cyclet1:MBR -(PC)t2:MAR - save-address PC - routine-addresst3:memory - (MBR)This is a minimumMay be additional micro-ops to get addressesN.B. saving context is done by interrupt handler routine, not micro-ops13Execute Cycle (ADD)Di

8、fferent for each instructione.g. ADD R1,X - add the contents of location X to Register 1 , result in R1t1:MAR - (IRaddress)t2:MBR - (memory)t3:R1 - R1 + (MBR)Note no overlap of micro-operations14Execute Cycle (ISZ)ISZ X - increment and skip if zerot1:MAR - (IRaddress)t2:MBR - (memory)t3:MBR - (MBR)

9、+ 1t4:memory - (MBR) if (MBR) = 0 then PC - (PC) + 1Notes:if is a single micro-operationMicro-operations done during t415Execute Cycle (BSA)BSA X - Branch and save addressAddress of instruction following BSA is saved in XExecution continues from X+1t1:MAR - (IRaddress) MBR - (PC)t2:PC - (IRaddress)

10、memory - (MBR)t3:PC - (PC) + 116Instruction CycleEach phase decomposed into sequence of elementary micro-operationsE.g. fetch, indirect, and interrupt cyclesExecute cycleOne sequence of micro-operations for each opcodeNeed to tie sequences togetherAssume new 2-bit registerInstruction cycle code (ICC

11、) designates which part of cycle processor is in00: Fetch01: Indirect10: Execute11: Interrupt17Flowchart for Instruction Cycle18Functional RequirementsDefine basic elements of processorDescribe micro-operations processor performsDetermine functions control unit must perform19Basic Elements of Proces

12、sorALURegistersInternal data pahsExternal data pathsControl Unit20Types of Micro-operationTransfer data between registersTransfer data from register to externalTransfer data from external to registerPerform arithmetic or logical ops21Functions of Control UnitSequencingCausing the CPU to step through

13、 a series of micro-operationsExecutionCausing the performance of each micro-opThis is done using Control Signals22Control SignalsClockOne micro-instruction (or set of parallel micro-instructions) per clock cycleInstruction registerOp-code for current instructionDetermines which micro-instructions ar

14、e performedFlagsState of CPUResults of previous operationsFrom control busInterruptsAcknowledgements23Model of Control Unit24Control Signals - outputWithin CPUCause data movementActivate specific functionsVia control busTo memoryTo I/O modules25Example Control Signal Sequence - FetchMAR - (PC)Contro

15、l unit activates signal to open gates between PC and MARMBR - (memory)Open gates between MAR and address busMemory read control signalOpen gates between data bus and MBR26Data Paths and Control Signals27Internal OrganizationUsually a single internal busGates control movement of data onto and off the

16、 busControl signals control data transfer to and from external systems busTemporary registers needed for proper operation of ALU28Data Paths and Control SignalsExecute Cycle (ADD)Execute Cycle (ISZ)Execute Cycle (BSA)29Internal OrganizationUsually a single internal busGates control movement of data

17、onto and off the busControl signals control data transfer to and from external systems busTemporary registers needed for proper operation of ALU t1:MAR(IR(address) t2:MBRMemory t3:Y(MBR) t4:Z(AC)+(Y) t5:AC(Z)30CPU with Internal Busc1c2c10c7c8c9c11c3c4c5c631Intel 8085 CPU Block Diagram32Intel 8085 Pi

18、n Configuration33Intel 8085 OUT InstructionTiming Diagram34Hardwired Implementation (1)Control unit inputsFlags and control busEach bit means somethingInstruction registerOp-code causes different control signals for each different instructionUnique logic for each op-codeDecoder takes encoded input a

19、nd produces single outputn binary inputs and 2n outputs35Hardwired Implementation (2)ClockRepetitive sequence of pulsesUseful for measuring duration of micro-opsMust be long enough to allow signal propagationDifferent control signals at different times within instruction cycleNeed a counter with dif

20、ferent control signals for t1, t2 etc.36Control Unit with Decoded InputsPQ=00 Fetch CyclePQ=01 Indirect Cycle PQ=10 Execute CyclePQ=11 Interrupt Cycle37Control Unit with Decoded Inputs38Problems With Hard Wired DesignsComplex sequencing & micro-operation logicDifficult to design and testInflexible d

21、esignDifficult to add new instructions39Required ReadingStallings chapter 1640計算機結(jié)構(gòu)與邏輯設(shè)計 黃正瑾編著第七章 控制單元7.1 計算機中的寄存器及其控制信號7.2 指令的執(zhí)行過程7.3 控制電路的硬件結(jié)構(gòu)7.4 其他類型指令的執(zhí)行過程7.5 微程序控制方式7.6 全硬件數(shù)字系統(tǒng)控制器的設(shè)計41P291 7.5 微程序控制方式每條指令的執(zhí)行過程可以認(rèn)為是按照一定的“微程序”進(jìn)行的，這個“微程序”可以用硬件實現(xiàn)，也可以用軟件實現(xiàn)。所謂微程序控制，就是將執(zhí)行指令的微程序用一條條二進(jìn)制代碼編寫的微指令組成，成為真正意義

22、上的程序，并用此程序來控制指令的執(zhí)行。42AdderRESET IARIARINCREMENT IAR+1C INTO IARADD OP TO IAR ROM 控制存儲器C1.C6 C7.C26(控制命令)來自O(shè)P的操作碼圖 7.9 微程序控制系統(tǒng)框圖IAR: 微指令地址寄存器 (uPC)OP: 剛才存在操作碼寄存器中的數(shù)據(jù)43圖7.10所示是某個計算機微程序控制器中的ROM，它的每條指令的解釋與表7.4相同?，F(xiàn)在以此ROM為例，說明微程序系統(tǒng)中指令的執(zhí)行情況。設(shè)起始時微指令地址寄存器IAR中的數(shù)據(jù)為0，計算機運行后從ROM中取的第一條微指令是0號微指令，其代碼為0000 0000 0000

23、 0010 0000 0010 00，它所發(fā)出的命令為C15和C23,C15是一條向存儲器取指令的操作命令，即執(zhí)行微操作R-1，C23是將微指令地址寄存器IAR中的數(shù)據(jù)加1，于是下一步應(yīng)執(zhí)行1號微指令；44微指令的控制位微操作控制命令C7IC-0RESET ICC8IC-IC+1INCREMENT ICC9IC-MBMB INTO ICC10AC-0RESET ACC11AC-AC+BRADDC12AC-AC-BRSUBSTRACTC13W-1SET WC14W-0RESET WC21OP-MB1115C22BR-MBMB INTO BRC23IAR-IAR+1INCREMENT IARC24

24、IAR-C1C6C INTO IARC25IAR-OP+IAR+1ADD OP TO IARC26 IAR-0RESET IARTABLE 7.4 計算機的微結(jié)構(gòu)451號微指令的代碼為0000 0000 0000 0000 0000 1010 00，它也發(fā)出兩條命令，分別為C21和C23，C21-執(zhí)行OP-MB的操作，將存儲器緩沖寄存器中的操作碼部分送到操作碼寄存器中去，C23-將微指令地址寄存器IAR中的數(shù)據(jù)加1，接下去執(zhí)行2號微指令；2號微指令：3號微指令是一條跳轉(zhuǎn)微指令，將微指令地址寄存器IAR中的地址跳轉(zhuǎn)至C1C6所示的數(shù)據(jù)010100，即20，于是下一步執(zhí)行第20號微指令；20、21、22、23、24號微指令中