串口指令控制fifo環(huán)回功能練習(xí)

1、明德?lián)P科技教育串口指令控制 FIFO 環(huán)回功能練習(xí)官網(wǎng)：淘寶：群目錄com_prj 模塊3data_handle 模塊4my_fifo 模塊7uart_rx 模塊11uart_tx 模塊15明德?lián)P科技公司主要是以 FPGA 為，專(zhuān)業(yè)從事 FPGA 配套開(kāi)發(fā)板、FPGA加入明德?lián)P FPGA培訓(xùn)班或其他培訓(xùn)、研發(fā) FPGA 技術(shù)開(kāi)發(fā)、承接 FPGA 項(xiàng)目開(kāi)發(fā)。歡迎和 ASIC97925396。明德?lián)P以 PDF 格式提供源代碼，是為了鼓勵(lì)大家多思考，不要拿來(lái)就用，否則是學(xué)不好 FPGA 的。本代碼對(duì)應(yīng)的設(shè)計(jì)思路，請(qǐng)參考明德?lián)P課程。com_prj 模塊module com_prj(rst_n,clkr

2、x_uart, tx_uart,);parameterBPS= 5208;input input inputoutputrst_n;clk rx_uart;tx_uart;wire wire wire wirewire7:0uart_in;uart_in_vld ;7:0uart_out;uart_out_vld;rdy;/串口接收模塊uart_rx#(.BPS(BPS)uart_rx(.clk.rst_n.din.dout(clk (rst_n (rx_uart(uart_in),),),),.dout_vld(uart_in_vld);/串口發(fā)送模塊uart_tx#(.BPS(BPS)ua

3、rt_tx(.clk.rst_n.din(clk (rst_n(uart_out),),),.din_vld (uart_out_vld),.rdy(rdy),.dout(tx_uart);u_data_handle(.clk.rst_n.dindata_handle(clk(rst_n (uart_in),),),.din_vld (uart_in_vld ),.dout(uart_out),.dout_vld(uart_out_vld),.rdy);(rdy)endmoduledata_handle 模塊module data_handle(clkrst_n din,din_vld ,do

4、ut,dout_vld, rdy);parameterDATA_W =8;input inputinput DATA_W-1:0clk rst_ndin;inputdin_vld;input outputDATA_W-1:0outputrdydout;dout_vld;regregDATA_W-1:0doutdout_vld;reg reg reg wire wirewireDATA_W-1:0data ; rdreq; wrreq; empty; q ;usedw;DATA_W-1:06:0regrd_flag;regregrec_flag;DATA_W-1:0type;always(edg

5、e clk or negedge rst_n)beginif(rst_n=1b0)begin rec_flag = 1b0;endelse if(din_vld) begin rec_flag = rec_flag;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin type = 0;endelse if(din_vld & rec_flag=1b0) begin type = din;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin wrreq

6、 = 0;endelse if(rec_flag & din_vld & type=0) beginwrreq = 1b1;endelse beginwrreq = 1b0;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin data = 0;endelse begindata = din;endendmy_fifo u_my_fifo (.clock(clk),.data (data ),.rdreq(rdreq),.wrreq(wrreq),.empty(empty),.q(q),.usedw(usedw) );al

7、ways(*)beginif(rec_flag & din_vld & type=2 & empty=1b0) rdreq = 1b1;elserdreq = 1b0;endalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin dout = 0;endelse if(rec_flag & din_vld & type=1)begin dout = usedw;endelse begindout = q;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin dout

8、_vld = 1b0;endelse if(rec_flag & din_vld & type=1)begin dout_vld = 1b1;endelse begindout_vld = rdreq;endendendmodulemy_fifo 模塊/ megafunction wizard: %FIFO%/ GENERATION: STANDARD/ VER: WM1.0/ MODULE: scfifo/ =/ File Name: my_fifo.v/ Megafunction Name(s):/scfifo/ Simulation Library Files(s):/altera_mf

9、/ =/ */ THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!/ 11.0 Build 157 04/27/2011 SJ Full Ver/ */Copyright (C) 1991-2011 Altera Corporation/Your use of Altera Corporations design tools, logic functions/and other software and tools, and itsP partner logic/functions, and any output files from

10、 any of the foregoing/(including device programming or simulation files), and any/assotedation or information are expressly subject/to the terms and conditions of the Altera Program License/Subscription Agreement, Altera MegaCore Function License/Agreement, or other applicable license agreement, inc

11、luding,/without limiion,t your use is for the sole pure of/programming logic devimanufactured by Altera and sold by/Altera or its authorized distributors.Please refer to the/applicable agreement for further details./ synopsys translate_offtimescale 1 ps / 1 ps/ synopsys translate_on module my_fifo (

12、clock, data, rdreq, wrreq, empty, q,usedw);input input input input output outputoutputclock;7:0data; rdreq; wrreq; empty;7:0q;6:0usedw;wire 6:0 sub_wire0; wiresub_wire1; wire 7:0 sub_wire2;wire 6:0 usedw = sub_wire06:0; wireempty = sub_wire1;wire 7:0 q = sub_wire27:0;scfifoponent (.clock (clock),.da

13、ta (data),.rdreq (rdreq),.wrreq (wrreq),.usedw (sub_wire0),.empty (sub_wire1),.q (sub_wire2),.aclr (),.almost_empty (),.almost_full (),.full (),.sclr ();defparamponent.add_ram_output_register = OFF,ponent.ended_device_family = Cyclone IV E, ponent.lpm_numwords = 128, ponent.lpm_showahead = ON,ponent

14、.lpm_type = scfifo, ponent.lpm_width = 8,ponent.lpm_widthu = 7, ponent.overflow_checking = ON, ponent.underflow_checking = ON,ponent.use_eab = ON;endmodule/ =/ CNX file retrieval info/ =/ Retrieval info: PRIVATE: AlmostEmpty NUMERIC 0/ Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC -1/ Retrieval in

15、fo: PRIVATE: AlmostFull NUMERIC 0/ Retrieval info: PRIVATE: AlmostFullThr NUMERIC -1/ Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC 0/ Retrieval info: PRIVATE: Clock NUMERIC 0/ Retrieval info: PRIVATE: Depth NUMERIC 128/ Retrieval info: PRIVATE: Empty NUMERIC 1/ Retrieval info: PRIVATE: F

16、ull NUMERIC 0/ Retrieval info: PRIVATE:ENDED_DEVICE_FAMILY STRING Cyclone IV E/ Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC 0/ Retrieval info: PRIVATE: LegacyRREQ NUMERIC 0/ Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC 0/ Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC 0/ Retrieval info: PRI

17、VATE: Optimize NUMERIC 0/ Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC 0/ Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_TFIX STRING 0/ Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC 0/ Retrieval info: PRIVATE: UsedW NUMERIC 1/ Retrieval info: PRIVATE: Width NUMERIC 8/ Retrieval info: PRIVATE: d

18、c_aclr NUMERIC 0/ Retrieval info: PRIVATE: diff_widths NUMERIC 0/ Retrieval info: PRIVATE: msb_usedw NUMERIC 0/ Retrieval info: PRIVATE: output_width NUMERIC 8/ Retrieval info: PRIVATE: rsEmpty NUMERIC 1/ Retrieval info: PRIVATE: rsFull NUMERIC 0/ Retrieval info: PRIVATE: rsUsedW NUMERIC 0/ Retrieva

19、l info: PRIVATE: sc_aclr NUMERIC 0/ Retrieval info: PRIVATE: sc_sclr NUMERIC 0/ Retrieval info: PRIVATE: wsEmpty NUMERIC 0/ Retrieval info: PRIVATE: wsFull NUMERIC 1/ Retrieval info: PRIVATE: wsUsedW NUMERIC 0/ Retrieval info: LIBRARY: altera_mf altonents.all/ Retrieval info: CONSTANT: ADD_RAM_OUTPU

20、T_REGISTER STRING OFF/ Retrieval info: CONSTANT:ENDED_DEVICE_FAMILY STRING Cyclone IV E/ Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC 128/ Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ON/ Retrieval info: CONSTANT: LPM_TYPE STRING scfifo/ Retrieval info: CONSTANT: LPM_WIDTH NUMERIC 8/ Retrieval i

21、nfo: CONSTANT: LPM_WIDTUMERIC 7/ Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ON/ Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ON/ Retrieval info: CONSTANT: USE_EAB STRING ON/ Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock/ Retrieval info: USED_PORT: data 0 0 8 0 INPUT NO

22、DEFVAL data7.0/ Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty/ Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q7.0/ Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq/ Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw6.0/ Retrieval info: USED_PORT: wrre

23、q 0 0 0 0 INPUT NODEFVAL wrreq/ Retrieval info: CONNECT: clock 0 0 0 0 clock 0 0 0 0/ Retrieval info: CONNECT: data 0 0 8 0 data 0 0 8 0/ Retrieval info: CONNECT: rdreq 0 0 0 0 rdreq 0 0 0 0/ Retrieval info: CONNECT: wrreq 0 0 0 0 wrreq 0 0 0 0/ Retrieval info: CONNECT: empty 0 0 0 0 empty 0 0 0 0/

24、Retrieval info: CONNECT: q 0 0 8 0 q 0 0 8 0/ Retrieval info: CONNECT: usedw 0 0 7 0 usedw 0 0 7 0/ Retrieval info: GEN_FILE: TYPE_NORMAL my_fifo.v TRUE/ Retrieval info: GEN_FILE: TYPE_NORMAL my_fifo.inc FALSE/ Retrieval info: GEN_FILE: TYPE_NORMAL my_fifo.cmp FALSE/ Retrieval info: GEN_FILE: TYPE_N

25、ORMAL my_fifo.bsLSE/ Retrieval info: GEN_FILE: TYPE_NORMAL my_fifo_inst.v FALSE/ Retrieval info: GEN_FILE: TYPE_NORMAL my_fifo_bb.v FALSE/ Retrieval info: LIB_FILE: altera_mfuart_rx 模塊timescale 1ns / 1ps/*波特率設(shè)定明德?lián)P科教 注釋開(kāi)始*分頻計(jì)數(shù)值計(jì)算方法：(1/bps)/2*100000000-1;加大波特率不用改變計(jì)數(shù)器cnt 的位寬，減小波特率要記得改變計(jì)數(shù)器的位寬這里為了節(jié)省資源，計(jì)數(shù)

26、器的位寬只定義為使用 9600 波特的位寬*module uart_rx(明德?lián)P科教 注釋結(jié)束*/clk, rst_n, din, dout,dout_vld);parameter parameter parameter parameterparameterDATA_W = 8;NUM_W= 4;CNT_W= 14;BPS= 5208;BPS_P= BPS/2;input input inputoutputDATA_W-1:0outputclk rst_n din doutdout_vld;regregDATA_W-1:0doutdout_vld;regNUM_W-1 :0data_num;r

27、egDATA_W-1:0rx_temp_data ;reg reg reg reg wire reg wirewirerx0 rx1 rx2 rx3 rx_enbps_flag clk_bpsclk_bps_p;regCNT_W-1:0/*cnt;明德?lián)P科教 注釋開(kāi)始*下降沿檢測(cè):濾掉20ns-40ns 的毛刺(包脈沖和低脈沖毛刺)rx_en=1 表示數(shù)據(jù)線接收到下降沿,維持一個(gè)時(shí)鐘周期*always (明德?lián)P科教 注釋結(jié)束*/edge clk or negedge rst_n) beginif(!rst_n) beginrx0 = 1b1; rx1 = 1b1; rx2 = 1b1; rx3

28、 = 1b1;endelse beginrx0 = din; rx1 = rx0; rx2 = rx1; rx3 = rx2;endendassign rx_en = rx3 & rx2;/*明德?lián)P科教 注釋開(kāi)始*接收到 din 下降沿時(shí)啟動(dòng)串口準(zhǔn)備數(shù)據(jù)接收data_num 等于 10 時(shí)數(shù)據(jù)接收完畢，波特率啟動(dòng)信號(hào)*always (明德?lián)P科教 注釋結(jié)束*/edge clk or negedge rst_n)beginif(!rst_n) beginbps_flag = 1b0;endelse if(rx_en) begin bps_flag = 1b1;endelse if(data_num

29、=4d8&clk_bps) begin bps_flag = 1b0;endend/*明德?lián)P科教 注釋開(kāi)始*沒(méi)接到數(shù)據(jù)起始位，cnt 保持等于 0接收到起始位則 bps_flag 拉高，cnt 開(kāi)始計(jì)數(shù)，接收完則 bps_flag 拉低，計(jì)數(shù)停止cnt 計(jì)數(shù)到分頻計(jì)數(shù)值則清零重新計(jì)數(shù)*always (明德?lián)P科教 注釋結(jié)束*/edge clk or negedge rst_n)beginif(!rst_n)begincnt = 0;endelse if(bps_flag)begin if(clk_bps)begincnt = 0;endelse begincnt = cnt+1b1;endend

30、else begincnt = 0;endendassignassignclk_bps=(cnt = BPS-1);clk_bps_p=(cnt = BPS_P-1);/*明德?lián)P科教 注釋開(kāi)始*接收數(shù)據(jù)計(jì)數(shù)，1 個(gè)起始位，8bit 數(shù)據(jù)，1 個(gè)結(jié)束位*always (明德?lián)P科教 注釋結(jié)束*/edge clk or negedge rst_n)beginif(!rst_n) begindata_num = 4d0;endelse if(bps_flag)beginif(data_num= 4d8&clk_bps) begin data_num = 4d0;endelse if(clk_bps)

31、begindata_num = data_num+1b1;endendelse begindata_num = 0;endend/*明德?lián)P科教 注釋開(kāi)始*并保存數(shù)據(jù),接收數(shù)據(jù)為一個(gè)起始位，8bit 數(shù)據(jù)，1 個(gè)結(jié)束位*always (明德?lián)P科教 注釋結(jié)束*/edge clk or negedge rst_n)beginif(!rst_n) begindout = 8d0;endelse if(clk_bps_p&data_num!=0) begin dout=din,dout7:1;endelse begindout=dout;endend/*明德?lián)P科教 注釋開(kāi)始*接收到的數(shù)據(jù)輸出有效信號(hào)，只

32、保留一個(gè)時(shí)鐘周期*always (明德?lián)P科教 注釋結(jié)束*/edge clk or negedge rst_n)beginif(!rst_n) begindout_vld = 1b0;endelse if(data_num = 4d8&clk_bps) begin dout_vld = 1b1;endelse begindout_vld = 1b0;endendendmoduleuart_tx 模塊timescale 1ns / 1ps/*波特率設(shè)定明德?lián)P科教 注釋開(kāi)始*分頻計(jì)數(shù)值計(jì)算方法：(1/bps)/2*100000000-1;加大波特率不用改變計(jì)數(shù)器cnt 的位寬，減小波特率要記得改變計(jì)

33、數(shù)器的位寬這里為了節(jié)省資源，計(jì)數(shù)器的位寬只定義為使用 9600 波特的位寬*明德?lián)P科教注釋結(jié)束*/module uart_tx(clk, rst_n, din, din_vld, rdy,dout);parameter parameter parameter parameter parameterparameterDATA_W = 8;NUM_W= 4;CNT_W= 14;BPS WAITTX= 5208;= 1b0;= 1b1;inputinputclk;rst_n;inputDATA_W-1:0 din;inputoutput outputdin_vld;rdy; dout;regregrdy;dout;regDATA_W-1:0 regNUM_W-1 :0regCNT_W-1 :0reg regregtx_data_tmp; dat