vhdl課程設(shè)計-簡單處理器的設(shè)計與仿真

-PAGE33-前言 11、設(shè)計任務(wù) 22、設(shè)計說明 32.1處理器原理圖及其組成 32.2數(shù)據(jù)傳輸及加減法的實(shí)現(xiàn) 32.3處理器所支持的指令及功能說明、指令的編碼規(guī)則 42.4指令執(zhí)行的時序控制 43.處理器指令實(shí)現(xiàn)的功能及其具體描述 63.1mvRx,Ry 63.2mviRx,#D 73.3addRx,Ry和subRx,Ry 84單元模塊設(shè)計說明、VHDL代碼及其仿真 104.1寄存器RX 104.2寄存器A 114.3加/減法器addsub 124.4寄存器G 134.5指令寄存器IR 144.6計數(shù)器upcount 154.7復(fù)用器multi 164.8控制單元control 184.9控制指令輸入轉(zhuǎn)換模塊 264.1016*16點(diǎn)陣顯示控制模塊 275處理器各個模塊的連接及處理器功能仿真 295.1處理器各個模塊的連接 295.2處理器功能仿真 295.2.1立即數(shù)賦給寄存器R0 295.2.2立即數(shù)賦給寄存器R1 295.2.3寄存器R0的值賦給寄存器R2 295.2.4寄存器R1的值賦給寄存器R3 295.2.5立即數(shù)賦給寄存器R4 295.2.6寄存器R0加上R4賦給R0 305.2.7寄存器R1加上R4賦給R1 305.2.6寄存器R0加上R4賦給R0 305.2.7立即數(shù)賦給寄存器R5 305.2.8寄存器R4減去R5賦給R4 305.2.9寄存器R4減去R0賦給R4 306處理器實(shí)現(xiàn)的功能與操作說明 316.1處理器實(shí)現(xiàn)的功能 316.2處理器相關(guān)的操作說明 317課程設(shè)計總結(jié) 328附錄……………………...……34前言VHDL的英文全名是Very-High-SpeedIntegratedCircuitHardwareDescriptionLanguage，誕生于1982年。1987年底，VHDL被IEEE和美國國防部確認(rèn)為標(biāo)準(zhǔn)硬件描述語言。VHDL主要用于描述數(shù)字系統(tǒng)的結(jié)構(gòu)，行為，功能和接口。除了含有許多具有硬件特征的語句外，VHDL的語言形式和描述風(fēng)格與句法是十分類似于一般的計算機(jī)高級語言。VHDL的程序結(jié)構(gòu)特點(diǎn)是將一項工程設(shè)計，或稱設(shè)計實(shí)體（可以是一個元件，一個電路模塊或一個系統(tǒng)）分成外部（或稱可是部分,及端口)和內(nèi)部（或稱不可視部分），既涉及實(shí)體的內(nèi)部功能和算法完成部分。在對一個設(shè)計實(shí)體定義了外部界面后，一旦其內(nèi)部開發(fā)完成后，其他的設(shè)計就可以直接調(diào)用這個實(shí)體。這種將設(shè)計實(shí)體分成內(nèi)外部分的概念是VHDL系統(tǒng)設(shè)計的基本點(diǎn)。與其他硬件描述語言相比，VHDL具有以下特點(diǎn)：（1）功能強(qiáng)大、設(shè)計靈活VHDL具有功能強(qiáng)大的語言結(jié)構(gòu)，可以用簡潔明確的源代碼來描述復(fù)雜的邏輯控制。它具有多層次的設(shè)計描述功能，層層細(xì)化，最后可直接生成電路級描述。VHDL支持同步電路、異步電路和隨機(jī)電路的設(shè)計，這是其他硬件描述語言所不能比擬的。VHDL還支持各種設(shè)計方法，既支持自底向上的設(shè)計，又支持自頂向下的設(shè)計；既支持模塊化設(shè)計，又支持層次化設(shè)計。（2）支持廣泛、易于修改由于VHDL已經(jīng)成為IEEE標(biāo)準(zhǔn)所規(guī)范的硬件描述語言，目前大多數(shù)EDA工具幾乎都支持VHDL，這為VHDL的進(jìn)一步推廣和廣泛應(yīng)用奠定了基礎(chǔ)。在硬件電路設(shè)計過程中，主要的設(shè)計文件是用VHDL編寫的源代碼，因為VHDL易讀和結(jié)構(gòu)化，所以易于修改設(shè)計。（3）強(qiáng)大的系統(tǒng)硬件描述能力VHDL具有多層次的設(shè)計描述功能，既可以描述系統(tǒng)級電路，又可以描述門級電路。而描述既可以采用行為描述、寄存器傳輸描述或結(jié)構(gòu)描述，也可以采用三者混合的混合級描述。另外，VHDL支持慣性延遲和傳輸延遲，還可以準(zhǔn)確地建立硬件電路模型。VHDL支持預(yù)定義的和自定義的數(shù)據(jù)類型，給硬件描述帶來較大的自由度，使設(shè)計人員能夠方便地創(chuàng)建高層次的系統(tǒng)模型。（4）獨(dú)立于器件的設(shè)計、與工藝無關(guān)設(shè)計人員用VHDL進(jìn)行設(shè)計時，不需要首先考慮選擇完成設(shè)計的器件，就可以集中精力進(jìn)行設(shè)計的優(yōu)化。當(dāng)設(shè)計描述完成后，可以用多種不同的器件結(jié)構(gòu)來實(shí)現(xiàn)其功能。（5）很強(qiáng)的移植能力VHDL是一種標(biāo)準(zhǔn)化的硬件描述語言，同一個設(shè)計描述可以被不同的工具所支持，使得設(shè)計描述的移植成為可能。（6）易于共享和復(fù)用VHDL采用基于庫（Library）的設(shè)計方法，可以建立各種可再次利用的模塊。這些模塊可以預(yù)先設(shè)計或使用以前設(shè)計中的存檔模塊，將這些模塊存放到庫中，就可以在以后的設(shè)計中進(jìn)行復(fù)用，可以使設(shè)計成果在設(shè)計人員之間進(jìn)行交流和共享，減少硬件電路設(shè)計。1、設(shè)計任務(wù)用VHDL設(shè)計一個簡單的處理器，并完成相關(guān)的仿真測試。2、設(shè)計說明2.1處理器原理圖及其組成圖1是一個處理器的原理圖，它包含了一定數(shù)量的寄存器、一個復(fù)用器、一個加法/減法器（Addsub）,一個計數(shù)器和一個控制單元。圖1簡單處理器的電路圖2.2數(shù)據(jù)傳輸及加減法的實(shí)現(xiàn)數(shù)據(jù)傳輸實(shí)現(xiàn)過程：16位數(shù)據(jù)從DIN輸入到系統(tǒng)中，可以通過復(fù)用器分配給R0~R7和A，復(fù)用器也允許數(shù)據(jù)從一個寄存器傳通過Bus送到另外一個寄存器。加法和減法的實(shí)現(xiàn)過程：復(fù)用器先將一個數(shù)據(jù)通過總線放到寄存器A中，然后將另一個數(shù)據(jù)放到總線上，加法/減法器對這兩個數(shù)據(jù)進(jìn)行運(yùn)算，運(yùn)算結(jié)果存入寄存器G中，G中的數(shù)據(jù)又可根據(jù)要求通過復(fù)用器轉(zhuǎn)存到其他寄存器中。2.3處理器所支持的指令及功能說明、指令的編碼規(guī)則表1是該處理所支持的指令表1操作功能說明mvRx,RyRx←[Ry]將Ry寄存器的值復(fù)制到Rx寄存器mviRx,#DRx←Data將Data值存入Rx寄存器addRx,RyRx←[Rx]+[Ry]先將Rx和Ry寄存器的值相加，再把相加的值存入Rx寄存器subRx,RyRx←[Rx]-[Ry]先將Rx和Ry寄存器的值相減，再把相減的值存入Rx寄存器所有指令都按9位編碼（取自DIN的高9位）存儲在指令寄存器IR中，編碼規(guī)則為IIIXXXYYY，III表示指令，XXX表示Rx寄存器，YYY表示Ry寄存器。立即數(shù)#D是在mvi指令存儲到IR中之后，通過16位DIN輸入的。如表2所示表22.4指令執(zhí)行的時序控制有一些指令，如加法指令和減法指令，需要在總線上多次傳輸數(shù)據(jù)，因此需要多個時鐘周期才能完成。控制單元使用了一個兩位計數(shù)器來區(qū)分這些指令執(zhí)行的每一個階段。當(dāng)Run信號置位時，處理器開始執(zhí)行DIN輸入的指令。當(dāng)指令執(zhí)行結(jié)束后，Done信號置位，表3列出四個指令在執(zhí)行過程中每一個時間段置位的控制信號。圖2列出了處理器的狀態(tài)轉(zhuǎn)換圖表3：時間指令T0T1T2T3(mv):I0(mvi):I1(add):I2(sub):I3IRinIRinIRinIRinRYout,RXin,DoneDINout,RXin,DoneRXout,AinRXout,AinRYout,Gin,AddsubRYout,Gin,AddsubGout,RXin,DoneGout,RXin,Done““00”IRin“10”Add/sub“01”mv“11”Add/sub“01”Add/sub“01”mvi“10”Add/sub圖2，處理器狀態(tài)轉(zhuǎn)換圖3.處理器指令實(shí)現(xiàn)的功能及其具體描述3.1mvRx,Ry實(shí)現(xiàn)的功能：將寄存器Rx的值賦給寄存器Ry（以mvR0,R5為例）（1）計數(shù)器為“00”時,指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。置位的控制信號如圖3加粗黑線所示。圖3（2）計數(shù)器為“01”時,首先控制單元根據(jù)設(shè)計器為“00”時輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓R5的值輸出到總線上，然后控制單元控制寄存器R0將總線上的值鎖存，完成整個寄存器對寄存器的賦值過程。置位的控制信號和數(shù)據(jù)流如圖4加粗黑線所示。圖43.2mviRx,#D實(shí)現(xiàn)的功能：將的立即數(shù)#D賦給寄存器Rx（以mvR0,#D為例）（1）計數(shù)器為“00”時,指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。置位的控制信號如圖5加粗黑線所示。圖5（2）計數(shù)器為“01”時,首先控制單元根據(jù)設(shè)計器為“00”時輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓DIN的值輸出到總線上，然后控制單元控制寄存器R0將總線上的值鎖存，完成整個立即數(shù)對寄存器的賦值過程。置位的控制信號和數(shù)據(jù)流如圖6加粗黑線所示。圖63.3addRx,Ry和subRx,Ry實(shí)現(xiàn)的功能：將寄存器Ry的值加上/減去寄存器Rx的值并賦給寄存器Rx（以add/subR0,R1為例）。（1）計數(shù)器為“00”時,指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。置位的控制信號如圖7加粗黑線所示。圖7（2）計數(shù)器為“01”時,首先控制單元根據(jù)設(shè)計器為“00”時輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓R0的值輸出到總線上，然后控制單元控制寄存器A將總線上的值鎖存。置位的控制信號和數(shù)據(jù)流如圖8加粗黑線所示。圖8（3）計數(shù)器為“10”時,首先控制單元根據(jù)設(shè)計器為“00”時輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓R1的值輸出到總線上，然后控制單元控制加法/減法器addsub將寄存器A的值和總線上的值相加/相減并輸出，接著寄存器G將加法/減法器addsub的計算結(jié)果鎖存。置位的控制信號和數(shù)據(jù)流如圖9加粗黑線所示。圖9（4）計數(shù)器為“11”時,首先控制單元向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓寄存器G的值輸出到總線上，寄存器R0將總線上的值進(jìn)行鎖存，完成整個寄存器與對寄存器見加減法的運(yùn)算過程。置位的控制信號和數(shù)據(jù)流如圖10加粗黑線所示。圖104單元模塊設(shè)計說明、VHDL代碼及其仿真4.1寄存器RX寄存器R0~R7用于數(shù)據(jù)的存儲。當(dāng)時鐘輸入clock的上升沿到來且RXin=1時，將數(shù)據(jù)輸入端datain[15..0]的數(shù)據(jù)鎖存到寄存器中并從數(shù)據(jù)輸出端dataout[15..0]輸出；當(dāng)RXin=0時，輸出端保持原來的值不變。圖11寄存器RX的VHDL代碼：libraryieee;useieee.std_logic_1164.all;entityRXisport(RXin,clock:instd_logic;datain:instd_logic_vector(15downto0);dataout:outstd_logic_vector(15downto0));endRX;architecturebehaveofRXissignaldatabuffer:std_logic_vector(15downto0);beginprocess(clock,RXin,datain,databuffer)beginif(clock'eventandclock='1')thenif(RXin='1')thendatabuffer<=datain;elsedatabuffer<=databuffer;endif;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.2寄存器A寄存器A用于數(shù)據(jù)的存儲，當(dāng)時鐘輸入clock的上升沿到來且Ain=1時，將數(shù)據(jù)輸入端datain[15..0]的數(shù)據(jù)鎖存到寄存器中并從數(shù)據(jù)輸出端dataout[15..0]輸出；當(dāng)RXin=0時，輸出端保持原來的值不變。當(dāng)處理加減法時，將時間T1時總線送過來的數(shù)據(jù)暫存，當(dāng)T2時，將T1時存儲在A中的數(shù)據(jù)與總線傳輸過來的數(shù)據(jù)在Addsub中進(jìn)行加減運(yùn)算，并將結(jié)果并輸出到寄存器G中。圖12寄存器A的VHDL代碼：libraryieee;useieee.std_logic_1164.all;entityAisport(Ain,clock:instd_logic;datain:instd_logic_vector(15downto0);dataout:outstd_logic_vector(15downto0));endA;architecturebehaveofAissignaldatabuffer:std_logic_vector(15downto0);beginprocess(clock,Ain,datain,databuffer)beginif(clock'eventandclock='1')thenif(Ain='1')thendatabuffer<=datain;elsedatabuffer<=databuffer;endif;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.3加/減法器addsub加/減法器addsub用于處理兩個輸入的數(shù)據(jù)datain2[15..0]和datain1[15..0]，當(dāng)控制端Addsub=1時，兩個數(shù)據(jù)輸入端datain2[15..0]和datain1[15..0]相加并從數(shù)據(jù)輸出端dataout[15..0]輸出；當(dāng)控制端Addsub=0時，數(shù)據(jù)輸入端datain2[15..0]減去datain1[15..0]，結(jié)果從數(shù)據(jù)輸出端dataout[15..0]輸出。圖13加/減法器addsub的VHDL代碼：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityaddsubisport(Addsub:instd_logic;datain1:instd_logic_vector(15downto0);datain2:instd_logic_vector(15downto0);dataout:outstd_logic_vector(15downto0));endaddsub;architecturebehaveofaddsubissignaldatabuffer:std_logic_vector(15downto0);beginprocess(Addsub,datain1,datain2,databuffer)beginif(Addsub='1')thendatabuffer<=datain2+datain1;elsif(Addsub='0')thendatabuffer<=datain2-datain1;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.4寄存器G寄存器G用于加減運(yùn)算結(jié)果的存儲，當(dāng)時鐘輸入clock的上升沿到來且Gin=1時，將數(shù)據(jù)輸入端datain[15..0]的數(shù)據(jù)鎖存到寄存器中并從數(shù)據(jù)輸出端dataout[15..0]輸出；當(dāng)RXin=0時，輸出端保持原來的值不變。圖14寄存器G的VHDL代碼：libraryieee;useieee.std_logic_1164.all;entityGisport(Gin,clock:instd_logic;datain:instd_logic_vector(15downto0);dataout:outstd_logic_vector(15downto0));endG;architecturebehaveofGissignaldatabuffer:std_logic_vector(15downto0);beginprocess(clock,Gin,datain,databuffer)beginif(clock'eventandclock='1')thenif(Gin='1')thendatabuffer<=datain;elsedatabuffer<=databuffer;endif;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.5指令寄存器IR指令寄存器IR用于對輸入的16為指令進(jìn)行處理，取其高9位。當(dāng)時鐘輸入clock的上升沿到來且IRin=1時，取數(shù)據(jù)輸入端datain[15..0]的高9位將其鎖存到寄存器中并從數(shù)據(jù)輸出端dataout[8..0]輸出；當(dāng)RXin=0時，輸出端保持原來的值不變。圖15指令寄存器IR的VHDL代碼libraryieee;useieee.std_logic_1164.all;entityIRisport(IRin,clock:instd_logic;datain:instd_logic_vector(15downto0);dataout:outstd_logic_vector(8downto0));endIR;architecturebehaveofIRissignaldatabuffer:std_logic_vector(8downto0);beginprocess(clock,IRin,datain,databuffer)beginif(clock'eventandclock='1')thenif(IRin='1')thendatabuffer<=datain(15downto7);elsedatabuffer<=databuffer;endif;elsedatabuffer<=databuffer;endif;dataout<=databuffer;endprocess;endbehave;4.6計數(shù)器upcount計數(shù)器upcount用于產(chǎn)生控制單元的輸入脈沖，對控制單元的工作時序進(jìn)行控制。當(dāng)clear=0時（清零端clear無效），時鐘輸入clock每來一個上升沿，輸出Q[1..0]加1，所以輸出為00——>01——>10——>11——>00不斷循環(huán)；當(dāng)clear=1時（清零端clear有效），對輸出Q[1..0]異步清零，與時鐘無關(guān)。圖16計數(shù)器upcount的VHDL代碼libraryieee;useieee.std_logic_1164.all;useieee.std_logic_signed.all;entityupcountisport(clear,clock:instd_logic;Q:outstd_logic_vector(1downto0));endupcount;architectureBehaviorofupcountissignalcount:std_logic_vector(1downto0);beginprocess(Clock)beginif(clock'eventandclock='1')thenifclear='1'thenclear='1'cleariseffectivecount<="00";elsecount<=count+1;endif;endif;endprocess;Q<=count;endBehavior;4.7復(fù)用器multi復(fù)用器根據(jù)控制單元的控制信號將指定的輸入數(shù)據(jù)輸出到總線上。來自控制單元的控制信號為R0out~R7out、Gout、DINout，輸入數(shù)據(jù)位來自寄存器R0~R7、寄存器A、數(shù)據(jù)輸入端DIN，當(dāng)控制信號的某一位為1時，將其對應(yīng)的輸入數(shù)據(jù)輸出到總線上。圖17復(fù)用器multi的VHDL代碼libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitymultiisport(R0in:instd_logic_vector(15downto0);R1in:instd_logic_vector(15downto0);R2in:instd_logic_vector(15downto0);R3in:instd_logic_vector(15downto0);R4in:instd_logic_vector(15downto0);R5in:instd_logic_vector(15downto0);R6in:instd_logic_vector(15downto0);R7in:instd_logic_vector(15downto0);DIN:instd_logic_vector(15downto0);Gin:instd_logic_vector(15downto0);R0out:instd_logic;R1out:instd_logic;R2out:instd_logic;R3out:instd_logic;R4out:instd_logic;R5out:instd_logic;R6out:instd_logic;R7out:instd_logic;Gout:instd_logic;DINout:instd_logic;buswire:bufferstd_logic_vector(15downto0));endmulti;architecturebehaveofmultiissignalselect_signal:std_logic_vector(9downto0);signaldatabuffer:std_logic_vector(15downto0);beginselect_signal<=R7out&R6out&R5out&R4out&R3out&R2out&R1out&R0out&Gout&DINout;process(databuffer,R0in,R1in,R2in,R3in,R4in,R5in,R6in,R7in,DIN,Gin,R7out,R6out,R5out,R4out,R3out,R2out,R1out,R0out,Gout,DINout)begincaseselect_signaliswhen"0000000001"=>databuffer<=DIN;when"0000000010"=>databuffer<=Gin;when"0000000100"=>databuffer<=R0in;when"0000001000"=>databuffer<=R1in;when"0000010000"=>databuffer<=R2in;when"0000100000"=>databuffer<=R3in;when"0001000000"=>databuffer<=R4in;when"0010000000"=>databuffer<=R5in;when"0100000000"=>databuffer<=R6in;when"1000000000"=>databuffer<=R7in;whenothers=>null;endcase;buswire<=databuffer;endprocess;endbehave;4.8控制單元control控制單元根據(jù)計數(shù)器發(fā)出的脈沖和DIN輸入的操作指令對整個系統(tǒng)的其他模塊進(jìn)行控制，完成指定的操作。圖18控制單元control的VHDL代碼libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitycontrolisport(Run:instd_logic;Reset:instd_logic;DIN_IR_9:instd_logic_vector(8downto0);count:instd_logic_vector(1downto0);IRin:outstd_logic;Gout:outstd_logic;DINout:outstd_logic;R0in,R1in,R2in,R3in,R4in,R5in,R6in,R7in:outstd_logic;R0out,R1out,R2out,R3out,R4out,R5out,R6out,R7out:outstd_logic;Gin:outstd_logic;Ain:outstd_logic;Addsub:outstd_logic;Done:outstd_logic;clear:outstd_logic);endcontrol;architecturebehaveofcontrolis--typestateis(state0,state1,state2,state3);--signalcurrent_state,next_state:state;signalIR_buffer:std_logic_vector(8downto0);--signaltemp0:std_logic_vector(2downto0);beginprocess(Run,reset,count)beginIR_buffer<=DIN_IR_9;if(Run='1'andreset='0')thencasecountiswhen"00"=>IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';IRin<='1';state1when"01"=>tttttttttttttttttttttttttttttttttttttttttif(IR_buffer(8downto6)="000")thenmvRx,Rystate1IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';caseIR_buffer(2downto0)iswhen"000"=>R0out<='1';--test1_signal<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"001"=>R1out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"010"=>R2out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"011"=>R3out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"100"=>R4out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"101"=>R5out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"110"=>R6out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;when"111"=>R7out<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;whenothers=>null;endcase;Done<='1';clear<='1';tttttttttttttttttttttttttttttttttttttttttelsif(IR_buffer(8downto6)="001")thenmviRx,#Dstate1IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';DINout<='1';caseIR_buffer(5downto3)iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;Done<='1';clear<='1';========================================pppppppppppppppppppppppppppppppppppppppelsif(IR_buffer(8downto6)="010")thenaddRx,Rystate1IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';caseIR_buffer(5downto3)iswhen"000"=>R0out<='1';when"001"=>R1out<='1';when"010"=>R2out<='1';when"011"=>R3out<='1';when"100"=>R4out<='1';when"101"=>R5out<='1';when"110"=>R6out<='1';when"111"=>R7out<='1';whenothers=>null;endcase;Ain<='1';pppppppppppppppppppppppppppppppppppppppcccccccccccccccccccccccccccccccccccccccccelsif(IR_buffer(8downto6)="011")thensubRx,Rystate1IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';caseIR_buffer(5downto3)iswhen"000"=>R0out<='1';when"001"=>R1out<='1';when"010"=>R2out<='1';when"011"=>R3out<='1';when"100"=>R4out<='1';when"101"=>R5out<='1';when"110"=>R6out<='1';when"111"=>R7out<='1';whenothers=>null;endcase;Ain<='1';endif;cccccccccccccccccccccccccccccccccccccccccstate1state2state2state2when"10"=>if(IR_buffer(8downto6)="000")thenmvwithoutstate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';elsif(IR_buffer(8downto6)="001")thenmviwithoutstate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';elsif(IR_buffer(8downto6)="010")thenaddRx,Rystate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';case(IR_buffer(2downto0))iswhen"000"=>R0out<='1';when"001"=>R1out<='1';when"010"=>R2out<='1';when"011"=>R3out<='1';when"100"=>R4out<='1';when"101"=>R5out<='1';when"110"=>R6out<='1';when"111"=>R7out<='1';whenothers=>null;endcase;Addsub<='1';Gin<='1';elsif(IR_buffer(8downto6)="011")thensubRx,Rystate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';case(IR_buffer(2downto0))iswhen"000"=>R0out<='1';when"001"=>R1out<='1';when"010"=>R2out<='1';when"011"=>R3out<='1';when"100"=>R4out<='1';when"101"=>R5out<='1';when"110"=>R6out<='1';when"111"=>R7out<='1';whenothers=>null;endcase;Addsub<='0';Gin<='1';endif;state2state2state2state3state3state3state3when"11"=>if(IR_buffer(8downto6)="000")thenmvwithoutstate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';elsif(IR_buffer(8downto6)="001")thenmviwithoutstate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';elsif(IR_buffer(8downto6)="010"orIR_buffer(8downto6)="011")thenaddRx,Rystate2IRin<='0';Gout<='0';DINout<='0';R0in<='0';R1in<='0';R2in<='0';R3in<='0';R4in<='0';R5in<='0';R6in<='0';R7in<='0';R0out<='0';R1out<='0';R2out<='0';R3out<='0';R4out<='0';R5out<='0';R6out<='0';R7out<='0';Gin<='0';Ain<='0';Addsub<='0';Done<='0';clear<='0';Gout<='1';case(IR_buffer(5downto3))iswhen"000"=>R0in<='1';when"001"=>R1in<='1';when"010"=>R2in<='1';when"011"=>R3in<='1';when"100"=>R4in<='1';when"101"=>R5in<='1';when"110"=>R6in<='1';when"111"=>R7in<='1';whenothers=>null;endcase;Done<='1';endif;state3state3state3state3whenothers=>null;endcase;endif;endprocess;endbehave;4.9控制指令輸入轉(zhuǎn)換模塊由于試驗箱上只有12個撥動開關(guān)，而16位控制指令只有高9位有效，低7位只有在賦立即數(shù)時有用到。為了方便操作，將波動開關(guān)K1~K9接輸入控制指令DIN的高9位，波動開關(guān)K11和K12分別接Run和Reset的輸入?？刂浦噶頓IN的低7位全部用0填充。圖19控制指令輸入轉(zhuǎn)換模塊的VHDL代碼libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityin9_out16isport(operate_in_9:instd_logic_vector(8downto0);operate_out_16:outstd_logic_vector(15downto0));endin9_out16;architecturebehaveofin9_out16issignaltemp:std_logic_vector(15downto0);begintemp<=operate_in_9&'0'&'0'&'0'&'0'&'0'&'0'&'0';operate_out_16<=temp;endbehave;4.1016*16點(diǎn)陣顯示控制模塊將寄存器R0~R7的值顯示在16*16點(diǎn)陣上，具體顯示規(guī)則為：列對應(yīng)某個寄存器的值，從左到右為R0~R7，其中每兩列有效的顯示列間都間隔1列全部滅燈以方便觀察；行對應(yīng)特定寄存器的不同位，從上到下為寄存器的地位到高位RX（0）~RX(15)。圖2016*16點(diǎn)陣顯示控制模塊的VHDL代碼libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityled_matrixisport(clk:instd_logic;R0_in:instd_logic_vector(15downto0);R1_in:instd_logic_vector(15downto0);R2_in:instd_logic_vector(15downto0);R3_in:instd_logic_vector(15downto0);R4_in:instd_logic_vector(15downto0);R5_in:instd_logic_vector(15downto0);R6_in:instd_logic_vector(15downto0);R7_in:instd_logic_vector(15downto0);keyc:outstd_logic_vector(15downto0);--點(diǎn)陣列控制keyr:outstd_logic_vector(15downto0)--點(diǎn)陣行顯示);endled_matrix;architecturebehaveofled_matrixissignalcdount:std_logic_vector(3downto0);signaldount:std_logic_vector(8downto0);signalS:std_logic_vector(3downto0);beginprocess(clk)--顯示時序控制beginifclk'eventandclk='1'thenifcdount<15thencdount<=cdount+1;elsecdount<="0000";endif;endif;endprocess;process(cdount)begincasecdountiswhen"0000"=>keyc<="0000000000000001";when"0001"=>keyc<="0000000000000010";when"0010"=>keyc<="0000000000000100";when"0011"=>keyc<="0000000000001000";when"0100"=>keyc<="0000000000010000";when"0101"=>keyc<="0000000000100000";when"0110"=>keyc<="0000000001000000";when"0111"=>keyc<="0000000010000000";when"1000"=>keyc<="0000000100000000";when"1001"=>keyc<="0000001000000000";when"1010"=>keyc<="0000010000000000";when"1011"=>keyc<="0000100000000000";when"1100"=>keyc<="0001000000000000";when"1101"=>keyc<="0010000000000000";when"1110"=>keyc<="0100000000000000";when"1111"=>keyc<="1000000000000000";whenothers=>keyc<="0000000000000000";endcase;casecdountiswhen"0000"=>keyr<=R0_in;when"0001"=>keyr<="1111111111111111";when"0010"=>keyr<=R1_in;when"0011"=>keyr<="1111111111111111";when"0100"=>keyr<=R2_in;when"0101"=>keyr<="1111111111111111";when"0110"=>keyr<=R3_in;when"0111"=>keyr<="1111111111111111";when"