第四章靜態(tài)功耗優(yōu)化技術課件

第四章多電壓域設計技術

（Multi-VoltageDomain）第四章多電壓域設計技術

（Multi-VoltageDo14.1多電壓域設計

VLSI發(fā)展的一個重要趨勢是SOC工藝的進步使SOC成為可能；

設計復雜度的提高需要新的設計方法SOC中各部分性能要求不盡相同，可工作在不同電壓下，性能要求高的工作的高電壓域，反之。。。

同一部分根據(jù)其工作負荷也可工作在不同電壓4.1多電壓域設計2工作電壓可以有不同變化方式?StaticVoltageScaling(SVS):differentblocksorsubsystemsaregivendifferent,fixedsupplyvoltages.（最簡單的多電壓域設計）?Multi-levelVoltageScaling(MVS):anextensionofthestaticvoltagescalingcasewhereablockorsubsystemisswitchedbetweentwoormorevoltagelevels.Onlyafew,fixed,discretelevelsaresupportedfordifferentoperatingmodes.工作電壓可以有不同變化方式3?DynamicVoltageandFrequencyScaling(DVFS):anextensionofMVSwherealargernumberofvoltagelevelsaredynamicallyswitchedtofollowchangingworkloads. ?AdaptiveVoltageScaling(AVS):anextensionofDVFSwhereacontrolloopisusedtoadjustthevoltage.?DynamicVoltageandFreque4

就是最簡單的multi-voltage設計（SVS）也給設計增加了難度

?Levelshifters.Signalsthatgobetweenblocksthatusedifferentpowerrailsoftenrequirelevelshifters?CharacterizationandSTA.Withasinglesupplyfortheentirechip,timinganalysiscanbedoneatasingleperformancepoint.Thelibrariesarecharacterizedforthispoint,andthetoolsperformtheanalysisinastraight-forwardmanner.Withmultipleblocksrunningatdifferentvoltages,andwithlibrariesthatmaynotbecharacterizedattheexactvoltageweareusing,timinganalysisbecomesmuchmorecomplex就是最簡單的multi-voltage設計（SVS）也給5?Floorplanning,powerplanning,grids.Multiplepowerdomainsrequiremorecarefulanddetailedfloorplanning.Thepowergridsbecomemorecomplex.?Boardlevelissues.Multi-voltagedesignsrequireadditionalresourcesontheboard–additionalregulatorstoprovidetheadditionalsupplies.?Powerupandpowerdownsequencing.Theremaybearequiredsequenceforpoweringupthedesigninordertoavoiddeadlock.?Floorplanning,powerplanni6?高電壓電源推低電壓單元一般不會有問題但時序參數(shù)不準，因庫單元的時序參數(shù)是針對同電位的驅動和接收電路的，驅動端過驅動的時序最好專門單元4.2LevelShifter?高電壓電源推低電壓單元一般不會有問題4.2Level7?低推高時會出現(xiàn)P、N管同時導通，必須用LevelShifterSuch“up-shifting”levelconvertersrequiretwosupplyrails–andtypicallyshareacommonground.Thewellstructurescannotbejoinedtogetherbutmustbeassociatedwiththesuppliesindependently.?低推高時會出現(xiàn)P、N管同時導通，必須用LevelShi8?高推低時，LevelShifter使用低電壓，故一般放在低電壓域，因其使用低電壓4.3LevelShifterPlacement?高推低時，LevelShifter使用低電壓，故一般放在9?兩電壓域的模塊距離較遠時，可插入Buffer，BUFFER使用高電壓?兩電壓域的模塊距離較遠時，可插入Buffer，BUFFE10?低推高時，LevelShifter一般放在高電壓域，但因其使用高、低兩個電壓，低壓要象信號線一樣連出Sincetheoutputdriverrequiresmorecurrentthantheinputstage,weplacethelevelshifterinthe1.2Vdomain.placingthelevelshiftersinthedestinationdomain?低推高時，LevelShifter一般放在高電壓域，但因11?ClockSkew靜態(tài)時序分析：都要針對多電壓域進行4.4多電壓設計時的時序問題?ClockSkew4.4多電壓設計時的時序問題12第五章漏電流控制技術第五章漏電流控制技術13ThePowerCrisisfromIntelLeakagePoweriscatchingupwiththeactivepowerinnano-scaledCMOScircuits.ThePowerCrisisfromIntelLea14ThePowerCrisisfromIBMThePowerCrisisfromIBM15低壓設計的問題：漏電流為什么要低電壓設計？小尺寸器件的要求漏端熱載流子退化臨界電場Em<0.2MV/cm0.35um擊穿電壓6V左右一般要求工作電壓為擊穿電壓的1/3~1/2一般按恒定電場ScaleDown低功耗設計的要求5.1Low-VoltageLow-Threshold-VoltagecircuitDesign低壓設計的問題：漏電流5.1Low-VoltageLow16PNReverse-BiasCurrent(I1)WeakInversion(I2)（亞域電流）Gate-InducedDrainLeakage(I3)GateOxideTunneling(I4)5.2漏流主要來源PNReverse-BiasCurrent(I1)5.17PowerGatingStackedCMOSDual（Multi)ThresholdCMOS5.3LeakageControlTechniquesPowerGating5.3LeakageCont18一、PowerGating技術

1、Power-Gating與Clock-GatingClockGatingPowerGating一、PowerGating技術

1、Power-Gatin19Clock-Gating只關斷時鐘，節(jié)省動態(tài)功耗，靜態(tài)功耗不變。Power-Gating是關斷電源，動態(tài)、靜態(tài)功耗都不存在（還存在開關管的漏電）Clock-Gating只關斷時鐘，節(jié)省動態(tài)功耗，靜態(tài)功耗202、PowerGating的適用性、問題及解決的途徑概述powergatingismoreinvasivethanclock-gatinginthatitaffectsinter-blockinterfacecommunicationandaddssignificanttimedelaystosafelyenterandexitpowergatedmodes.Shuttingdownpowertoablockoflogicmaybescheduledexplicitlybycontrolsoftwareaspartofdevicedriversoroperatingsystemidletasks.Alternativelyitmaybeinitiatedinhardwarebytimersorsystemlevelpowermanagementcontrollers.2、PowerGating的適用性、問題及解決的途徑概述21Inanyevent,wearefacedwitharchitecturaltrade-offsbetween?theamountofleakagepowersavingsthatispossible?theentryandexittimepenaltiesincurred?theenergydissipatedenteringandleavingsuchleakagesavingmodes?theactivityprofile(proportionandfrequencyoftimesasleeporactive)Inanyevent,wearefacedwit22AcachedCPUsubsystemcantypicallybedormantorinactiveforlongperiods,makingpowergatingattractive.Buttherearesometrade-offsthatmustbeconsidered:?PowergatingtheentireCPUprovidesverygoodleakagepowerreduction.Butwake-up-timeresponsetoaninterrupthassignificantsystemleveldesignimplications.?IfthecachecontentsarelosteverytimetheCPUispowereddownthenthereislikelytobeasignificanttimeandenergycostinallthebusactivitytorefillthecachewhenitispoweredup.?Thenetenergysavingsdependonthesleep/wakeactivityprofileastohowmuchenergywassavedwhenpowergatedversustheenergyspentinreloadingstate.AcachedCPUsubsystemcantyp23AperipheralsubsystemmayhaveamuchbetterdefinedprofilethanaCPU.Buttherearestillsometrade-offs.Inparticular,itmaybenecessarytorestorestatequicklyonwake-uptomaximizepowersavings:?Thedevicedrivermayberequiredtoexplicitlyload/restorekeystateorinitiatehardwaresequencercontrolaspartofthesleep/wakeupsequence,butthisplacesasignificantburdenonsoftware.?Abetterapproachmaybefortheperipheraltostorekeystateinternallyduringsleepmode,butthisrequiresspecialcircuitryandadditionalcontrol.Aperipheralsubsystemmayhav24multi-processorCPUclusterwhereoneormoreprocessorsmaybepowergatedoffcompletely.Inthiscaseweassumethataprocessorispowereddownonlywhenithascompletedataskandisidle,waitingforanothertasktobeassigned:?PowergatingindividualCPUsprovidesverygoodleakagepowerreduction.?BecausetheCPUhascompleteditstask,thefactthatthelocalcachecontentsarelostwhenitispowergatedisnotaproblem.TheCPUisawokencleanandresetreadytoexecuteandcachethenexttaskitisgiven.?OptimizedenergysavingsmaywellrequireadaptiveshutdownalgorithmsthatvarythenumberofCPUcorespowergatedandactivewithvaryingworkload.multi-processorCPUclusterwh253、PowerGating的實現(xiàn)externallyswitchedpowersupply：長期閑置Internalpowergating：短期閑置3、PowerGating的實現(xiàn)externallysw26PowerGating的設計涉及到Thecriticalissuesinpowergatinginclude：switchingnetworkandthepowergatingcontroller.isolationcells.retentionflopsPowerGating的設計涉及到Thecritica27開關網(wǎng)絡的設計：

開關網(wǎng)絡的設計應避免多層次PowerGating（避免IRDrop增大）開關網(wǎng)絡的設計：

開關網(wǎng)絡的設計應避免多層次PowerGa28開關網(wǎng)絡可以是“header”switch；也可以是“footer”switch或Both（IRDrop大，代價大），一般用其一。大多用“header”

開關網(wǎng)絡可以是“header”switch；也可以是“fo29Withaheader-styleswitchfabric,theinternalnodesandoutputsofapowergatedblockcollapsedowntowardsthegroundrailwhentheswitchisturnedoff.Withafooter-styleswitchfabrictheinternalnodesandoutputsallchargetowardsthesupplyrailwhentheswitchisturnedoff.Notethathereisnoguaranteethatthepowergatednodeswilleverfullydischargetogroundorfullychargetothesupply.Instead,anequilibriumisreachedwhentheleakagecurrentthroughtheswitchesisbalancedbythesub-thresholdleakageoftheswitchedcells.ThisisoneofthereasonswhyisolationcellsarerequiredonoutputsofpowergatedblocksWithaheader-styleswitchfab30SwitchVddorVssratherthenbooth,inordertominimizetheIRdrop.Decideearlyoninthedesignphasewhetherheaderorfooterswitchesmostnaturallyfitwiththesystemdesign.Headerswitchesmaybethemostappropriatechoiceforswitchesifexternalpowergatingwillalsobeusedonthechip.Headerswitchesmaybethemostappropriatechoiceforswitchesifmultiplepowerrailsand/orvoltagescalingwillbeusedonthechip.（共地）第四章靜態(tài)功耗優(yōu)化技術課件31Akeyconcernincontrollingtheswitchingfabricistolimitthein-rushcurrentwhenpowertotheblockisswitchedon.Excessivein-rushcurrentcancausevoltagespikesonthesupply,possiblycorruptingregistersinthealways-onblocks,aswellasretentionregistersinthepowergatedblockOnerepresentativeapproachistodaisy-chainthecontrolsignaltotheswitches.Thecontrolsignalfromthepowercontrollerisconnectedtothefirstswitch,anditbuffers(withanappropriatedelay)thesignalandsendsitontothenextswitch.Turningontheswitchingfabricistouseseveralpower-upcontrolsignalsinsequence.Thefirstcontrolsignalmayturnonasetofweakor“trickle”switches,whichinitiatethepowerupbutlimitthein-rushcurrent.Thesecondcontrolsignalmaythenturnonthemainsetofpowerswitches.Akeyconcernincontrollingt32Theseswitcheshavemultipleenablepins;typically,thesmallerswitchisturnedonfirsttogetthevoltageupto95percent,thenthebiggerswitchisturnedontoreducetheIRdrop.Theseswitcheshavemultiplee33Power-Gating的粒度（粗粒度）Incoarsegrainpowergating,ablockofgateshasitspowerswitchedbyacollectionofswitchcells.Thesizingofacoarsegrainswitchnetworkismoredifficultthanafinegrainswitchastheexactswitchingactivityofthelogicitsuppliesisnotknownandcanonlybeestimated.Butcoarsegraingatingdesignshavesignificantlylessareapenaltythanfinegrain.多數(shù)應用：粗粒度Power-Gating的粒度（粗粒度）34Power-Gating的粒度（細粒度）Infinegrainpowergatingtheswitchisplacedlocallyinsideeachstandardcell.Sincethisswitchmustsupplytheworstcasecurrentrequiredbythecell,ithastobequitelargeinordernottoimpactperformance.Theareaoverheadofeachcellissignificant(often2x-4xthesizeoftheoriginalcell).ThekeyadvantageoffinegrainpowergatingisthatthetimingimpactoftheIRdropacrosstheswitchandthebehavioroftheclampareeasytocharacterizeastheyarecontainedwithinthecell.ThismeansthatitisstillpossibletouseatraditionaldesignflowtodeployfinegrainpowergatingPower-Gating的粒度（細粒度）35IsolationCell的設計模塊被PowerDown后輸出浮空，電平未知，被其驅動的負載可能處于P、N管都通的情況需加信號隔離，輸出固定值隔離單元輸出一般為被驅動的無效態(tài)IsolationCell的設計模塊被PowerDow36增加隔離單元增加了延遲選用上下拉做隔離可消除延遲但隔離信號處于多源驅動，Power-gatingcontroler設計時必須注意，避免出現(xiàn)多源競爭增加隔離單元增加了延遲37用OR還是AND要看被驅動電路輸入是高有效還是低有效。若某輸入為低時發(fā)出中斷，在需用OR將其啟動為高因驅動負載可能是多個，故信號隔離單元一般亦放在驅動端用OR還是AND要看被驅動電路輸入是高有效還是低有效。若某輸38SignalIsolation應滿足一定時序要求SignalIsolation應滿足一定時序要求39

StateRetention設計Givenapowerswitchingfabricandanisolationstrategy,itispossibletopowergateablockoflogic.Butunlessaretentionstrategyisemployed,allstateinformationislostwhentheblockispowereddown.Toresumeitsoperationonpowerup,theblockmusteitherhaveitsstaterestoredfromanexternalsourceorbuildupitsstatefromtheresetcondition.Ineithercase,thetimeandpowerrequiredcanbesignificant.StateRetention設計Givenapow40Retentionregisterstypicallyhaveanauxiliaryorshadowregisterthatisslowerthanthemainregisterbutwhichhasmuchlessleakagecurrent.Theshadowregisterisalwayspoweredup,andstoresthecontentsofthemainregisterduringpowergatingTheseretentionregistersneedtobetoldwhentostorethecurrentcontentsofthemainregisterintotheshadowregisterandwhentorestorethevaluebacktothemainregister.Thiscontrolisprovidedbythepowergatingcontroller.Retentionregisterstypically41

StateRetentionandRestorationMethodsAsoftwareapproachbasedonreadingandwritingregistersAscan-basedapproachbasedonusingscanchainstostorestateoffchipAregister-basedapproachthatusesretentionregistersStateRetentionandRestorati42

StateRetention時序SRPG不能斷電（VRET）SRPG速度可以慢，漏流要小StateRetention時序SRPG不能斷電（VR43實現(xiàn)Power-Gating應解決如下問題?Designofthepowerswitchingfabric?Designofthepowergatingcontroller?Selectionanduseofretentionregistersandisolationcells?Minimizingtheimpactofpowergatingontimingandarea.?Thefunctionalcontrolofclocksandresets?Interfaceisolation實現(xiàn)Power-Gating應解決如下問題44實現(xiàn)Power-Gating應解決如下問題?Developingthecorrectconstraintsforimplementationandanalysis?Performingstate-dependentverificationforeachsupportedpowerstate?Performingpowerstatetransitionverificationtoensurealllegalstateentryandexitarcsaresimulatedandverified?Developingastrategyformanufacturingandproductiontest實現(xiàn)Power-Gating應解決如下問題45一個完整的PowerGating的設計switchingnetworkisolationcellsretentionflopspowergatingcontrollerLevelShifter（看是否是多電壓域）一個完整的PowerGating的設計switching46

PowerCycleSequenceForpower-down,aspecificsequenceisgenerallyfollowed:isolation,stateretention,powershut-off(見下圖).Forthepower-upcycle,theoppositesequenceneedstobefollowed.Thepower-upcyclecanalsorequireaspecificresetsequence.PowerCycleSequenceForpower474、CadenceLow-PowerFlowersCPF（CommonPowerFormat）是Cadence提出，SiliconIntegrationInitiative通過的標準CPF-basedflow中RTL不需修改;TheRTLcanbeinstantiatednnumberoftimes,andeachinstancewillhaveadifferentlow-powerbehaviorasspecifiedbythecorrespondingCPF.4、CadenceLow-PowerFlowersCP48

如何利用CPF描述電源管理方案設計還是按原來的方法進行，電源管理方案由CPF描述圖中pdA，pdB可以Power-Down，其他部分省缺屬于pdTop電壓域及Power-Down條件描述#Definethetopdomainset_designTOP#Definethedefaultdomaincreate_power_domain\–namepdTop–default#DefinePDAcreate_power_domain\–namepdA\–instances{uAuC}\–shutoff_condition{!uPCM/pso[0]}#DefinePDB–PSOwhenpsoislowcreate_power_domain–namepdB\–instances{uB}\–shutoff_condition{!uPCM/pso[1]}如何利用CPF描述電源管理方案設計還是按原來的方法進行，電49

隔離和stateretention描述#ActivehighIsolationsethiPin{uB/en1uB/en2}create_isolation_rule\–nameir1\–frompdB\–isolation_condition{uPCM/iso}\–isolation_outputhigh\–pins$hiPin#DefineState-Retention(SRPG)setsrpgList{uB/reg1uB/reg2}create_state_retention_rule\–namesr1\–restore_edge{uPCM/restore[0]}\-instances$srpgList隔離和stateretention描述50

Level-Shifter描述#DefineLevel-Shiftersinthe#“to”domaincreate_level_shifter_rule–namelsr1\–to{pdB}–from{pdA}create_level_shifter_rule–namelsr2\–to{pdA}–from{pdB}create_level_shifter_rule–namelsr3\–to{pdTop}–from{pdB}create_level_shifter_rule–namelsr4\–to{pdA}–from{pdTop}Level-Shifter描述51CPF支持VLSI設計全流程用RTL完成功能設計用CPF完成PowerIntent描述CPF語法，RTL與CPF的相容性，CPF的完整性等低功耗模式下的驗證。如：模塊電源關閉、重啟，保持寄存器等含CPF進行邏輯綜合，對DVFS需多約束文件。isolationandstateretention的插入使等價性檢查更復雜減小測試功耗isolation、stateretention、Level-Shifer等單元的測試powerswitchinsertionPowerdomain–awareplacementandoptimization等等CPF支持VLSI設計全流程用RTL完成功能設計CPF語法，52Power-down模擬下的邏輯模擬Power-down模擬下的邏輯模擬53邏輯綜合左上窗口未含CPF?Isolationcellstoalloutputsofpowerdomains?Isolationcellstoinputswherespecified?Levelshifterstosignalscrossingvoltagedomains?Replacementofallflopswithretentionflopswherespecified邏輯綜合?Isolationcellstoallo54TestForLow-PowerTestForLow-Power55TestForLow-PowerTestForLow-Power56

VT=√2εε0qNA(2ψB+VBS)/Ci+2ψB+φms－Qf/Ci

.二、晶體管堆疊技術VT=√2εε0qNA(2ψB+VBS)57襯底電壓Vbb是如何影響Vth的？N管P形襯底加負電壓時Vth升高、加正偏壓時Vth降低P管N形襯底加正電壓時Vth升高、加負偏壓時Vth降低襯底電壓Vbb是如何影響Vth的？58Vs>0時VG＝0相當于VGS＝－VsVs>0時VG＝0相當于VGS＝－Vs59第四章靜態(tài)功耗優(yōu)化技術課件60第四章靜態(tài)功耗優(yōu)化技術課件61第四章靜態(tài)功耗優(yōu)化技術課件62第四章靜態(tài)功耗優(yōu)化技術課件63第四章靜態(tài)功耗優(yōu)化技術課件64第四章靜態(tài)功耗優(yōu)化技術課件65第四章靜態(tài)功耗優(yōu)化技術課件66第四章靜態(tài)功耗優(yōu)化技術課件67第四章靜態(tài)功耗優(yōu)化技術課件68結論串聯(lián)堆疊管越多漏流越小不通的管子位置越低（靠近地）漏流越小插入高Vth管對降低漏流大有好處原因ZLa(kT)22q2

ni

NA21-exp(-qVD/kT)exp(qψS/kT)(qψS/kT)1/2μn

Ci結論ZLa(kT)22q2niNA21-exp69第四章靜態(tài)功耗優(yōu)化技術課件70第四章靜態(tài)功耗優(yōu)化技術課件71第四章靜態(tài)功耗優(yōu)化技術課件72第四章靜態(tài)功耗優(yōu)化技術課件73第四章靜態(tài)功耗優(yōu)化技術課件74第四章靜態(tài)功耗優(yōu)化技術課件75第四章靜態(tài)功耗優(yōu)化技術課件76三、雙域值晶體管電路三、雙域值晶體管電路77第四章靜態(tài)功耗優(yōu)化技術課件78NodesincriticalpathNodeswithlowVthNodeswithhighVthabcdNodesi