12February1999

1、This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentationIn Slide Show, click on the right mouse buttonSelect “Meeting Minder”Select the “Action Items” tabType in action items as they come

2、upClick OK to dismiss this boxThis will automatically create an Action Item slide at the end of your presentation with your points entered.Levan BabukhadiaD Collaboration Meeting, October 11 - 13, 2000, FermilabStatus of the L1 TriggerSUNY at Stony BrookCTPT/FPS ComponentsAnalog (Fermilab - D)AFE-8M

3、CM (primarily CFTax): 10 here, ready by 11/01, 54 more by 12/15, balance 01/30/01Crates/Cables on hand, installed when requiredPower supplies delayed until new year (partial).Mixer ( Fermilab - CD )Super-sector (1/5th) mid-NovemberFull Mixer 1/01Digital ( Fermilab - D )All MBs here and in testingTra

4、nsition boards expecting in 2 weeksCTPT DBs (single-wide, 5 Virtex 2.5v FPGAs) by mid-November FPS DBs (double-wide, 3 Virtex 2.5v FPGAs) partial order outXilinx/Virtex FPGAs for CTOT on order, others held until further decision, Virtex vs. Virtex-ECrates/Cables/PS all here by mid-NovemberCTTP/FPS F

5、irmware: CFT/CPS AxialDFEA (80) : Jamieson Olsen (Kin is gone)Both L1/L2 firmware in good shape4 FPGAs find tracks in 4 Pt and report to 5-th FPGA and to MuonBackend (5-th) FPGA does CPS cluster finding and track matchingfirmware has to be re-written, concerns on the chip sizeexpect functional and t

6、ested firmware in a couple of monthsCTOC (8) : Juan Lizarazo, now Ricardo Rodrigez Both L1/L2 firmware completed and tested in testbenchMinor issues and additions will be addressed by Ricardo/ManuelCTQD (4) : Pavel Polozov now goneL2CFT part completed functionally with some minor issueNeeds implemen

7、tation, L2CPS, and all of this tested in the hardwareCTTT (1) : Jerry BlazeyAlgorithm/VHDL/Functional/Implementation at 20%2 out of 64 Trigger Terms done through the implementation phaseL1-L3 sender, finish all VHDL, implementation, hardware test standCTTP/FPS Firmware: CPS StereoDFES (5) : Qichun X

8、u, MSUNo link to L1 TM, straight to L2 and L3, thus has time!Main issue is cluster finding in the large number (500) of CPS stereo strips in a sector but having time may save the day.New MSU student Qichun Xu, just startedMade a good head-start with an overall algorithms and the cluster finding algo

9、rithms in particular Start writing VHDL, expect functional code in about 1-2 monthsCPSS (2) : ?!Nobody yet! Perhaps Qichun will take on this one as well .CTTP/FPS Firmware: FPSDFEF (32) : Levan BabukhadiaChallenge: cluster finding in 144 FPS strips at the L1 rateL1 U/V algo developed, coded, and imp

10、lemented; test stand is nextL1U and L1V each takes Xilinx/Virtex 400 FPGA (75%, 63 MHz)Develop L2 priority reporting algo to take care of truncation. It is aimed at the 3rd FPGATransferring clusters within a DB or find clusters anew?.FPSS (4) : Mrinmoy BhattacharjeeL1 algo developed, coded, and impl

11、emented w/o the L3 senderfits in one Xilinx/Virtex 400 FPGA (30%, 66 MHz)Develop L2 algorithmFPTT (1) : Satish DesaiL1 algo developed, coded, and implemented w/o the L3 senderfits in one Xilinx/Virtex 400 FPGA (20%, 64 MHz)Complete all L1 functionally, test stand by the end of OctoberCTPT/FPS Instal

12、lation/CommissioningAssembling test stands for digital/VHDL testingHardware: 2 PCs, MBs, 2 Data Pump Boards, PS, cables, CTPT/FPS DBs1 fully stuffed double-wide DB10 fully stuffed single-wide DBsPersonnel: Jamieson Olsen, Brian Connolly (very short time), Ricardo Rodrigez, and a new part-time techHa

13、d 1 working test stand but recently moved to DAB3/NE; will be made operational this week Aiming at having 2 “single board” bench-tops and 1 “multi-board” test stand (for a one sparse system test - available now, Jamieson)Installing cables/crates on platformCrates/Cables installed in MCHComponentsSci

14、ntillator (48) completeCAF boards (175) on handCompleting ADC (12) board layout, ordering partsVertex board, FPGA 75% complete, layout commencingProcuring signal cables (60) soonCrate/PS on handInstallation/CommissioningInstalled scintillator (4/00) Cabling awaits FPS, commissioning thereafter Softw

15、are/FirmwareWorking on embedded softwareDownload currently underwayDatabase under developmentSchedule (on time)Electronics installed, February 1; Lum Monitoring March 1And/Or terms, March-AprilLuminosity Monitor StatusTiming signal generation and distributionSome work has been done and some tests ha

16、ve been madeInitial implementation will probably cover just the CC racksL2/L3 readout complete (by November)Uses much of the same equipment as the readout from the TFAll circuit boards exist and initial designs of all the FPGAs existAnalog input circuit (pick-off) boards (320) Prototypes of this exi

17、st and some testing has been done1FTE month to productionQuadrant Terms Circuit board (40) and FPGA design work has been startedNo prototypes exist yetWill not be pushed in the immediate futureSchedule (late but well before 3/01)Inactive until TF complete 11/00. Resume within a monthStart with analo

18、g pick-offsL1 Calorimeter Trigger Status L1MU Hardware (4 crates, prod beginning UAz)Crate Manager (MTCM)Production card testing in progressMotherboard (MTCxx - Trigger Card) Production cards beginning fabricationFlavor Boards Production Trigger Manager (MTM) boards ready for fabricationProduction w

19、ire DB (MTC10) design in progress (finish in 2 weeks) Preproduction scintillator DB (MTC05) in fabricationSLDBs (Gbit/s Serial Links)Production board testing in progress Software/FirmwareDownload infrastructure in placePreproduction versions of all firmware existNo alarms, monitoringL1 Muon Trigger

20、Status MCEN Hardware (5 crates, in preprod testing BU)Crate Manager (MCCM)Preproduction card layout in progressCentroid Finder Cards (MCEN) Preproduction card testing in progressPhysics Boards (MCPB)Preproduction board testing in progress InfrastructureCustom VME backplanes completedPower suppliesPr

21、ototype assembled and testedVICOR supplies ordered but with 20-22 week lead timePlatform Services - on hold pending final cable plant designCabling (1,600)Production at Fermilab and NIU in progressL1 Muon Trigger Status Near Term Commissioning GoalsMid-AugustStable operation of one (sparse) L1MU trigger crate and the L1MU MTM cratestill using preproduction cardsEarly OctoberAdd L1CTPT MTM crate to the aboveMid-OctoberBegin commissioning production of L1MU crates and cards Longer Term Commissioning GoalsBegin full crate testing in late Dec