超大規(guī)模集成電路第四次作業(yè)

1、精選優(yōu)質(zhì)文檔-傾情為你奉上精選優(yōu)質(zhì)文檔-傾情為你奉上專心-專注-專業(yè)專心-專注-專業(yè)精選優(yōu)質(zhì)文檔-傾情為你奉上專心-專注-專業(yè)Shown below are buffer-chain designs. Calculate the minimum delay of a chain of inverters for the overall effective fan-out of 64/1. Solution：由題可知：根據(jù)經(jīng)驗為最合適的值，所以，所以，但是級數(shù)必須為整數(shù)所以取，又因為，所以：，所以。(2) Using HSPICE and TSMC 0.18 um CMOS technology

2、 model with 1.8 V power supply, design a circuit simulation scheme to verify them with their correspondent parameters of N, f, and tp.Solution:根據(jù)（1）中計算知道三級最合適，所以驗證如下：A）、一級無負載測本征延時代碼如下：.title buffer-chain 1.lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.opt scale=0.1u * set

3、lambda.options post=2 list.temp 27.global vdd Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0 1.8 25n 5p 5p 49.99n 100n $頻率為10MhzCl vout gnd 0f $Cg1=2.46fF，負載為CL=157.44fF.subckt inv in out wn=3.5 wp=10 t=7.5mn out in gnd gnd NCH l=2 w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=2 w=wp ad=wp*t

4、 pd=wp+2*t as=wp*t ps=wp+2*t.endsX1 vin vout inv wn=3.5 wp=10 t=7.5.op.tran 5p 5n.meas tran voutmax max v(vout) from=5p to=5n.meas tran voutmin min v(vout) from=5p to=5n$一級.meas tran tphl1+trig v(vin) +val=0.9 +rise=1+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +fall=1.meas tran tplh1 +trig v(vi

5、n) +val=0.9 +fall=1+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +rise=1.end1）一級無負載測得本征延時約為17ps；2）帶上64倍Cg1大小的負載測得延時為750.35ps，是本征延時的44倍B）、三級帶負載測延時代碼如下：.title buffer-chain 3.lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.opt scale=0.1u * set lambda.options post=2 list.temp

6、 27.global vdd .param fan=4Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0 1.8 25n 5p 5p 49.99n 100nCl vout gnd 0f $Cg1=2.46fF，負載為CL=157.44fF.subckt inv in out wn=3.5 wp=10 t=7.5mn out in gnd gnd NCH l=2 w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=2 w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.

7、endsX1 vin 2 inv wn=3.5 wp=10 t=7.5X2 2 3 inv wn=fan*3.5 wp=fan*10 t=5X3 3 vout inv wn=fan*fan*3.5 wp=fan*fan*10 t=5.op.tran 50p 500n.meas tran voutmax max v(vout) from=50p to=500n.meas tran voutmin min v(vout) from=50p to=500n$三級.meas tran tphl3 +trig v(vin) +val=0.9 +rise=1+targ v(vout) +val=0.5*(

8、voutmax-voutmin)+voutmin +fall=1.meas tran tplh3 +trig v(vin) +val=0.9 +fall=1+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +rise=1帶上64倍Cg1大小的負載測得延時為174.6ps，是本征延時的10.27倍總結(jié)如下：經(jīng)過調(diào)整參數(shù)近似時每一級的，所以經(jīng)過手工計算得到一級帶負載和三級帶負載的延時比值為：，而仿真得到的結(jié)果為，所以符合手工計算的比值，同理其他級的延時代碼也是如上的寫法，經(jīng)過仿真得到三級延時最小。.endConsider the logic netw

9、ork below, which may represent the critical path of a more complex logic block. The output of the network is loaded with a capacitance which is 5 times larger than the input capacitance of the first gate, which is a minimum-sized inverter. The effective fanout of the path hence equals F = CL/Cg1 = 5

10、. Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, design a circuit simulation scheme to verify the OPTIMAZATION parameters of g, f, and s for each of the inverter and gates.Solution:由題得到路徑邏輯努力，由于沒有分支B=1，所以，所以使延時最小的邏輯努力為，得到如下的扇出系數(shù)：，利用書上公式6.18計算得到尺寸系數(shù)。電路仿真代碼如下：.title INV 2

11、NAND 2NOR .lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.options post=2 list.temp 27.global vdd Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0.0 1.8 150p 5p 5p 290p 600pC1 vout gnd 12.3f $Cg1=2.46fF，所以負載為12.3fF.subckt inv1 in out wn=0.35u wp=1u t=0.75umn out in gnd gnd NCH l=0.2u w=

12、wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.ends.subckt nand3 NAND-A1 NAND-D1 NAND-B1 NAND-C1 wn=0.35u*1.16 wp=1u*1.16t=0.5u $優(yōu)化尺寸系數(shù)S2*.subckt nand3 NAND-A1 NAND-D1 NAND-B1 NAND-C1 wn=0.35u wp=1u t=0.5u $未優(yōu)化尺寸系數(shù)S2mn3 NAND-S2 NAND-C1 gnd

13、 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmn2 NAND-S1 NAND-B1 NAND-S2 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmn1 NAND-D1 NAND-A1 NAND-S1 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp1 NAND-D1 NAND-A1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*

14、tmp2 NAND-D1 NAND-B1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*tmp3 NAND-D1 NAND-C1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.ends.subckt nor2 NOR-A1 NOR-D1 NOR-B1 wn=0.35u*1.34 wp=1u*1.34 t=0.5u $優(yōu)化尺寸系數(shù)S3*.subckt nor2 NOR-A1 NOR-D1 NOR-B1 wn=0.35u wp=1u t=0.5u $未優(yōu)化

15、尺寸系數(shù)S3mn2 NOR-D1 NOR-B1 gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmn1 NOR-D1 NOR-A1 gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp1 NOR-S1 NOR-A1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*tmp2 NOR-D1 NOR-B1 NOR-S1 vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t

16、as=wp*t ps=wp+2*t.ends.subckt inv2 in out wn=0.35u*2.6 wp=1u*2.6 t=0.5u $優(yōu)化尺寸系數(shù)S4*.subckt inv2 in out wn=0.35u wp=1u t=0.5u $未優(yōu)化尺寸系數(shù)S4 mn out in gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.endsX1 vin 2 inv1X2 2 3 vd

17、d vdd nand3X3 3 4 gnd nor2X4 4 vout inv2 .op.tran 5p 3000p.meas tran voutmax max v(vout) from=5p to=3000p.meas tran voutmin min v(vout) from=5p to=3000p.meas tran tphl+trig v(vin) +val=0.9 +rise=2+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +rise=2.meas tran tplh+trig v(vin) +val=0.9 +fall=2+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +fall=2.end$Cg1=2.46fF，所以負載為12.3fF仿真結(jié)果如