靜態(tài)時序分析基本原理和時序分析模型課件

1、Quartus II Software Design Series: Timing Analysis- Timing analysis basics2ObjectivesDisplay a complete understanding of timing analysis3How does timing verification work?Every device path in design must be analyzed with respect to timing specifications/requirementsCatch timing-related errors faster

2、 and easier than gate-level simulation & board testingDesigner must enter timing requirements & exceptionsUsed to guide fitter during placement & routingUsed to compare against actual results INCLKOUTDQCLRPREDQCLRPREcombinational delaysCLR4Timing Analysis BasicsLaunch vs. latch edgesSetup & hold tim

3、esData & clock arrival timeData required timeSetup & hold slack analysisI/O analysisRecovery & removalTiming models5Path & Analysis TypesThree types of Paths:Clock PathsData PathAsynchronous Paths*Clock PathsAsync PathData PathAsync PathDQCLRPREDQCLRPRETwo types of Analysis:Synchronous clock & data

4、pathsAsynchronous* clock & async paths*Asynchronous refers to signals feeding the asynchronous control ports of the registers6Launch & Latch EdgesCLKLaunch EdgeLatch EdgeData ValidDATALaunch Edge:the edge which “l(fā)aunches” the data from source registerLatch Edge:the edge which “l(fā)atches” the data at d

5、estination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle)7Setup & HoldSetup:The minimum time data signal must be stableBEFORE clock edgeHold:The minimum time data signal must be stableAFTER clock edgeDQCLRPRECLKThValidDATATsuCLKDATATogether, the setup time

6、 and hold time form a Data Required Window, the time around a clock edge in which data must be stable.8Data Arrival TimeData Arrival Time = launch edge + Tclk1 + Tco +TdataCLKREG1.CLKTclk1Data ValidREG2.DTdataLaunch EdgeData ValidREG1.QTcoThe time for data to arrive at destination registers D inputR

7、EG1PRED QCLRREG2PRED QCLRComb.LogicTclk1TCOTdata9Clock Arrival TimeClock Arrival Time = latch edge + Tclk2 CLKREG2.CLKTclk2Latch EdgeThe time for clock to arrive at destination registers clock inputREG1PRED QCLRREG2PRED QCLRComb.LogicTclk210Data Required Time - SetupData Required Time = Clock Arriva

8、l Time - Tsu - Setup Uncertainty CLKREG2.CLKTclk2Latch EdgeThe minimum time required for the data to get latched into the destination registerTsuData ValidREG2.DData must be valid hereREG1PRED QCLRREG2PRED QCLRComb.LogicTclk2Tsu11Data Required Time - HoldData Required Time = Clock Arrival Time + Th

9、+ Hold Uncertainty CLKREG2.CLKTclk2Latch EdgeThe minimum time required for the data to get latched into the destination registerThData mustremain validto hereData ValidREG2.DREG1PRED QCLRREG2PRED QCLRComb.LogicTclk2Th12Tclk2Setup SlackREG2.CLKThe margin by which the setup timing requirement is met.

10、It ensures launched data arrives in time to meet the latching requirement.TsuCLKREG1.CLKTclk1Data ValidREG2.DTdataData ValidREG1.QTco Setup SlackLaunch EdgeLatch EdgeREG1PRED QCLRREG2PRED QCLRComb.LogicTclk1TCOTdataTclk2Tsu13Setup Slack (contd)Positive slackTiming requirement metNegative slackTiming

11、 requirement not met Setup Slack = Data Required Time Data Arrival Time14Hold SlackREG2.CLKTclk2The margin by which the hold timing requirement is met. It ensures latch data is not corrupted by data from another launch edge. ThCLKREG1.CLKTclk1Data ValidREG2.DTdataData ValidREG1.QTcoHoldSlackLatch Ed

12、geNext Launch EdgeREG1PRED QCLRREG2PRED QCLRComb.LogicTclk1TCOTdataTclk2Th15Hold Slack (contd)Positive slackTiming requirement metNegative slackTiming requirement not met Hold Slack = Data Arrival Time Data Required Time16FPGA/CPLD or ASSPASSP or FPGA/CPLDI/O Analysis Analyzing I/O performance in a

13、synchronous design uses the same slack equationsMust include external device & PCB timing parametersreg1PRED QCLRreg2PRED QCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCData Arrival PathData Arrival PathData Required Path* Represents delay due to capacitive loading17Recovery & RemovalRecovery:The minimum time an

14、 asynchronous signal mustbe stable BEFORE clock edgeRemoval:The minimum time an asynchronous signal mustbe stable AFTER clock edgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC18Asynchronous = Synchronous?Asynchronous control signal source is assumed synchronousSlack equations still applydata arrival path =

15、asynchronous control pathTsu Trec; Th TremExternal device & board timing parameters may be needed (Ex. 1)ASSPreg1PRED QCLRFPGA/CPLDreg2PRED QCLROSCFPGA/CPLDreg1PRED QCLRreg2PRED QCLRExample 1Example 2Data arrival pathData arrival pathData required pathData required path19Why Are These Calculations I

16、mportant?Calculations are important when timing violations occurNeed to be able to understand cause of violationExample causesData path too longRequirement too short (incorrect analysis) Large clock skew signifying a gated clock, etc.TimeQuest timing analyzer uses themEquations to calculate slackTer

17、minology (launch and latch edges, Data Arrival Path, Data Required Path, etc.) in timing reports20Timing Models in DetailQuartus II software models device timing at two PVT conditions by defaultSlow Corner ModelIndicates slowest possible performance for any single pathTiming for slowest device at ma

18、ximum operating temperature and VCCMINFast Corner ModelIndicates fastest possible performance for any single pathTiming for fastest device at minimum operating temperature and VCCMAXWhy two corner timing models?Ensure setup timing is met in slow modelEnsure hold timing is met in fast modelEssential

19、for source synchronous interfacesThird model (slow, min. temp.) available only for 65 nm and smaller technology devices (temperature inversion phenomenon)21Generating Fast/Slow NetlistSpecify one of the default timing models to be used when creating your netlistDefault is the slow timing netlistTo s

20、pecify fast timing netlistUse -fast_model option with create_timing_netlist commandChoose Fast corner in GUI when executing Create Timing Netlist from Netlist menuCANNOT select fast corner from Tasks Pane22Specifying Operating Conditions Perform timing analysis for different delay models without rec

21、reating the existing timing netlistTakes precedence over already generated netlistRequired for selecting slow, min. temp. model and other models (industrial, military, etc.) depending on deviceUse get_available_operating_conditions to see available conditions for target deviceReference DocumentsQuar

22、tus II Handbook, Volume 3, Chapter 7 The Quartus II TimeQuest Timing Analyzer/literature/hb/qts/qts_qii53018.pdfQuick Start Tutorial /literature/hb/qts/ug_tq_tutorial.pdfCookbook/literature/manual/mnl_timequest_cookbook.pdfReference DocumentsSDC and TimeQuest API Reference Manual/literature/manual/m

23、nl_sdctmq.pdfAN 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer/literature/an/an481.pdfAN 433: Constraining and Analyzing Source-Synchronous Interfaces/literature/an/an433.pdf25Instructor-Led TrainingWith Alteras instructor-led training courses, you can: Listen to a lecture from

24、 an Altera technical training engineer (instructor) Complete hands-on exercises with guidance from an Altera instructor Ask questions & receive real-time answers from an Altera instructor Each instructor-led class is one or two days in length (8 working hours per day). Online TrainingWith Alteras online