RF射頻電路設計英文教學課件Lecture09-RFICandSOC

1、1. Interference and Isolation o Existence of Interference in Circuitry o Definition and Measurement of Isolation o Main Path of Interference in a RF Module o Main Path of Interference in a IC Die2. Shielding for a RF Module by a Metallic Shielding Box3. Strong Desirability to Develop RFIC4. Interfer

2、ence Going Along IC Substrate Path o Experimentation o Trench o Guard Ring5. Solution for Interference Coming from the Sky6. Common Grounding Rules for RF Module and RFIC Design o Grounding of Circuit-branches or Blocks in Parallel o DC Power Supply to Circuit-branches or Blocks in Parallel7. Bottle

3、necks in RFIC o Low Q Inductor and Possible Solution o “Zero” Capacitors o Bonding Wires8. Prospect of SOC9. What is Next?Appendixes o Notes about RFIC layout o Calculation of Quarter Wavelength o Progress of Electronic Industry Lecture 9 : RFIC & SOC Richard Chi-Hsi Li 李緝熙Cellular phone: 1391744136

4、3 (PRC) Email : chihsiliLecture 91*第1頁，共48頁。o Existence of Interference in Circuitry1. Interference and Isolationo Definition and Measurement of Isolation Point AInterferenceSourcePCB or IC DiePoint BInterferenceSensorPAPBFigure 1 Definition of isolation between node A and B.AttenuationIsolationIsol

5、ation = - Attenuation of interference. , dB , dB Lecture 92*第2頁，共48頁。o Main Path of Interference in a RF Moduleo Main Path of Interference in a IC Die * From the sky!* From the “ground” - the substrate!Lecture 93*第3頁，共48頁。o Definition and Measurement of Isolation o Main Path of Interference in a RF

6、Moduleo Main Path of Interference in a IC Die Lecture 94*第4頁，共48頁。2 . Schielding for a RF Module by a Metallic Shielding Box Figure 2 Shielding for a RF module PCB of One RF block(Parts and runners are neglected)Metallic shielding boxMain PCBHole for receiving of short stub from PCBPin receiverRunne

7、r on bottom sideShort stubEarPinSlot for receiving the ear of metallic shielding boxSlot for sliding of PCB into metallic shielding boxLecture 95*第5頁，共48頁。3. Strong Desirability to Develop RFICThe great advantages of the IC are: Greatly reduced cost, down by at least 10 times; Greatly reduced size,

8、down more than 1000 times; Greatly enhanced reliability of product, by at least 100 times.Lecture 96*第6頁，共48頁。4. Interference Going Along IC Substrate Path o ExperimentationTo Network Analyzer Port 1 P+N+N+GNDIC die (Vertical profile) P-substrateFigure 3 IC die sample for experiment of interference

9、from substrateN+ P substrateContactP+ GNDDddPoint BInterferenceSensor Point AInterferenceSourceTo Network Analyzer Port 2Lecture 97*第7頁，共48頁。Figure 4 Measured attenuation of interference from source A to sensor B or isolation from sensor B to source A when D 150m, d 50m.Attenuation ofinterference S2

10、1, dB-10-20-40-60-10010 510 710 810 910 1010 6Frequency, Hz-80IsolationFrom sensor to source,-S21, dB1020406010080Table 1 Interference attenuation or isolation when interference signal goes along IC substrate pathS21 - 40 dB, when f =10 MHz, S21 - 30 dB, when f =100 MHz, S21 - 20 dB, when f =1000 MH

11、z, Lecture 98*第8頁，共48頁。o TrenchFigure 5 Trenching of a RF block is to dig a deep ditch encompassing the RF blockMain PCBOne RF blockExternalinterferencesourceIC substrateA deep ditchInternalinterferencesourceLecture 99*第9頁，共48頁。o Guard RingTo Network Analyzer Port 1 P+N+N+GND P-substrate IC die (Ver

12、tical profile) GNDFigure 6 IC die sample for experiment of interference from substrate- Interference source is circled by a P+ guard ring N+ P substrateContactP+ DddPoint BInterferenceSensor Point AInterferenceSourceTo Network Analyzer Port 2P+P+P+ Guard ringP+ Guard ringLecture 910*第10頁，共48頁。Figure

13、 7 Measured attenuation of interference from source A to sensor B or isolation from sensor B to source A when D 150m, d 50mAttenuation ofinterference, S21, dB-10-20-40-60-10010 510 710 810 910 1010 6Frequency, Hz-80IsolationFrom sensor to source,-S21, dB1020406010080With P+ guard ringWithout P+ guar

14、d ringTable 2 Comparison of interference attenuation or isolation between the cases with and without P+ guard ring Without P+ guard ringWith P+ guard ring Frequency S21 - 40 dB, - 80 to - 70 dB, 10 MHz, S21 - 30 dB, - 60 to - 55 dB, 100 MHz, S21 - 20 dB, - 40 dB, 1000 MHz.Lecture 911*第11頁，共48頁。(a) T

15、renching ditch(b) P+ and deep N-well Figure 8 Trenching ditch is replaced by P+ and deep N-wellDeep N-wellP+ guard ringRF blockRF blockTrenching ditchS1=10 mS2=1 mWP=10 mWN=10 m Table 1 Typical width of guard ring and spacing between guard rings in a RFIC layoutItem Value . Spacing between RF block

16、and P+ guard ring,S1 = 10 m,Spacing between P+guard ring and deep N-well,S2 = 1 m, Width of P+ guard ring,WP = 10 m,Width of deep N-well guard ring,WN = 10 m.Lecture 912*第12頁，共48頁。5. Solution for Interference Coming from the SkyG GNDFigure 9 Electric lines either radiated from RFIC die internally or

17、 radiated to RFIC die externally would be terminated on the grounded guard ring.Electric line from insideElectric line from outsideP+ guard ringRFIC- One RF BlockLecture 913*第13頁，共48頁。P+ guard ringFigure 10 Typical width , spacing and connections of P+ and N-well guard ring.N-well guard ringS2=1 mS1

18、=10 mWN=10 mWP=10 mRF Circuit BlockVddGNDLecture 914*第14頁，共48頁。6. Common Grounding Rules for RF Module and RFIC Designo Grounding of Circuit-branches or Blocks in ParallelIC Die or PCBBlock # 3VCO Block #1LNABlock # 2MixerGND (at DC power supply)Figure 11(a) Incorrect grounding connection in series

19、or stacked together Ground ringLecture 915*第15頁，共48頁。IC Die or PCBBlock # 3VCO Block #1LNABlock # 2MixerGND (at DC power supply)Figure 11 (b) Correct grounding connection in parallel or separately Ground ringLecture 916*第16頁，共48頁。o DC Power Supply to Circuit-branches or Blocks in ParallelIC Die or P

20、CBBlock # 3VCO Block #1LNABlock # 2MixerVdd or VCC (at DC power supply)Figure 12 (a) Incorrect DC power supply connection in series or stacked together DC power supply ring (N-well guard ring in IC Die)Lecture 917*第17頁，共48頁。IC Die or PCBBlock # 3VCO Block #1LNABlock # 2MixerVdd or Vcc (at DC power s

21、upply)Figure 12 (b) Correct DC power supply connection in parallel or separately DC power supply ring (N-well guard ring in IC Die)Lecture 918*第18頁，共48頁。7. Bottlenecks in RFIC Designo Low Q Inductor and Possible Solution Figure 13 Spiral configuration of an inductor in IC chipCPoRPCSCPRPCSCPRSLSZiZo

22、Figure 14 Model of a spiral inductorSpiral inductorLecture 919*第19頁，共48頁。 Skin effect* Possible reasons of Low Q value For copper, 0.66 m , when frequency = 10 GHz , 6.6 m , when frequency = 100 MHz. T 0.1 m. (Thickness of the metal layer in IC) Unfortunately, the experiments indicate that the thin

23、thickness of the metal layer is not the main reason that brings about the low Q value of the IC spiral inductor.2) Attenuation due to the Existence of Substrate(Top view)(Side view)Figure 13a Digging of the substrate beneath the spiral wire awayLecture 920*第20頁，共48頁。3) Flux LeakageFigure 13b. Squeez

24、ing of windings so as to reduce the spacing between windings. Lecture 921*第21頁，共48頁。Flux into paperFlux out from paperFigure 15 Cancellation of flux between two windings4) Flux Cancellation Lecture 922*第22頁，共48頁。* Possible Solution of Low Q Value - Compensation of negative resistance LLrQ=L/rFigure

25、16 Change of an inductors Q value by adding of negative resistance into inductor in series.-rr-rQ=L/(r-r)However, it is not so simple in actual engineering design. The difficult points are: Generating a negative resistance; Ensuring that there is not negative resistance outside the expected bandwidt

26、h; The remained negative resistance inside the bandwidth must be kept below a small positive value ; Reducing current consumption of generating negative resistance, which is usually done by an active device; Handling the noise generated due to the existence of the active device.Lecture 923*第23頁，共48頁

27、。o “Zero” Capacitors o Bonding Pad & WiresMetal # 1Metal # 2PassivationPassivationTEOSOxideP - wellN- wellP - wellP+ buriedP+ buriedN+ buried layerP - substrateFigure 16a Bonding pad cross sectionPackage size: 7.5x7.5 mmWire diameter: 1.0 milDie size: 4x4mm. Frequency: 1.8GHz.Simulation Values (Note

28、:Bond Wire Effects are included.) R(mohm) Ls(nH) Lm(nH) CL(pF) Cm(pF)Max 540 1.80 0.36 0.180 0.080Min 400 1.40 0.32 0.120 0.020RRRCmRCmLsLmLmLsLsLsCLCLCLCLBoardDieFigure 16b Example of bonding wires modelLecture 924*第24頁，共48頁。8. Prospect of SOCo Remove All the Bottlenecks in RFIC Design The main bot

29、tlenecks in RFIC design are: Enhancing the low Q value of the spiral inductor; Developing a “zero” capacitor directly on the RFIC chip; Modeling the bonding wire with higher accuracy.o Continue to Study Isolation Studying isolation between RF blocks Studying isolation between digital blocks. Studyin

30、g isolation between RF and digital blocks. Lecture 925*第25頁，共48頁。9. What is Next?SoftwareHardwareHigh data rateResemble Product(RP)20XXs?System on Chip(SOC)Analog ICDigital IC RFIC 19951990s to 20XXsFigure 17 Prospect of a communication system Hardware Hardware-Software SoftwareLNADown-converterDe-M

31、odulatorD to APAUp-converterModulatorA to DControl(SOC)ReceiverServiceI/OTransmitterOSCD to APAA to DControl(RP)ServiceI/OReceiverTransmitterOSCLNALecture 926*第26頁，共48頁。Appendixes o Runner * Length and widthA.1 Notes About RFIC Layout* Multiple runners or curves in parallel Figure A.1 Multiple runne

32、rs or multiple curves in parallel are not welcome.Multiple runners in parallel!Multi curves in parallel!No !No !* Style of runner : As short as possible* Smooth of the runner : As smooth as possible * Placement of runners : Do perpendicular , not parallel as possible* Corner of the runner : As smoot

33、h as possible Lecture 927*第27頁，共48頁。* Runners in parallel ABCDWSrrFigure A.2 Spacing between two runners in parallel.* Runner in parallel with grounded edgeFigure A.3 Spacing between runner and ground surface in parallel.ABWSrgGround surfaceRunnerFigure A.4 Spacing between runner and ground surface

34、in parallel.WSrggGround surfaceRunnerSrggLecture 928*第28頁，共48頁。* Style of runner“Nice looking” - NO!“E-W, S-N” - NO!As short as possible -Yes!ABABFigure A.5 Two runner styles from A to B.* Corner of the runnerRectangular- Lousy!Circular-the best!45o-OK!BABAABFigure A.6 Three different corners of run

35、ner from A to B.Lecture 929*第29頁，共48頁。* Preference of the adjacent runnersIn parallel - Reluctant!Perpendicular - Welcome!CADABCBCDFigure A.7 Draw two adjacent runners in perpendicular, not in parallel* Spacing between adjacent runners(It does not matter for DC runner.)S 3 W - Yes!ABCDWSFigure A.8 S

36、pacing between two runners in parallel.Lecture 930*第30頁，共48頁。* Comparison of even and un-even runnerslABW0ZOZL(a) An even runner : W0= 6 m, Z0= 50.2 ohm, l = 100 m, CDW1W0l/2l/2Z0Z1ZL(b) An uneven runner : W0= 30 m, Z0= 21.2 ohm, l/2 = 50 m, W1= 6 m, Z1= 50.2 ohm, l /2= 50 m, ZC = 48.4 j7.9 ohm ZL=

37、50 + j0 ohmZA = 50 + j0 ohmZL= 50 + j0 ohmAdditional Capacitor:In seriers: -j7.9 ohm = 20.15 8.39 3.47 2.01 pF 1.0 2.4 5.8 10.0 GHzIn parallel: -j7.9 ohm = 20.15 8.39 3.47 2.01 pF 1.0 2.4 5.8 10.0 GHz Figure A.9 Comparison of impedance between even and uneven runnerLecture 931*第31頁，共48頁。* Summary ab

38、out runners Smoothly Perpendicular from each other as possible As short as possibleABZABZ1Z2PFigure A.10 Width of runner changed gradually, not suddenly.* Preference of smooth runnerLecture 932*第32頁，共48頁。 o Parts * Device : Not “dragon”, but square!But square!SourceDrainGateGateSourceDrainFigure A.1

39、1 Devices must be arranged in a “square” but not a “dragon” shape.Lecture 933*第33頁，共48頁。* Inductor : Be care of the coupling!D d1, d2 Add guard ringd2Dd1Cross-talk or coupling!Guard ringFigure A.12 Cross-talk between two inductorsLecture 934*第34頁，共48頁。* capacitor(b) Study of capacitor with high capa

40、citor/area is in progress.Capacitor in RFIC is currently limited by its area, It is ruled less than about 20 pFFigure A.14 Area of capacitor is one of important R & D projects at present* ResistorIn order to enhance the tolerance, . 10 identical resistors connected in parallel to form a resistor10 x

41、 10 kohms1 kohmsFigure A.13 A desired 1 kohms resistor ohm is replaced by 10 resistors in parallel, the value of each resistor being 10 kohms.Lecture 935*第35頁，共48頁。o Parts must be located in a symmetrical way for differential circuit.o Via : The smaller the hole, The higher the inductance and resist

42、ance! o Free space is OK. Dont try to cover all the free space with grounding metal ! Lecture 936*第36頁，共48頁。* Ideal number : 1* Key issue : variable components by means of trimming or variable components by means of switching (Rather than switching, the trimming is to be preferred.)o How many times

43、of tape-out ? DeviceCut!Cut!Cut!GateSourceDrainCut!Cut!Cut!Figure A.15 Variable deviceLecture 937*第37頁，共48頁。 Capacitor ResistorCut!Cut!Cut!(a) Variable capacitor Cut!Cut!Cut!Cut!Cut!Cut!(b) Variable resistor Cut!Cut!Cut!Cut!(c) Variable inductorFigure A.16 Layout of RFIC variable parts InductorLectu

44、re 938*第38頁，共48頁。* Example : Layout for PA +LNA+Antenna SW.Figure A.17 An example of RFIC layout with variable partsLecture 939*第39頁，共48頁。o Pin distributionL/Nr/NNC1NC2N pieces of ViaRunner BRunner AFigure A.18 Equivalent circuit of multi-viao Via * Insert “GND” pad in the middle of differential pai

45、r pads. * Insert “GND” pads between two groups of pads, which correspond to two blocks respectively Lecture 940*第40頁，共48頁。A.2 Calculation of Quarter Wavelength, F/cm nH/cm, F/cm, where Cmsl = Capacitance per unit length in respect to the substrate, W = Width if micro strip line Xint = Thickness of o

46、xide layer, ox = Electric permittivity of the silicon-oxide layer, and Lmsl = Self-inductance per unit length along the runner, Xsi = Thickness of silicon substrateLecture 941*第41頁，共48頁。XintXSiGround planeSilicon SubstrateoxFigure A.19 Various parameters of a micro strip line on silicon substrate.WM

47、icro strip line or runnerOxide layerLecture 942*第42頁，共48頁。 W, m C, pF/cm L, nH/cm Freq, Hz QWL, mm l,5o, m Freq, Hz QWL, mm l,5o, m Freq, Hz QWL, mm l,5o, m Freq, Hz QWL, mm l,5o, m Table A.1 Quarter wavelength (QWL) on RFIC die by CMOS1 1.45 16.59 1.0E+09 16.09 894 2.4E+09 6.71 373 5.8E+09 2.77 154

48、 10.0E+09 1.61 8922.24 15.20 1.0E+09 13.55 753 2.4E+09 5.65 314 5.8E+09 2.34 130 10.0E+09 1.36 75 33.00 14.39 1.0E+09 12.04 669 2.4E+09 5.02 279 5.8E+09 2.08 115 10.0E+09 1.20 67 4 3.73 13.82 1.0E+09 11.01 612 2.4E+09 4.59 255 5.8E+09 1.90 105 10.0E+09 1.10 6154.45 13.37 1.0E+09 10.25 569 2.4E+09 4.

49、27 237 5.8E+09 1.77 98 10.0E+09 1.02 57 10 7.98 11.98 1.0E+09 8.08 449 2.4E+09 3.37 187 5.8E+09 1.39 77 10.0E+09 0.81 4515 11.46 11.17 1.0E+09 6.99 388 2.4E+09 2.91 162 5.8E+09 1.20 67 10.0E+09 0.70 39 20 14.93 10.60 1.0E+09 6.29 349 2.4E+09 2.62 145 5.8E+09 1.08 60 10.0E+09 0.63 35 30 21.84 9.79 1.

50、0E+09 5.41 300 2.4E+09 2.25 125 5.8E+09 0.93 52 10.0E+09 0.54 30 40 28.75 9.21 1.0E+09 4.86 270 2.4E+09 2.02 112 5.8E+09 0.84 47 10.0E+09 0.49 27 50 35.66 8.77 1.0E+09 4.47 248 2.4E+09 1.86 104 5.8E+09 0.77 43 10.0E+09 0.45 25100 70.17 7.38 1.0E+09 3.47 193 2.4E+09 1.45 80 5.8E+09 0.60 33 10.0E+09 0

51、.35 1960 42.56 8.40 1.0E+09 4.18 232 2.4E+09 1.74 97 5.8E+09 0.72 40 10.0E+09 0.42 2375 52.92 7.96 1.0E+09 3.85 214 2.4E+09 1.61 89 5.8E+09 0.66 37 10.0E+09 0.39 21200 139.17 6.00 1.0E+09 2.74 152 2.4E+09 1.14 63 5.8E+09 0.47 26 10.0E+09 0.27 15500 346.18 4.22 1.0E+09 2.07 115 2.4E+09 0.86 48 5.8E+0

52、9 0.36 20 10.0E+09 0.21 11Assuming that Xint=0.5 m, Xsi=500 m, and ox= 3.45x10-13 F/cm, Note: l,5o, m = Length of runner corresponding to phase shift 5o.Lecture 943*第43頁，共48頁。Frequency, GHz 52.57.510005102015QWL, mmW= 1 mW=10mFigure A.20 Quarter wavelength (QWL) vs. FrequencyLecture 944*第44頁，共48頁。9A

53、.3 Progress of Electronic Industry o Evolutiono Why people are focusing on RFIC at present?* Technology for logic or digital IC with low data rate is OK; * Technology for RFIC is still in the development phase; * Technology for logic or digital IC with high data rate must be based on RFIC Technology

54、. Vacuum Tube(VT)1910s to dateSemi-Conductor Device(SC)1940s to dateIntegrated Circuit(IC)1960s to dateSystem on Chip(SOC)Analog ICDigital IC RFIC 19951990s to dateCostSizeCurrentReliabilityFigure A.21 Milestones in history of electronic industryLecture 945*第45頁，共48頁。CompanyMotorolaPhilipsTek/MaximH

55、arrisAD/IBMTechnologyMOSIC-5QB1C1QUICKCHIP-8UHF-1SiGeBiCmos85GST-2C-PIft(NPN)12/12 GHz13 GHz12/27/12 GHz8.6 GHz50 GHzft(PNP)700/50M200MHz8.5G/50M8.5GHz 4GHzStatusProProPro/DevProDevCycle time50 days90 days30-70 days90 days90 daysRiskM-H/M-HML/M-H/L-MM-HM-HM-H$/wafer$1.2k/2kTBD$10kTBD$2kDesign sys.Cadence-QUICKICFASTRACSPICERF ICMC13142SA601/6203600o RFIC developmentTable A.2 Early status of RF IC development (1995 1996)Table A.3 Performance of RF front end IC development (1996)Company(Motorola)(Philips)ChipMC13142*)SA601*)