電信單片機外文翻譯外文文獻(xiàn)英文文獻(xiàn)AT89C51單片機介紹

1、AT89C51單片機介紹Eric S.Roberts 著 陳雄兵 譯描述AT89C51是美國ATMEL公司生產(chǎn)的低電壓，高性能 CM0S8位單片機， 片內(nèi)含4Kbytes的快速可擦寫的只讀程序存儲器（PEROM）和128 bytes的隨 機存取數(shù)據(jù)存儲器（RAM ），器件采用ATMEL公司的高密度、非易失性存儲技 術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn) MCS-51 產(chǎn)品指令系統(tǒng)，片內(nèi)置通用 8 位中央處理器（ CPU） 和 flish 存儲單元，功能強大 AT89C51 單片機可為您提供許多高性價比的應(yīng)用 場合，可靈活應(yīng)用于各種控制領(lǐng)域。主要性能參數(shù)?S-51 產(chǎn)品指令系統(tǒng)完全兼容?4K 字節(jié)可重復(fù)寫 flash

2、 閃速存儲器?1000 次擦寫周期? 靜態(tài)操作： 0HZ24MHZ? 級加密程序存儲器?28*8 字節(jié)內(nèi)部 RAM?32 個可編程 I/O 口?2 個 16 位定時計數(shù)器?6 個中斷源? 編程串行 UART 通道? 功耗空閑和掉電模式AT89C51 提供以下標(biāo)準(zhǔn)功能： 4K 字節(jié) flish 閃速存儲器， 128 字節(jié)內(nèi)部 RAM ， 32 個 I/O 口線，兩個 16位定時計數(shù)器，一個 5 向量兩級中斷結(jié)構(gòu)， 一個全雙工串行通信口，片內(nèi)振蕩器及時鐘電路。同時， AT89C51 可降至 0HZ 的靜態(tài)邏輯操作， 并支持兩種軟件可選的節(jié)電工作模式。 空閑方式停止 CPU 的 工作，但允許 RAM

3、 ，定時計數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方 式保存 RAM 中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個硬件復(fù)位。引腳功能說明Vcc :電源電壓GND:地P0 口： P0 口是一組8位漏極開路型雙向I/O 口，也即地址/數(shù)據(jù)總線復(fù)位 口。作為輸出口用時，每位能吸收電流的方式驅(qū)動8個邏輯門電路，對端口寫“ 1 可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲器或程序存儲器時，這組口線分時轉(zhuǎn)換地址（低8位） 和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。P1 口： P1是一個帶內(nèi)部上拉電阻的8位雙向I/O 口，P1的輸出緩沖級可 驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“

4、 1,通過內(nèi)部的上拉 電阻把端口拉到高電平，此時可做熟出口。做輸出口使用時，因為內(nèi)部存在上 拉電阻，某個引腳被外部信號拉低時會輸出一個電流（Iil）.Flash編程和程序校驗期間，P1接受低8位地址。P2 口： P2是一個帶有內(nèi)部上拉電阻的8位雙向I/O 口，P2的輸出緩沖級 可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對端口寫“ 1,通過內(nèi)部地山 拉電阻把端口拉到高電平，此時可作為輸出口，作輸出口使用時，因為內(nèi)部存 在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（Iil）。在訪問外部程序存儲器獲16位地址的外部數(shù)據(jù)存儲器（例如執(zhí)行 MOVX DPTR指令）時，P2 口送出高8位地址數(shù)據(jù)

5、。在訪問8位地址的外部數(shù)據(jù)存 儲器（如執(zhí)行MOVX RI指令）時，P2 口線上的內(nèi)容（也即特殊功能寄存器（SFR）區(qū)中R2寄存器的內(nèi)容），在整個訪問期間不改變。Flash編程或校驗時，P2亦接受高地址和其它控制信號。P3 口： P3 口是一組帶有內(nèi)部上拉電阻的 8位雙向I/O 口。P3 口輸出緩沖 級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。對P3 口寫入“ 1時，他們 被內(nèi)部上拉電阻拉高并可作為輸出口。 做輸出端時，被外部拉低的P3 口將用上 拉電阻輸出電流（Iil）P3 口除了作為一般的I/O 口線外，更重要的用途是它的 第二功能，如下表所示：端口引腳第二功能接收P3.Orxd （串行

6、輸入口）P3.1txd （串行輸出口）P3.2AintO （外中斷0）P3.3Ai nt1 （外中斷1）P3.4tO （定時/計數(shù)器O）P3.5t1 （定時/計數(shù)器1）P3.6AWR （外部數(shù)據(jù)存儲器寫選通）P3.7ARD （外部數(shù)據(jù)存儲器讀選通）P3于 flash口還 些用 閃速存儲器編程和程序校驗的控制信號。RST:復(fù)位輸入。當(dāng)振蕩器工作時，RST引腳出現(xiàn)兩個機器周期以上高電 平將使單片機復(fù)位。ALE/PROG :當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時，ALE （地址所存允許）輸出脈沖用于所存地址的低8位字節(jié)。即使不訪問外部存儲器，ALE仍以 時鐘振蕩頻率的1/6輸出固定的正脈沖信號，因此它可

7、對外輸出時鐘或用于定 時目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時將跳過一個ALE脈沖。對flash存儲器編程期間，該引腳還用于輸入編程脈沖（APROG）。如有不要，可通過對特殊功能寄存器（SFR）區(qū)中的8EH單元的DO位置 位，可禁止ALE操作。該外置位后，只要一條 MOVX和MOVC指令A(yù)LE才 會被激活。此外，該引腳會被微弱拉高，單片機執(zhí)行外部程序時，應(yīng)設(shè)置 ALE 無效。APSEN：程序存儲允許（APSEN）輸出是外部程序存儲器的讀選通信號， 當(dāng)AT89C51由外部程序存儲器取指令（或數(shù)據(jù)）時，每個機器周期兩個 apsen 有效，即輸出兩個脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲器，這兩次有

8、效的APSEN 信號不出現(xiàn)。EA/VPP:外部訪問允許。欲使 CPU僅訪問外部程序存儲器（地址為OOOOH-FFFFH），EA端必須保持低電平（接地）。需注意的是；如果加密位LB1被編程，復(fù)位時內(nèi)部會鎖存EA端狀態(tài)。女口 EA端為高電平（接VCC端），CPU則執(zhí)行內(nèi)部程序存儲器中的指令。Flash存儲器編程時，該引腳加上+12V的編程允許電源VPP，當(dāng)然這必須 是該器件是使用12V編程電壓VPP.第3頁（共15頁）XTAL1: 振蕩器反相放大器的及內(nèi)部時鐘發(fā)生器的輸出端。XTAL2: 振蕩器反相放大器的輸出端。時鐘振蕩器AT89C51 中有一個用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器， 引腳 XT

9、AL1 和 XTAL2 分別是該放大器的輸入端和輸出端。 這個放大器與作為反饋的片外石 英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器。外接石英晶體（或陶瓷諧振器）及電容C1、C2 接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對外接電容 C1、 C2 雖然沒有十分嚴(yán)格的要求，但電容容 量的大小會輕微影響振蕩頻率的高低、振蕩器的穩(wěn)定性、起振的難易程度及溫 度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30PF+10PF,而如使用陶瓷諧振器建議選擇 40PF+10PF。用戶也可以采用外部時鐘。這種情況下，外部時鐘脈沖接到 XTAL1 端，即 內(nèi)部時鐘發(fā)生器的輸入端， XTAL2 則懸空。由于外部時鐘信號是通過一個

10、 2 分頻觸發(fā)器后作為內(nèi)部時鐘信號的，所以 對外部時鐘信號的占空比沒有特殊要求，但最小高電平持續(xù)時間和最大的低電 平持續(xù)時間應(yīng)符合產(chǎn)品技術(shù)要求?？臻e模式在空閑工作模式狀態(tài)， CPU 保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀 態(tài)，這種方式由軟件產(chǎn)生。此時，片內(nèi) RAM 和所有特殊功能寄存器的內(nèi)容保 持不變。空閑模式可由任何允許的中斷請求或硬件復(fù)位終止。終止空閑工作模式的方法有兩種，其一是任何一條被允許中斷的事件被激 活，即可終止空閑工作模式。程序會首先響應(yīng)中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行 完中斷服務(wù)程序并僅隨終端返回指令，下一條要執(zhí)行的指令就是使單片機進(jìn)入 空閑模式那條指令后面的一條指令。其二是通過

11、硬件復(fù)位也可將空閑工作模式 終止，需要注意的是，當(dāng)由硬件復(fù)位來終止空閑模式時， CPU 通常是從激活空 閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬 件復(fù)位脈沖要保持兩個機器周期（ 24 個時鐘周期）有效，在這種情況下，內(nèi)部 禁止 CPU 訪問片內(nèi) RAM ，而允許訪問其它端口。為了避免可能對端口產(chǎn)生以外寫入，激活空閑模式的那條指令后一條指令不應(yīng)該是一條對端口或外部存儲 器的寫入指令?？臻e和掉電模式外部引腳狀態(tài)模式程序存儲器ALEAPSENPORT0PORT1PORT2PORT3空閑模式內(nèi)部11數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)空閑模式外部11浮空數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式內(nèi)部00數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)

12、數(shù)據(jù)掉電模式外部00浮空數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式在掉電模式下，震蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行 的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出 掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不 改變RAM中的內(nèi)容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保 持一定時間以使振蕩器重啟動并穩(wěn)定工作。程序存儲器的加密：AT89C51可使用對芯片上的3個加密位進(jìn)行編程（P）或 不編程（U）來得到如下表所示的功能：加密位保護(hù)功能表程序加密位保護(hù)類型LB1LB2LB31UUU沒有程序保護(hù)功能2PUU禁止從外部程序存儲器中執(zhí)行MOVC指令讀取內(nèi)

13、部程序存儲器的內(nèi)容3PPU除上表功能外，還禁止程序校驗4PPP除以上功能外，同時禁止外部執(zhí)行當(dāng)加密位LB1被編程時，在復(fù)位期間，EA端的邏輯電平被采樣并鎖存， 如果單片機上電后一直沒有復(fù)位，則鎖存起的初始值是一個隨機數(shù)，且這個隨 機數(shù)會一直保持到真正復(fù)位為止。為使單片機能正常工作，被鎖存的EA電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除FLASH 閃速存儲器的編程AT89C51單片機內(nèi)部有4K字節(jié)的FLASH PEROM,這個FLASH存儲陣列 出廠時已處于擦除狀態(tài)（即所有存儲單元的內(nèi)容均為FFH）,用戶隨時可對其進(jìn) 行編程。編程接口可接收高電平（+12V）或低

14、電平（VCC）的允許編程信號， 低電平編程模式適合于用戶再線編程系統(tǒng), 而高電平編程模式可與通用 EPROM 編程器兼容。AT89C51 單片機中，有些屬于低電壓編程方式，而有些則是高電平編程方 式，用戶可從芯片上的型號和讀取芯片內(nèi)的簽名字節(jié)獲得該信息。AT89C51 的程序存儲器陣列是采用字節(jié)寫入方式編程的，每次寫入一個字 節(jié)，要對整個芯片內(nèi)的 PEROM 程序存儲器寫入一個非空字節(jié)，必須使用片擦 除的方式將整個存儲器的內(nèi)容清除。編程方法編程前，需設(shè)置好地址，數(shù)據(jù)及控制信號， AT89C51 編程方法如下： 1在地址線上加上要編程單元的地址信號。2在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。3激活相應(yīng)的

15、控制信號。4.在高電壓編程方式時，將AEA/VPP端加上+12V編程電壓。5每對 FLASH 存儲陣列寫入一個字節(jié)或每寫入一個程序加密位， 加上一 個 ALE/APROG 編程脈沖，改變編程單元的地址和寫入的數(shù)據(jù)， 重復(fù) 15步驟， 直到全部文件編程結(jié)束。每個字節(jié)寫入周期是自身定時地，通常約為 1.5ms。數(shù)據(jù)查詢： AT89C51 單片機用數(shù)據(jù)查詢方式來檢測一個寫周期是否結(jié)束， 在一個寫周期中，如需要讀取最后寫入的那個字節(jié)，則讀出的數(shù)據(jù)的最高位（P0.7）是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數(shù)據(jù)就會出現(xiàn) 在所有輸出端上，此時，可進(jìn)入下一個字節(jié)的寫周期，寫周期開始后，可在任 意時刻

16、進(jìn)行數(shù)據(jù)查詢。READY/ABUSY :字節(jié)編程的進(jìn)度可通過 “ RDY/ABSY輸出信號監(jiān)測，編 程期間，ALE變?yōu)楦唠娖健癏后P3.4（RDY/ABSY）端電平被拉低，表示正在編程第7頁（共15頁）狀態(tài)（忙狀態(tài)）。編程完成后， P3.4 變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀態(tài)程序校驗：如果加密位 LB1 、LB2 沒有進(jìn)行編程，則代碼數(shù)據(jù)可通過地址 和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)。加密位不可能直接變化。證實加密位的完成通過 觀察它們的特點和能力。芯片擦除：利用控制信號的正確組合并保持ALE/APROG引腳10ms的低電平脈沖寬度即可將 PEROM 陣列（ 4k 字節(jié)）整片擦除，代碼陣列在擦除操作 中將任何非

17、空單元寫入 “1，”這步驟需要再編程之前進(jìn)行。讀片內(nèi)簽名字節(jié)： AT89C51 單片機內(nèi)有 3個簽名字節(jié)，地址為 030H、031H 和032H。用于聲明該器件的廠商、型號和編程電壓。讀簽名字節(jié)的過程和單元 030H、031H和032H的正常校驗相仿，只需將 P3.6和P3.7保持低電平，返回 值意義如下：（030H）=1EH 聲明產(chǎn)品由 ATMEL 公司制造。（031H）=51H聲明為AT89C51單片機。（032H） =FFH 聲明為 12V 編程電壓。（032H） =05H 聲明為 5V 編程電壓。編程接口：采用控制信號的正確組合可對 FLASH 閃速存儲陣列中的每一代 碼字節(jié)進(jìn)行寫入和

18、存儲器的整片擦除，寫操作周期是自身定時的，初始化后它 將自動定時到操作完成。第 # 頁（共 15頁）AT89C51 MCU In troductionAT89C51 MCU In troductionDescriptionThe AT89C51 is a low-power, high-performanee CMOS 8-bit microcomputerwith 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and128 bytes RAM. The device is manufactured u

19、sing Atmel s high density nonvolatilememory tech no logy and is compatible with the in dustry sta ndard MCS-51?instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a mono lithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost

20、 effective soluti on to many embedded con trol applicatio ns.FeaturesCompatible with MCS-51? Products4K Bytes of In-System Reprogrammable Flash MemoryEn dura nee: 1,000 Write/Erase CyclesFully Static Operatio n: 0 Hz to 24 MHzThreeLevel Program Memory Lock128 x 8Bit In ternal RAM32 Programmable I/O

21、LinesTwo 16-Bit Timer/C oun tersSix In terrupt SourcesProgrammable Serial ChannelLow Power Idle and Power Dow n ModesThe AT89C51 provides the followi ng sta ndard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lin es, two 16-bit timer/cou nters, a five vector two-level in terrupt architecture

22、, a full duplex serial port, on-chip oscillator and clock circuitry .In additi on, the AT89C51 is desig ned with static logic for operati on dow n to zero freque ncy and supports two software selectable power sav ing modes. The Idle Mode stops the CPU while allowi ng the RAM, timer/cou nters, serial

23、 port and in terrupt system to con ti nue fun cti oning. The Power Dow n Mode saves the RAM contents but freezes the oscillator disabli ng all other chip fun cti ons un til the n ext hardware reset.Pin DescriptionVCC Supply voltage.GND Grou nd.Port 0:Port 0 is an 8-bit ope n drain bidirect ional I/O

24、 port. As an output port each pin can si nk eight TTL in puts. When is are writte n to port 0 pins, the pins can be used as high impeda nee in puts.Port 0 may also be con figured to be the multiplexed loworder address/databus duri ng accessesto exter nal program and data memory. In this mode P0 has

25、in ternal pullups.Port 0 also receives the code bytes duri ng Flash program ming, and outputs the code bytes duri ng program verificati on. Exter nal pullups are required duri ng program verificati on.Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers

26、can sin k/source four TTL in puts. When 1s are writte n to Port 1 pins they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 1 pins that are externally being pulled low will source curre nt (IIL) because of the in ternal pullups.Port 1 also receives the low-order

27、address bytes duri ng Flash program ming and verificati on.Port 2:Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sin k/source four TTL in puts. When 1s are writte n to Port 2 pins they are pulled high by the internal pullups and can be used as in puts.

28、 As in puts, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte duri ng fetches from exter nal program memory and during accessesto external data memory that use 16-bit addresses (MOVX DPTR). I n this ap

29、plicatio n it uses stro ng internal pull-ups whe n emitti ng 1s. During accesses to exter nal data memory that use 8-bit addresses (MOVX RI), Port2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some con trol sig nals duri ng Flash program

30、ming and verification.Port 3:Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sin k/source four TTL in puts. When 1s are writte n to Port 3 pins they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 3 pins that are ext

31、er nally being pulled low will source curre nt (IIL) because of the pullups.Port 3 also serves the fun cti ons of various special features of the AT89C51 as listed below:Port pinalternate functionsP3.0rxd (serial in put port)P3.1txd (serial output port)P3.29ntO (external in terruptO)P3.39nt1 (extern

32、al in terrupt1)P3.4tO (timerO exter nal in put)P3.5t1 (timer1 exter nal in put)P3.6AWR (external data memory write strobe)P3.7Ard (exter nal data memory read strobe)Port 3 also receives some con trol sig nals for Flash program ming and verificati on.RST:Reset in put. A high on this pin for two mach

33、ine cycles while the oscillator is running resets the device.ALE/PROG : Address Latch Enable output pulse for latching the low byte of the address duri ng accesses to exter nal memory. This pin is also the program pulse input (PROG) duri ng Flash program ming.In normal operation ALE is emitted at a

34、constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri ng each access to exter nal Data Memory.If desired, ALE operatio n can be disabled by sett ing bit 0 of SFR locatio n 8EH. With the bit set, ALE

35、is active only during a MOVX or MOVC in structio n. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microc on troller is in exter nal executi on mode.PSEN: Program Store En able is the read strobe to exter nal program memory.Whe n the AT89C51 is executi ng

36、code from exter nal program memory, PSEN is activated twice each mach ine cycle, except that two PSEN activati ons are skipped duri ng each access to exter nal data memory.EA/VPP:External Access En able. EA must be strapped to GND in order to en able the device to fetch code from exter nal program m

37、emory locati ons start ing at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executio ns.This pin also receives the 12-volt program ming en able voltage(VPP) duri ng Flash program ming, for

38、parts that require 12-volt VPP.XTAL1:I nput to the inverting oscillator amplifier and in put to the in ternal clock operat ing circuit.XTAL2:Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the in put and output, respectively, of an inverting amplifier whi

39、ch can be con figured for use as an on-chip oscillator, as show n in Figure1. Either a quartz crystal or ceramic res on ator may be used. To drive the device from an exter nal clock source, XTAL2 should be left unconn ected while XTAL1 is drive n as show n in Figure 2. There are no requireme nts on

40、the duty cycle of the exter nal clock sig nal, since the in put to the internal clock ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specificatio ns must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the on chip perip

41、herals rema in active. The mode is inv oked by software. The content of the on-chip RAM and all the special fun cti ons registers rema in un cha nged duri ng this mode. The idle mode can be termin ated by any en abled in terrupt or by a hardware reset.It should be no ted that whe n idle is termi nat

42、ed by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes con trol. On-chip hardware in hibits access to internal RAM in this eve nt, but access to the port pi ns is not in hibited. To elimi nate

43、 the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to exter nal memory.Status of External Pins During Idle and Power Down ModesmodeProgram memoryALEApse nPort0Port1

44、Port2Port3idlein ternal11datadatadataDataIdleExternal11floatDatadataDataPower downIn ternal00DataDataDataDataPower downExternal00floatdataDatadataPower Down ModeIn the power dow n mode the oscillator is stopped, and the in structi on that inv okes power dow n is the last in structi on executed. The

45、on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power dow n is a hardware reset. Reset redefi nes the SFRS but does not cha nge the on-chip RAM. The reset should not be activated before VCC is restored to its no rmal operat i

46、ng level and must be held active long eno ugh to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left un programmed (U) or can beprogrammed (P) to obtain the additional features listed in the table below:Lock Bit Protection ModesProg

47、ram lock bitsProtect ion typeLb1Lb2Lb31UUUNo program lock features2PUUMovc in struct ions executed from exter nal program memory are disable from fetching code bytes from internal memory, Aea is sampled and latched on reset, and further program ming of the flash disabled3PPUSame as mode 2, also veri

48、fy is disable.4PPPSame as mode 3, also exter nal executi on is disabled.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a ran dom value, and holds that value un til reset is activa

49、ted. It is n ecessarythat the latched value of EA be in agreement with the current logic level at that pin in order for the device to fun cti on properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready t

50、o be programmedThe programming in terface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C51 in side the user s system, while -tholtlagjh program ming mode is compatible with conven t

51、i onal third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage program ming mode en abled. The respective top-side marki ng and device sig nature codes.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any

52、 nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the en tire memory must be erased using the Chip Erase Mode.Programming AlgorithmBefore program ming the AT89C51, the address, data and con trol sig nals should be set up accordi ng to the Flash program ming mode table a

53、nd Figures 3 and 4. To program the AT89C51, take the followi ng steps.1. In put the desired memory locati on on the address lin es.2. In put the appropriate data byte on the data lin es.3. Activate the correct comb in atio n of con trol sig nals.4. Raise EA/VPP to 12V for the high-voltage program mi

54、ng mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, cha nging the address and data for the en tire array or un til the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of