EDA實(shí)驗(yàn)報(bào)告波形發(fā)生

1、2009-2010第一學(xué)期北京工業(yè)大學(xué)實(shí)驗(yàn)學(xué)院EDA實(shí)驗(yàn)報(bào)告題 目 波形發(fā)生與嵌入式邏輯分析儀 專 業(yè) 電子信息工程 學(xué) 號(hào) 07521203 姓 名 馬艷 成 績 指導(dǎo)教師 2009 CREATEDATE yyyy年MM月dd日 * MERGEFORMAT 年 12 月 6 日一 實(shí)驗(yàn)?zāi)康膶W(xué)習(xí)內(nèi)嵌式邏輯分析工具Signal TabII測試波形功能。達(dá)到檢驗(yàn)設(shè)計(jì)效果和提高分析設(shè)計(jì)過程的能力。二 實(shí)驗(yàn)內(nèi)容與要求利用內(nèi)嵌式邏輯分析工具完成信號(hào)發(fā)生器設(shè)計(jì)及編譯、綜合、適配、仿真和硬件測試，能夠產(chǎn)生正弦波，方波，三角波，鋸齒波。三 實(shí)驗(yàn)平臺(tái)（1）硬件：計(jì)算機(jī)、GX-SOC/SOPC-DEVLAB Cy

2、cloneII EP2C35F672C8核心扳（2）軟件：Quartus II四 實(shí)驗(yàn)原理 嵌入式邏輯分析儀主要分為硬件部分和軟件部分。硬件部分由待測設(shè)計(jì)（DUT），嵌入到FPGA中的ELA IP核、RAM存儲(chǔ)單元以及JTAG接口組成；軟件部分由用戶設(shè)計(jì)軟件和集成在其中的ELA在線調(diào)試軟件組成。五 程序代碼-clkgen.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY clkgen IS PORT(clkin:IN STD_LOGIC ; clkout: OUT STD_LOG

3、IC);END;ARCHITECTURE even OF clkgen ISconstant N:Integer:=16; SIGNAL coun:integer range 0 to N; SIGNAL clk1:STD_LOGIC;BEGIN PROCESS(clkin) BEGIN IF(clkinEVENT AND clkin=1)THEN IF(coun=N)THEN coun=0; clk1=Not clk1; else coun=coun+1; END IF; END IF; END PROCESS; clkout=clk1; END even;-方波library ieee;

4、use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fang2 is port( clk : in std_logic; fd1 : out std_logic_vector(7 downto 0); end; ARCHITECTURE fang OF fang2 IS SIGNAL q:integer range 0 to 1;BEGINPROCESS(clk) BEGIN IF(clkEVENT AND clk=1)THEN qfd1fd1nul

5、l; end case; end process; end architecture;-三角波library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sanj isport(clk: in std_logic; dd3 : out std_logic_vector(7 downto 0) );end;architecture one of sanj isbeginprocess(clk) variable num : std_logi

6、c_vector(7 downto 0);variable ff : std_logic;beginif (clkevent and clk=1) then if ff = 0 then if num=11111000then num:=11111111; ff:=1; else num:=num+8; end if; else if num=00000111 then num:=00000000; ff:=0; else num:=num-8; end if; end if; end if; dd3=num; end process;end;LIBRARY IEEE;USE IEEE.STD

7、_LOGIC_1164.ALL;entity jvchi2 is port(clk,up_down: in std_logic; dd2:out integer range 255 downto 0); end; architecture one of jvchi2 is signal d,temp:integer range 255 downto 0; begin process(clk) begin if(clkevent and clk=1) then if temp198 then temp=temp+2; else temp=0; end if; end if; end proces

8、s; process(temp,up_down) begin if up_down=0 then d=temp; else d=198-temp; end if; end process; dd2=d; end;六 引腳定義及代碼代碼：# Copyright (C) 1991-2008 Altera Corporation# Your use of Altera Corporations design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, an

9、d any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreemen

10、t, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details.# Quartus II: Gen

11、erate Tcl File for Project# File: wave.tcl# Generated on: Thu Nov 12 12:00:52 2009# Load Quartus II Tcl Project packagepackage require :quartus:projectset need_to_close_project 0set make_assignments 1# Check that the right project is openif is_project_open if string compare $quartus(project) wave pu

12、ts Project wave is not openset make_assignments 0 else # Only open if not already openif project_exists wave project_open -revision wave wave else project_new -revision wave waveset need_to_close_project 1# Make assignmentsif $make_assignments set_global_assignment -name FAMILY Cyclone IIset_global_

13、assignment -name DEVICE EP2C35F672C8set_global_assignment -name TOP_LEVEL_ENTITY wavetopset_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.0set_global_assignment -name PROJECT_CREATION_TIME_DATE 11:58:59 NOVEMBER 12, 2009set_global_assignment -name LAST_QUARTUS_VERSION 8.0set_global_assignment -

14、name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palaceset_global_assignment -name DEVICE_FILTER_PACKAGE FBGAset_global_assignment -name DEVICE_FILTER_PIN_COUNT 672set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0set_global_assignm

15、ent -name MAX_CORE_JUNCTION_TEMP 85set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Topset_global_assignment -name PARTITION_COLOR 14622752 -section_id Topset_global_assignment -name LL_ROOT_REGION ON -section_id Root Regionset_global_assignment -name LL_MEMBER_STATE LOCKED -sec

16、tion_id Root Regionset_global_assignment -name BDF_FILE wavetop.bdfset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top# Commit assignmentsexport_assignmentsset_location_assignment PIN_B13 -to clkset_location_assignment PIN_F6 -to switch0set_location_assignment PIN_

17、A21 -to switch1set_location_assignment PIN_B21 -to switch2set_location_assignment PIN_J25 -to dac_abset_location_assignment PIN_J26 -to dac_csset_location_assignment PIN_U26 -to dac_wrset_location_assignment PIN_G21 -to dout0set_location_assignment PIN_E23 -to dout1set_location_assignment PIN_E24 -to dout2set_location_assignment PIN_B24 -to dout3set_location_assi