課件文稿成果fsm

1、VHDL Model of a Finite State Machine BCD to Excess-3 code converter (Mealy) Traffic light controller (Moore) Serial to parallel data converter (Moore)Finite state machine Contains combinational logic Storage elements Edge-triggeredCombinational LogicState Flip FlopsInputsOutputsClockPresent StateNex

2、t State Mealy machine: Output = function of (Present State, Inputs)Moore machine: Output = function (Present State only)BCD to Excess-3 Code Converter Excess-3 code (X3): Add 3 to Binary Coded Decimal (BCD) Input: BCD, Least significant bit (LSB) first Output: Excess-3 code, LSB firstBCDExcess-30000

3、001100010100001001010011011010011100Code ConverterInputOutputCodeConverter00001001Mealy FSMS0S1S2S3S4S5S60/11/00/10/0, 1/11/00/0, 1/11/00/10/0, 1/10/1, 1/0No carryCarry S0: Reset state S1, S3, S5: No carry state S2, S4, S6: Carry state X/Y: Input/OutputTrace on BCD-Excess 3 Code Converter FSMS0S1S2S

4、3S4S5S60/11/00/10/0, 1/11/00/0, 1/11/00/10/0, 1/10/1, 1/0No carryCarry Input: 0110 Output: 1001 States traversed:S0, S1, S4, S6, S0VHDL Model of BCD-X3 FSM (Next State Logic)entity MealyFSM is port (x, reset, clock: in bit;z: out bit );end MealyFSM;architecture RTL of MealyFSM istype s_type is (s0,

5、s1, s2, s3, s4, s5, s6);signal state, nextstate: s_type;BeginstateFSM: process (clock, reset)begin if ( reset = 1 ) then state = s0; elsif ( clockevent and clock = 1) then state = nextstate; end if;end process stateFSM;Defines storage elementRising edge triggeredAsynchronous resetVHDL Model of BCD-X

6、3 FSM (Output Logic)outputFSM: process ( state, x )begin z = 0; nextstate if x = 0 then z = 1; nextstate = s1; else z = 0; nextstate if x = 0 then z = 1; nextstate = s3; else z = 0; nextstate if x = 0 then z = 0; nextstate = s4; else z = 1; nextstate if x = 0 then z = 0; nextstate = s5; else z = 1;

7、nextstate if x = 0 then z = 1; nextstate = s5; else z = 0; nextstate if x = 0 then z = 0; nextstate = s0; else z = 1; nextstate if x = 0 then z = 1; nextstate null; end case;end process outputFSM;end RTL;Output is a combinational function of input and stateSynthesized BCD2X3 ConverterOutputNext stat

8、e logicTraffic Light ControllerStreet a is the main street and street b is the side streetSa=1: Vehicle approaching on street aSb=1: Vehicle approaching on street bLight on a stays green until vehicle on bThen light on b changes green and changes back after 50 secondsIf another car on b and no car o

9、n a then light on b remains green for 10 more secondsWhen a is green remains green for at least 60 secondsTraffic Light ControllerClockSaSbRbGaYaRaYbGbSaSbTraffic Light Controller Moore FSMClock cycle period = 10 secondsSa=1: Vehicle approaching on street aSb=1: Vehicle approaching on street bS0GaRb

10、S1GaRbS2GaRbS3GaRbS4GaRbS5GaRbS12RaYbS11RaGbS10RaGbS9RaGbS8RaGbS7RaGbS6YaRbSbSbSaSbSa+SbTraffic Light Controller VHDL Modelentity traffic_light is port ( clk, Sa , Sb: in bit;Ra, Rb, Ga, Gb, Ya, Yb: out bit );end traffic_light;architecture behave of traffic_light issignal state, nextstate: integer r

11、ange 0 to 12;type light is ( R,Y, G );-signal lightA, lightB: light;beginprocess( clk )beginif ( clkevent and clk = 1 ) thenstate = nextstate;end if;end process;State transition on clock edgeTraffic Light Controller VHDL Model (Cont.)-lightA = R when Ra =1 else Y when Ya = 1 else G when Ga =1;-light

12、B = R when Rb =1 else Y when Yb = 1 else G when Gb =1;process ( state, Sa, Sb )beginRa =0; Rb=0; Ga=0;Gb=0; Ya=0; Yb Ga = 1; Ra=0; Ya=0;Rb = 1;Gb=0;Yb=0; nextstate Ga = 1; Rb=1;if Sb = 1then nextstate Ya = 1; Rb = 1; nextstate Ra =1; Gb =1; nextstate Ra = 1; Gb = 1;if (Sa =1 or Sb =0) then nextstate

13、 Ra = 1; Yb =1; nextstate NULL;end case;end process;end behave;Output and next state logicSerial-to-Parallel Data (S2PD) Converter4-bit serial-to-parallel converterSynchronous reset initializes the state machine from any stateA denotes valid data at input port DZ generates parallel dataSerial-to-Par

14、allel data converterClockADDoneZRS2PD Converter Moore FSMR: ResetA: Valid dataS3S4S2S0S5RS1RRRRRR & AR + AR + AR & ARRS2PD Converter VHDL Modelentity spdc is port ( clk, R , A, D: in bit;Z: out bit_vector ( 3 downto 0 ) ; Done: out bit );end spdc;architecture fsm_rtl of spdc istype state_type is ( S

15、0, S1, S2, S3, S4, S5 );signal state: state_type;signal shift_reg: bit_vector ( 3 downto 0 );beginprocess ( state )begincase state iswhen s0 to s4 = Done Done = 1; Z if R = 1 or A = 0 then state = S0;elsif R = 0 and A = 1 then state shift_reg = D & shift_reg ( 3 downto 1 );if R = 0 then state = S2;

16、elsif R = 1 then state shift_reg = D & shift_reg ( 3 downto 1 );if R = 0 then state = S3; elsif R = 1 then state shift_reg = D & shift_reg ( 3 downto 1 );if R = 0 then state = S4; elsif R = 1 then state shift_reg = D & shift_reg ( 3 downto 1 );if R = 0 then state = S5; elsif R = 1 then state if R =

17、0 and A = 1 then state = S1;elsif R = 1 or A = 0 then state NULL;end case; end if;end process;end fsm_rtl;Output and next state logicVHDL Modeling of FSMsController design shouldAvoid asynchronous feedback, race conditionsSplit large countersInitialize design to a known stateMinimize number of latch

18、esFull specify all signals in a combinational processA flow-through latch is implied when a signal or variable in a combinational process is not fully specifiedPrefer case over IF-THEN-ELSEIF statement operates on a priority encoded basisHWDesign a controller to dispense a package of gum when 25 cents are deposited. The machine has a single coin slot and only accepts, quarters, dimes and nickels (no pennies). Further, the machine accepts exact amount only (i.e. it does not give out change).Draw the state machine. Identif